Re: [PATCH] tee: optee: fix build error caused by recent optee tracepoints feature
Hi Jens, Am Di., 6. Apr. 2021 um 14:30 Uhr schrieb Jens Wiklander : > > Hi Heiko, > > [+Arnd] > > On Tue, Apr 6, 2021 at 12:38 PM Heiko Thiery wrote: > > > > Hi Jens, > > > > Am Di., 30. März 2021 um 10:26 Uhr schrieb Jens Wiklander > > : > > > > > > On Thu, Mar 25, 2021 at 12:06:01PM +0800, Jisheng Zhang wrote: > > > > If build kernel without "O=dir", below error will be seen: > > > > > > > > In file included from drivers/tee/optee/optee_trace.h:67, > > > > from drivers/tee/optee/call.c:18: > > > > ./include/trace/define_trace.h:95:42: fatal error: ./optee_trace.h: No > > > > such file or directory > > > >95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE) > > > > | ^ > > > > compilation terminated. > > > > > > > > Fix it by adding below line to Makefile: > > > > CFLAGS_call.o := -I$(src) > > > > > > > > Tested with and without "O=dir", both can build successfully. > > > > > > > > Reported-by: Guenter Roeck > > > > Suggested-by: Steven Rostedt > > > > Signed-off-by: Jisheng Zhang > > > > > > I've picked up this. > > > > For what tree did you pick this? I still see this build failure on the > > latest next tree (next-20210401). > > The next tree hasn't been updated since 1th of April so it's not > unexpected. The fix is supposed to be on its way to > https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=arm/drivers > , I can't see it there yet though. Ah I see. Now it has been landed in the actual next tree. Thank you, Heiko
Re: [PATCH] tee: optee: fix build error caused by recent optee tracepoints feature
Hi Jens, Am Di., 30. März 2021 um 10:26 Uhr schrieb Jens Wiklander : > > On Thu, Mar 25, 2021 at 12:06:01PM +0800, Jisheng Zhang wrote: > > If build kernel without "O=dir", below error will be seen: > > > > In file included from drivers/tee/optee/optee_trace.h:67, > > from drivers/tee/optee/call.c:18: > > ./include/trace/define_trace.h:95:42: fatal error: ./optee_trace.h: No such > > file or directory > >95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE) > > | ^ > > compilation terminated. > > > > Fix it by adding below line to Makefile: > > CFLAGS_call.o := -I$(src) > > > > Tested with and without "O=dir", both can build successfully. > > > > Reported-by: Guenter Roeck > > Suggested-by: Steven Rostedt > > Signed-off-by: Jisheng Zhang > > I've picked up this. For what tree did you pick this? I still see this build failure on the latest next tree (next-20210401). > > Thanks, > Jens Thank you, Heiko
Re: [PATCH] tee: optee: fix build error caused by recent optee tracepoints feature
> If build kernel without "O=dir", below error will be seen:
>
> In file included from drivers/tee/optee/optee_trace.h:67,
> from drivers/tee/optee/call.c:18:
> ./include/trace/define_trace.h:95:42: fatal error: ./optee_trace.h: No such
> file or directory
>95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
> | ^
> compilation terminated.
>
> Fix it by adding below line to Makefile:
> CFLAGS_call.o := -I$(src)
>
> Tested with and without "O=dir", both can build successfully.
>
> Reported-by: Guenter Roeck
> Suggested-by: Steven Rostedt
> Signed-off-by: Jisheng Zhang
Fixes: 0101947dbcc3 ("tee: optee: add invoke_fn tracepoints")
Tested-by: Heiko Thiery
> ---
> drivers/tee/optee/Makefile | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/tee/optee/Makefile b/drivers/tee/optee/Makefile
> index 56263ae3b1d7..3aa33ea9e6a6 100644
> --- a/drivers/tee/optee/Makefile
> +++ b/drivers/tee/optee/Makefile
> @@ -6,3 +6,6 @@ optee-objs += rpc.o
> optee-objs += supp.o
> optee-objs += shm_pool.o
> optee-objs += device.o
> +
> +# for tracing framework to find optee_trace.h
> +CFLAGS_call.o := -I$(src)
> --
> 2.31.0
>
Thank you.
--
Heiko
Re: [PATCH v2 2/2] mtd: spi-nor: add initial sysfs support
Hi Michael,
Am Di., 23. März 2021 um 15:34 Uhr schrieb Michael Walle :
>
> Add support to show the name and JEDEC identifier as well as to dump the
> SFDP table. Not all flashes list their SFDP table contents in their
> datasheet. So having that is useful. It might also be helpful in bug
> reports from users.
>
> Signed-off-by: Michael Walle
Tested-by: Heiko Thiery
> ---
> drivers/mtd/spi-nor/Makefile | 2 +-
> drivers/mtd/spi-nor/core.c | 5 +++
> drivers/mtd/spi-nor/core.h | 3 ++
> drivers/mtd/spi-nor/sysfs.c | 86
> 4 files changed, 95 insertions(+), 1 deletion(-)
> create mode 100644 drivers/mtd/spi-nor/sysfs.c
>
> diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
> index 653923896205..aff308f75987 100644
> --- a/drivers/mtd/spi-nor/Makefile
> +++ b/drivers/mtd/spi-nor/Makefile
> @@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -spi-nor-objs := core.o sfdp.o
> +spi-nor-objs := core.o sfdp.o sysfs.o
> spi-nor-objs += atmel.o
> spi-nor-objs += catalyst.o
> spi-nor-objs += eon.o
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index fbc34158a883..02523ddac612 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -3708,6 +3708,10 @@ static int spi_nor_probe(struct spi_mem *spimem)
> if (ret)
> return ret;
>
> + ret = spi_nor_sysfs_create(nor);
> + if (ret)
> + return ret;
> +
> return mtd_device_register(>mtd, data ? data->parts : NULL,
>data ? data->nr_parts : 0);
> }
> @@ -3717,6 +3721,7 @@ static int spi_nor_remove(struct spi_mem *spimem)
> struct spi_nor *nor = spi_mem_get_drvdata(spimem);
>
> spi_nor_restore(nor);
> + spi_nor_sysfs_remove(nor);
>
> /* Clean up MTD stuff. */
> return mtd_device_unregister(>mtd);
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 08d2469837da..599035200a03 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -486,4 +486,7 @@ static struct spi_nor __maybe_unused
> *mtd_to_spi_nor(struct mtd_info *mtd)
> return mtd->priv;
> }
>
> +int spi_nor_sysfs_create(struct spi_nor *nor);
> +void spi_nor_sysfs_remove(struct spi_nor *nor);
> +
> #endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
> diff --git a/drivers/mtd/spi-nor/sysfs.c b/drivers/mtd/spi-nor/sysfs.c
> new file mode 100644
> index ..c62cc4d6bce6
> --- /dev/null
> +++ b/drivers/mtd/spi-nor/sysfs.c
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "core.h"
> +
> +static ssize_t name_show(struct device *dev,
> +struct device_attribute *attr, char *buf)
> +{
> + struct spi_device *spi = to_spi_device(dev);
> + struct spi_mem *spimem = spi_get_drvdata(spi);
> + struct spi_nor *nor = spi_mem_get_drvdata(spimem);
> +
> + return sysfs_emit(buf, "%s\n", nor->info->name);
> +}
> +static DEVICE_ATTR_RO(name);
> +
> +static ssize_t jedec_id_show(struct device *dev,
> +struct device_attribute *attr, char *buf)
> +{
> + struct spi_device *spi = to_spi_device(dev);
> + struct spi_mem *spimem = spi_get_drvdata(spi);
> + struct spi_nor *nor = spi_mem_get_drvdata(spimem);
> +
> + return sysfs_emit(buf, "%*phN\n", nor->info->id_len, nor->info->id);
> +}
> +static DEVICE_ATTR_RO(jedec_id);
> +
> +static struct attribute *spi_nor_sysfs_entries[] = {
> + _attr_name.attr,
> + _attr_jedec_id.attr,
> + NULL
> +};
> +
> +static ssize_t sfdp_read(struct file *filp, struct kobject *kobj,
> +struct bin_attribute *bin_attr, char *buf,
> +loff_t off, size_t count)
> +{
> + struct spi_device *spi = to_spi_device(kobj_to_dev(kobj));
> + struct spi_mem *spimem = spi_get_drvdata(spi);
> + struct spi_nor *nor = spi_mem_get_drvdata(spimem);
> + struct sfdp *sfdp = nor->sfdp;
> + size_t sfdp_size = sfdp->num_dwords * sizeof(*sfdp->dwords);
> +
> + return memory_read_from_buffer(buf, count, , nor->sfdp->dwords,
> + sfdp_size);
> +}
> +static BIN_ATTR_RO(sfdp, 0);
> +
> +static struct bin_attribute *spi_nor_sysfs_bin_entries[] = {
> + _attr_sfdp,
> + NULL
> +}
Re: [PATCH v2 1/2] mtd: spi-nor: sfdp: save a copy of the SFDP data
Hi Michael, Am Di., 23. März 2021 um 19:45 Uhr schrieb Michael Walle : > > Am 23. März 2021 18:37:17 MEZ schrieb Pratyush Yadav : > >On 23/03/21 03:31PM, Michael Walle wrote: > >> Due to possible mode switching to 8D-8D-8D, it might not be possible > >to > >> read the SFDP after the initial probe. To be able to dump the SFDP > >via > >> sysfs afterwards, make a complete copy of it. > >> > >> Signed-off-by: Michael Walle > > > >Reviewed-by: Pratyush Yadav Tested-by: Heiko Thiery > > thanks for reviewing! > > -michael > > __ > Linux MTD discussion mailing list > http://lists.infradead.org/mailman/listinfo/linux-mtd/
[PATCH v2] arm64: dts: imx8mq-kontron-pitx-imx8m: pass phy reset delays
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 10us (T4) and
'reset-deassert-us' to 280us (T1+T3).
Without these reset delays the board will hang during startup when
bootargs has ip=dhcp set.
Fixes: 1dc7f3d79a1a ("arm64: dts: fsl: add support for Kontron pitx-imx8m
board")
Signed-off-by: Heiko Thiery
---
v2:
- add desciption what issue will be fixed
- add Fixes tag
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
index 91a9ceb10305..f593e4ff62e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -90,6 +90,8 @@ ethphy0: ethernet-phy@0 {
ti,tx-internal-delay = ;
ti,fifo-depth = ;
reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <280>;
};
};
};
--
2.30.0
[PATCH] arm64: dts: imx8mq-kontron-pitx-imx8m: pass phy reset delays
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 10us (T4) and
'reset-deassert-us' to 280us (T1+T3).
Signed-off-by: Heiko Thiery
---
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
index 91a9ceb10305..f593e4ff62e1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -90,6 +90,8 @@ ethphy0: ethernet-phy@0 {
ti,tx-internal-delay = ;
ti,fifo-depth = ;
reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10>;
+ reset-deassert-us = <280>;
};
};
};
--
2.30.0
[PATCH v3] arm64: configs: Enable PCIe support for imx8mq boards
Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. The driver only has build-in support and cannot be compiled as module. Signed-off-by: Heiko Thiery --- v2: - slightly modified the commit message (Fabio Estevam) v3: - add comment in the commit message to clarify why the driver has to be build as built-in arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 72ba52ad5a3c..54445b936066 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m +CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y -- 2.30.0
Re: [PATCH v2] arm64: configs: Enable PCIe support for imx8mq boards
Hi Shawn, Am Mi., 17. März 2021 um 12:52 Uhr schrieb Heiko Thiery : > > Hi Shawn, > > Am Mi., 17. März 2021 um 09:02 Uhr schrieb Shawn Guo : > > > > On Thu, Mar 11, 2021 at 08:27:47PM +0100, Heiko Thiery wrote: > > > Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, > > > imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. > > > > > > Signed-off-by: Heiko Thiery > > > --- > > > v2: > > > - slightly modified the commit message (Fabio Estevam) > > > > > > arch/arm64/configs/defconfig | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > > index 1f673b00c5f5..522bae6a8f21 100644 > > > --- a/arch/arm64/configs/defconfig > > > +++ b/arch/arm64/configs/defconfig > > > @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y > > > CONFIG_PCI_HOST_THUNDER_ECAM=y > > > CONFIG_PCIE_ROCKCHIP_HOST=m > > > CONFIG_PCIE_BRCMSTB=m > > > +CONFIG_PCI_IMX6=y > > > > Do we really want it to be built-in? If so, it would be nice to have some > > comments about that in commit log. Or do you mean why it cannot be enabled as a module? The PCI_IMX6 driver is only a bool option in the Kconfig and cannot be built as a module. So it is required to have it built-in. > > Why would you not want it? I see other SOC PCI controllers are also > enabled. I would like to have it because we have an Intel e1000 on our > pitx-imx8m board and the seconds PCI slot is for a m.2 card. So we > would have the PCI support with the default defconfig. On the NXP > imx8mq EVK a m.2 is connected to the PCI interface. > > Is this the kind of comments you want? > > > Shawn > > > > > CONFIG_PCI_LAYERSCAPE=y > > > CONFIG_PCIE_LAYERSCAPE_GEN4=y > > > CONFIG_PCI_HISI=y > > > -- > > > 2.30.0 > > > > > BR > -- > Heiko > -- > Heiko
Re: [PATCH v2] arm64: configs: Enable PCIe support for imx8mq boards
Hi Shawn, Am Mi., 17. März 2021 um 09:02 Uhr schrieb Shawn Guo : > > On Thu, Mar 11, 2021 at 08:27:47PM +0100, Heiko Thiery wrote: > > Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, > > imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. > > > > Signed-off-by: Heiko Thiery > > --- > > v2: > > - slightly modified the commit message (Fabio Estevam) > > > > arch/arm64/configs/defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > index 1f673b00c5f5..522bae6a8f21 100644 > > --- a/arch/arm64/configs/defconfig > > +++ b/arch/arm64/configs/defconfig > > @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y > > CONFIG_PCI_HOST_THUNDER_ECAM=y > > CONFIG_PCIE_ROCKCHIP_HOST=m > > CONFIG_PCIE_BRCMSTB=m > > +CONFIG_PCI_IMX6=y > > Do we really want it to be built-in? If so, it would be nice to have some > comments about that in commit log. Why would you not want it? I see other SOC PCI controllers are also enabled. I would like to have it because we have an Intel e1000 on our pitx-imx8m board and the seconds PCI slot is for a m.2 card. So we would have the PCI support with the default defconfig. On the NXP imx8mq EVK a m.2 is connected to the PCI interface. Is this the kind of comments you want? > Shawn > > > CONFIG_PCI_LAYERSCAPE=y > > CONFIG_PCIE_LAYERSCAPE_GEN4=y > > CONFIG_PCI_HISI=y > > -- > > 2.30.0 > > BR -- Heiko -- Heiko
[PATCH v2] arm64: configs: Enable PCIe support for imx8mq boards
Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. Signed-off-by: Heiko Thiery --- v2: - slightly modified the commit message (Fabio Estevam) arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1f673b00c5f5..522bae6a8f21 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m +CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y -- 2.30.0
Re: [PATCH] arm64: configs: Enable PCIe support for imx8mq boards
Hi all, Added some more to the CC list since they could be interested in this. Am Mo., 8. März 2021 um 13:58 Uhr schrieb Heiko Thiery : > > Hi all, > > Am Mo., 8. März 2021 um 10:03 Uhr schrieb Heiko Thiery > : > > > > Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, > > imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. This increases the image > > by 64k. > > The growth of 64k is not right. > > Using the support script shows: > > $ scripts/bloat-o-meter vmlinux vmlinux.with_pci > add/remove: 22/2 grow/shrink: 2/0 up/down: 8338/-16 (8322) > Function old new delta > imx6_pcie_probe-1804 +1804 > imx6_pcie_deassert_core_reset -1356 +1356 > imx6_pcie_of_match -1200 +1200 > imx6_pcie_start_link - 692+692 > imx6_pcie_suspend_noirq- 528+528 > imx6_pcie_init_phy - 496+496 > imx6_pcie_host_init- 336+336 > imx6_pcie_assert_core_reset- 332+332 > pcie_phy_write - 272+272 > imx6_pcie_driver - 200+200 > imx6_pcie_pm_ops - 184+184 > pcie_phy_read - 168+168 > imx6_pcie_resume_noirq - 156+156 > pcie_phy_wait_ack - 140+140 > pcie_phy_poll_ack.isra - 124+124 > imx6_pcie_quirk- 124+124 > drvdata- 60 +60 > dw_pcie_ops 208 264 +56 > imx6_pcie_init - 40 +40 > imx6_pcie_shutdown - 32 +32 > imx6_pcie_host_ops - 16 +16 > e843419@0d4b_0001256e_27c4 - 8 +8 > e843419@0590_7810_4f0 - 8 +8 > vermagic 76 82 +6 > e843419@0c2e_0001064f_80 8 - -8 > e843419@0633_8212_13c 8 - -8 > Total: Before=21884381, After=21892703, chg +0.04% > > > > Signed-off-by: Heiko Thiery > > --- > > arch/arm64/configs/defconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > index d612f633b771..4b7b4a8f1860 100644 > > --- a/arch/arm64/configs/defconfig > > +++ b/arch/arm64/configs/defconfig > > @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y > > CONFIG_PCI_HOST_THUNDER_ECAM=y > > CONFIG_PCIE_ROCKCHIP_HOST=m > > CONFIG_PCIE_BRCMSTB=m > > +CONFIG_PCI_IMX6=y > > CONFIG_PCI_LAYERSCAPE=y > > CONFIG_PCIE_LAYERSCAPE_GEN4=y > > CONFIG_PCI_HISI=y > > -- > > 2.30.0 > > -- Heiko
Re: [PATCH] arm64: configs: Enable PCIe support for imx8mq boards
Hi all, Am Mo., 8. März 2021 um 10:03 Uhr schrieb Heiko Thiery : > > Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, > imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. This increases the image > by 64k. The growth of 64k is not right. Using the support script shows: $ scripts/bloat-o-meter vmlinux vmlinux.with_pci add/remove: 22/2 grow/shrink: 2/0 up/down: 8338/-16 (8322) Function old new delta imx6_pcie_probe-1804 +1804 imx6_pcie_deassert_core_reset -1356 +1356 imx6_pcie_of_match -1200 +1200 imx6_pcie_start_link - 692+692 imx6_pcie_suspend_noirq- 528+528 imx6_pcie_init_phy - 496+496 imx6_pcie_host_init- 336+336 imx6_pcie_assert_core_reset- 332+332 pcie_phy_write - 272+272 imx6_pcie_driver - 200+200 imx6_pcie_pm_ops - 184+184 pcie_phy_read - 168+168 imx6_pcie_resume_noirq - 156+156 pcie_phy_wait_ack - 140+140 pcie_phy_poll_ack.isra - 124+124 imx6_pcie_quirk- 124+124 drvdata- 60 +60 dw_pcie_ops 208 264 +56 imx6_pcie_init - 40 +40 imx6_pcie_shutdown - 32 +32 imx6_pcie_host_ops - 16 +16 e843419@0d4b_0001256e_27c4 - 8 +8 e843419@0590_7810_4f0 - 8 +8 vermagic 76 82 +6 e843419@0c2e_0001064f_80 8 - -8 e843419@0633_8212_13c 8 - -8 Total: Before=21884381, After=21892703, chg +0.04% > Signed-off-by: Heiko Thiery > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index d612f633b771..4b7b4a8f1860 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y > CONFIG_PCI_HOST_THUNDER_ECAM=y > CONFIG_PCIE_ROCKCHIP_HOST=m > CONFIG_PCIE_BRCMSTB=m > +CONFIG_PCI_IMX6=y > CONFIG_PCI_LAYERSCAPE=y > CONFIG_PCIE_LAYERSCAPE_GEN4=y > CONFIG_PCI_HISI=y > -- > 2.30.0 > -- Heiko
[PATCH] arm64: configs: Enable PCIe support for imx8mq boards
Enable PCI_IMX6 to get PCI support for imx8mq boards like imx8mq-evk, imx8mq-kontron-pitx-imx8m and imx8mq-zii-ultra. This increases the image by 64k. Signed-off-by: Heiko Thiery --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f633b771..4b7b4a8f1860 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -225,6 +225,7 @@ CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m +CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y -- 2.30.0
[PATCH v4 0/2] add Kontron pITX-imx8m board
This patch series adds support for the Kontron pITX-imx8m board: https://www.kontron.com/products/boards-and-standard-form-factors/single-board-computer/pitx-imx8m.html Heiko Thiery (2): dt-bindings: arm: fsl: add Kontron pITX-imx8m board arm64: dts: fsl: add support for Kontron pitx-imx8m board .../devicetree/bindings/arm/fsl.yaml | 1 + arch/arm64/boot/dts/freescale/Makefile| 1 + .../freescale/imx8mq-kontron-pitx-imx8m.dts | 611 ++ 3 files changed, 613 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts -- 2.30.0
Re: [PATCH] usb: dwc3: Fix dereferencing of null dwc->usb_psy
Hi all,
> On Wed, Mar 3, 2021 at 6:00 PM Colin King wrote:
>>
>> From: Colin Ian King
>>
>> Currently the null check logic on dwc->usb_psy is inverted as it allows
>> calls to power_supply_put with a null dwc->usb_psy causing a null
>> pointer dereference. Fix this by removing the ! operator.
>>
>> Addresses-Coverity: ("Dereference after null check")
>> Fixes: 59fa3def35de ("usb: dwc3: add a power supply for current control")
>
> Acked-by: Ray Chi
>
>> Signed-off-by: Colin Ian King
Tested-by: Heiko Thiery
>> ---
>> drivers/usb/dwc3/core.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index d15f065849cd..94fdbe502ce9 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -1628,7 +1628,7 @@ static int dwc3_probe(struct platform_device *pdev)
>> assert_reset:
>> reset_control_assert(dwc->reset);
>>
>> - if (!dwc->usb_psy)
>> + if (dwc->usb_psy)
>> power_supply_put(dwc->usb_psy);
>>
>> return ret;
>> @@ -1653,7 +1653,7 @@ static int dwc3_remove(struct platform_device *pdev)
>> dwc3_free_event_buffers(dwc);
>> dwc3_free_scratch_buffers(dwc);
>>
>> - if (!dwc->usb_psy)
>> + if (dwc->usb_psy)
>> power_supply_put(dwc->usb_psy);
>>
>> return 0;
>> --
>> 2.30.0
>>
Thank you.
--
Heiko
[PATCH v4 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
Signed-off-by: Heiko Thiery
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Michael Walle
---
v2:
- bring root nodes in alphabetical order
- remove pinctrl_gpio_keys for pciewake
- remove pinctrl_sai2 and pinctrl_spdfif1 since it is not used yet
Thanks to Michael Walle:
- add pinctrl for regulator-v-3v3-sd
- add name for regulator swbst
- add comment about currently unused audio codec
- put usb_phy entry in correct alphabetical order
Thanks to Krzysztof Kozlowski:
- use generic names for pcie-refclk, tpm, fan-controller, sensor
- remove empty line
- fix group name to match schema (ecspi2cs -> ecspi2csgrp)
v3:
Thanks to Michael Walle:
- set compatible as first in regulator-v-3v3-sd node
- remove audio-codec@1a node
Thanks to Krzysztof Kozlowski:
- use more generic name for pcie reference clock
v4:
Thanks to Fabio Estevam:
- rename regulator node
- remove tpm-reset node
- remove usb-hub-reset
- use reset-gpios for ethernet phy instead of phy-reset-gpios
- remove disable-gpio and ext_osc property from pcie0
- remove ext_osc property from pcie1
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../freescale/imx8mq-kontron-pitx-imx8m.dts | 611 ++
2 files changed, 612 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..9fc2c6f64407 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
new file mode 100644
index ..91a9ceb10305
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include
+
+/ {
+ model = "Kontron pITX-imx8m";
+ compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ mmc0 =
+ mmc1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ spi0 =
+ spi1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ pcie0_refclk: pcie0-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ pcie1_refclk: pcie1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2>;
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <2>;
+ enable-active-high;
+ };
+};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_ecspi2 _ecspi2_cs>;
+ cs-gpios = < 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670";
+ reg = <0>;
+ spi-max-frequency = <4300>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = ;
+ ti,tx-internal-d
[PATCH v4 1/2] dt-bindings: arm: fsl: add Kontron pITX-imx8m board
Add the Kontron pITX-imx8m board. Signed-off-by: Heiko Thiery Reviewed-by: Krzysztof Kozlowski --- v2: - bring in correct alphabetical order v3: - no change v4: - no change Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..6d121bc9af8d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -733,6 +733,7 @@ properties: - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board - fsl,imx8mq-evk# i.MX8MQ EVK Board - google,imx8mq-phanbell# Google Coral Edge TPU + - kontron,pitx-imx8m# Kontron pITX-imx8m Board - purism,librem5-devkit # Purism Librem5 devkit - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk -- 2.30.0
Re: [PATCH 0/2] an additional path to control charging current
Hi Ray, > Currently, VBUS draw callback does no action when the > generic PHYs are used. The patches add an additional path > to control charging current through power supply property > POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT. > > Ray Chi (2): > usb: dwc3: add a power supply for current control > usb: dwc3: add an alternate path in vbus_draw callback While using next-20210303 this patchset leads to the following kernel crash on my board: 8< [1.392084] VFIO - User Level meta-driver version: 0.3 [1.398370] Unable to handle kernel NULL pointer dereference at virtual address 03a0 [1.407552] Mem abort info: [1.410479] ESR = 0x9604 [1.413668] EC = 0x25: DABT (current EL), IL = 32 bits [1.419217] SET = 0, FnV = 0 [1.422413] EA = 0, S1PTW = 0 [1.425690] Data abort info: [1.428705] ISV = 0, ISS = 0x0004 [1.432715] CM = 0, WnR = 0 [1.435821] [03a0] user address but active_mm is swapper [1.442458] Internal error: Oops: 9604 [#1] PREEMPT SMP [1.448274] Modules linked in: [1.451469] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.12.0-rc1-next-20210303-5-g090e892099db #126 [1.461269] Hardware name: Kontron pITX-imx8m (DT) [1.466268] pstate: 6005 (nZCv daif -PAN -UAO -TCO BTYPE=--) [1.472538] pc : devm_power_supply_get_by_phandle+0xe4/0x148 [1.478455] lr : dwc3_probe+0xbac/0xfa0 [1.482462] sp : 800011f1bb00 [1.485918] x29: 800011f1bb00 x28: [1.491467] x27: 800011681078 x26: 8000115d048c [1.497016] x25: c089ea00 x24: 0003 [1.502564] x23: c089ea00 x22: 800011b89948 [1.508112] x21: 0003 x20: fdfb [1.513660] x19: c03f1080 x18: 00c0 [1.519209] x17: x16: [1.524757] x15: fc001000 x14: [1.530306] x13: x12: 0030 [1.535853] x11: 0101010101010101 x10: 800011f1ba50 [1.541402] x9 : ff784c70 x8 : 0010 [1.546950] x7 : c03a5590 x6 : 0080 [1.552498] x5 : c0098000 x4 : 03a0 [1.558047] x3 : 800011cb2dc8 x2 : [1.563596] x1 : 0001 x0 : [1.569146] Call trace: [1.571700] devm_power_supply_get_by_phandle+0xe4/0x148 [1.577248] dwc3_probe+0xbac/0xfa0 [1.580890] platform_probe+0x68/0xd8 [1.584719] really_probe+0xe4/0x3c0 [1.588454] driver_probe_device+0x58/0xb8 [1.592733] device_driver_attach+0x74/0x80 [1.597100] __driver_attach+0x58/0xe0 [1.601016] bus_for_each_dev+0x74/0xc8 [1.605020] driver_attach+0x24/0x30 [1.608753] bus_add_driver+0x184/0x1e8 [1.612758] driver_register+0x64/0x120 [1.616764] __platform_driver_register+0x28/0x38 [1.621675] dwc3_driver_init+0x1c/0x28 [1.625684] do_one_initcall+0x74/0x1d0 [1.629691] kernel_init_freeable+0x1d4/0x23c [1.634240] kernel_init+0x14/0x118 [1.637885] ret_from_fork+0x10/0x30 [1.641624] Code: 88027c01 35a2 17fffe96 f9800091 (885f7c82) [1.647992] ---[ end trace c6e48cea897d0b0d ]--- [1.652833] Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b [1.660822] SMP: stopping secondary CPUs [1.664921] Kernel Offset: disabled [1.668560] CPU features: 0x00240002,2000200c [1.673106] Memory Limit: none [1.676296] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x000b ]--- 8< After reverting these 2 patches the problem is gone. -- Heiko
Re: [PATCH 0/2] an additional path to control charging current
Hi, Am Mi., 3. März 2021 um 16:01 Uhr schrieb Heiko Thiery : > > Hi Ray, > > > > Currently, VBUS draw callback does no action when the > > generic PHYs are used. The patches add an additional path > > to control charging current through power supply property > > POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT. > > > > Ray Chi (2): > > usb: dwc3: add a power supply for current control > > usb: dwc3: add an alternate path in vbus_draw callback > > While using next-20210303 this patchset leads to the following kernel crash > on my board: > > 8< > > [1.392084] VFIO - User Level meta-driver version: 0.3 > [1.398370] Unable to handle kernel NULL pointer dereference at virtual > address 03a0 > [1.407552] Mem abort info: > [1.410479] ESR = 0x9604 > [1.413668] EC = 0x25: DABT (current EL), IL = 32 bits > [1.419217] SET = 0, FnV = 0 > [1.422413] EA = 0, S1PTW = 0 > [1.425690] Data abort info: > [1.428705] ISV = 0, ISS = 0x0004 > [1.432715] CM = 0, WnR = 0 > [1.435821] [03a0] user address but active_mm is swapper > [1.442458] Internal error: Oops: 9604 [#1] PREEMPT SMP > [1.448274] Modules linked in: > [1.451469] CPU: 1 PID: 1 Comm: swapper/0 Not tainted > 5.12.0-rc1-next-20210303-5-g090e892099db #126 > [1.461269] Hardware name: Kontron pITX-imx8m (DT) > [1.466268] pstate: 6005 (nZCv daif -PAN -UAO -TCO BTYPE=--) > [1.472538] pc : devm_power_supply_get_by_phandle+0xe4/0x148 > [1.478455] lr : dwc3_probe+0xbac/0xfa0 > [1.482462] sp : 800011f1bb00 > [1.485918] x29: 800011f1bb00 x28: > [1.491467] x27: 800011681078 x26: 8000115d048c > [1.497016] x25: c089ea00 x24: 0003 > [1.502564] x23: c089ea00 x22: 800011b89948 > [1.508112] x21: 0003 x20: fdfb > [1.513660] x19: c03f1080 x18: 00c0 > [1.519209] x17: x16: > [1.524757] x15: fc001000 x14: > [1.530306] x13: x12: 0030 > [1.535853] x11: 0101010101010101 x10: 800011f1ba50 > [1.541402] x9 : ff784c70 x8 : 0010 > [1.546950] x7 : c03a5590 x6 : 0080 > [1.552498] x5 : c0098000 x4 : 03a0 > [1.558047] x3 : 800011cb2dc8 x2 : > [1.563596] x1 : 0001 x0 : > [1.569146] Call trace: > [1.571700] devm_power_supply_get_by_phandle+0xe4/0x148 > [1.577248] dwc3_probe+0xbac/0xfa0 > [1.580890] platform_probe+0x68/0xd8 > [1.584719] really_probe+0xe4/0x3c0 > [1.588454] driver_probe_device+0x58/0xb8 > [1.592733] device_driver_attach+0x74/0x80 > [1.597100] __driver_attach+0x58/0xe0 > [1.601016] bus_for_each_dev+0x74/0xc8 > [1.605020] driver_attach+0x24/0x30 > [1.608753] bus_add_driver+0x184/0x1e8 > [1.612758] driver_register+0x64/0x120 > [1.616764] __platform_driver_register+0x28/0x38 > [1.621675] dwc3_driver_init+0x1c/0x28 > [1.625684] do_one_initcall+0x74/0x1d0 > [1.629691] kernel_init_freeable+0x1d4/0x23c > [1.634240] kernel_init+0x14/0x118 > [1.637885] ret_from_fork+0x10/0x30 > [1.641624] Code: 88027c01 35a2 17fffe96 f9800091 (885f7c82) > [1.647992] ---[ end trace c6e48cea897d0b0d ]--- > [1.652833] Kernel panic - not syncing: Attempted to kill init! > exitcode=0x000b > [1.660822] SMP: stopping secondary CPUs > [1.664921] Kernel Offset: disabled > [1.668560] CPU features: 0x00240002,2000200c > [1.673106] Memory Limit: none > [1.676296] ---[ end Kernel panic - not syncing: Attempted to kill init! > exitcode=0x000b ]--- > > > 8< This fixes the crash. diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d15f065849cd..94fdbe502ce9 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1628,7 +1628,7 @@ static int dwc3_probe(struct platform_device *pdev) assert_reset: reset_control_assert(dwc->reset); - if (!dwc->usb_psy) + if (dwc->usb_psy) power_supply_put(dwc->usb_psy); return ret; @@ -1653,7 +1653,7 @@ static int dwc3_remove(struct platform_device *pdev) dwc3_free_event_buffers(dwc); dwc3_free_scratch_buffers(dwc); - if (!dwc->usb_psy) + if (dwc->usb_psy) power_supply_put(dwc->usb_psy); return 0; -- Heiko
Re: [PATCH v2 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Fabio,
Am Di., 2. März 2021 um 15:43 Uhr schrieb Fabio Estevam :
>
> Hi Heiko,
>
> On Mon, Feb 22, 2021 at 11:08 AM Heiko Thiery wrote:
>
> > + reg_usdhc2_vmmc: regulator-v-3v3-sd {
>
> reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
I used the same name as used on imx8mq-evk. Do you think a better name
is the one you proposed?
> > + tpm_reset: tpm-reset {
> > + compatible = "gpio-reset";
>
> I don't see this compatible string documented.
This comes from the linux-imx tree [1]. Nethertheless the reset seems
not to be used by the tpm driver for the infineon chip.
[1]
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/reset/gpio-reset.c?h=imx_5.4.70_2.3.0
So I think I can remove it here.
>
> > + reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <2>;
> > + reset-post-delay-ms = <60>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + usb_hub_reset: usb-hub-reset {
> > + compatible = "gpio-reset";
>
> Same here.
Also the usb-hub-reset can be removed.
>
> > + {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_fec1>;
> > + phy-mode = "rgmii-id";
> > + phy-handle = <>;
> > + phy-reset-gpios = < 11 GPIO_ACTIVE_LOW>;
>
> This property is deprecated. Please consider using reset-gpios inside
> ethernet-phy instead.
Done
> > + /* TODO: configure audio, as of now just put a placeholder */
> > + wm8904: audio-codec@1a {
> > + compatible = "wlf,wm8904";
> > + reg = <0x1a>;
> > + clocks = < IMX8MQ_CLK_SAI2_ROOT>;
> > + clock-names = "mclk";
> > + clock-frequency = <2400>;
>
> Not a valid property.
The whole node is removed since v3.
> > +/* M.2 B-key slot */
> > + {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pcie0>;
> > + disable-gpio = < 29 GPIO_ACTIVE_LOW>;
>
> Not a valid property.
This comes from the linux-imx tree [2]. but in mainline it is not
valid. So I will remove it.
[2]
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/pci/controller/dwc/pci-imx6.c?h=imx_5.4.70_2.3.0#n2436
> > + reset-gpio = < 9 GPIO_ACTIVE_LOW>;
> > + clocks = < IMX8MQ_CLK_PCIE1_ROOT>,
> > +< IMX8MQ_CLK_PCIE1_AUX>,
> > +< IMX8MQ_CLK_PCIE1_PHY>,
> > +<_refclk>;
> > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > + ext_osc = <1>;
>
> Not a valid property.
This comes from the linux-imx tree [3]. but in mainline it is not
valid. So I will remove it.
[3]
https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/pci/controller/dwc/pci-imx6.c?h=imx_5.4.70_2.3.0#n2422
> > +/* Intel Ethernet Controller I210/I211 */
> > + {
> > + clocks = < IMX8MQ_CLK_PCIE2_ROOT>,
> > +< IMX8MQ_CLK_PCIE2_AUX>,
> > +< IMX8MQ_CLK_PCIE2_PHY>,
> > +<_refclk>;
> > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > + ext_osc = <1>;
>
> Not a valid property.
same as commented before.
Thank you for the review. I will prepare v4.
--
Heiko
Re: [PATCH v2 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
Hi all,
Am Do., 25. Feb. 2021 um 22:15 Uhr schrieb Heiko Thiery
:
>
> When accessing the timecounter register on an i.MX8MQ the kernel hangs.
> This is only the case when the interface is down. This can be reproduced
> by reading with 'phc_ctrl eth0 get'.
>
> Like described in the change in 91c0d987a9788dcc5fe26baafd73bf9242b68900
> the igp clock is disabled when the interface is down and leads to a
> system hang.
>
> So we check if the ptp clock status before reading the timecounter
> register.
>
> Signed-off-by: Heiko Thiery
Sorry for the noise. But just realized that I sent a v3 version of the
patch but forgot to update the subject line (still v2). Should I
resend it with the correct subject?
> ---
> v2:
> - add mutex (thanks to Richard)
>
> v3:
> I did a mistake and did not test properly
> - add parenteses
> - fix the used variable
>
> drivers/net/ethernet/freescale/fec_ptp.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/net/ethernet/freescale/fec_ptp.c
> b/drivers/net/ethernet/freescale/fec_ptp.c
> index 2e344aada4c6..1753807cbf97 100644
> --- a/drivers/net/ethernet/freescale/fec_ptp.c
> +++ b/drivers/net/ethernet/freescale/fec_ptp.c
> @@ -377,9 +377,16 @@ static int fec_ptp_gettime(struct ptp_clock_info *ptp,
> struct timespec64 *ts)
> u64 ns;
> unsigned long flags;
>
> + mutex_lock(>ptp_clk_mutex);
> + /* Check the ptp clock */
> + if (!adapter->ptp_clk_on) {
> + mutex_unlock(>ptp_clk_mutex);
> + return -EINVAL;
> + }
> spin_lock_irqsave(>tmreg_lock, flags);
> ns = timecounter_read(>tc);
> spin_unlock_irqrestore(>tmreg_lock, flags);
> + mutex_unlock(>ptp_clk_mutex);
>
> *ts = ns_to_timespec64(ns);
>
> --
> 2.30.0
>
[PATCH v2 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
When accessing the timecounter register on an i.MX8MQ the kernel hangs.
This is only the case when the interface is down. This can be reproduced
by reading with 'phc_ctrl eth0 get'.
Like described in the change in 91c0d987a9788dcc5fe26baafd73bf9242b68900
the igp clock is disabled when the interface is down and leads to a
system hang.
So we check if the ptp clock status before reading the timecounter
register.
Signed-off-by: Heiko Thiery
---
v2:
- add mutex (thanks to Richard)
v3:
I did a mistake and did not test properly
- add parenteses
- fix the used variable
drivers/net/ethernet/freescale/fec_ptp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/freescale/fec_ptp.c
b/drivers/net/ethernet/freescale/fec_ptp.c
index 2e344aada4c6..1753807cbf97 100644
--- a/drivers/net/ethernet/freescale/fec_ptp.c
+++ b/drivers/net/ethernet/freescale/fec_ptp.c
@@ -377,9 +377,16 @@ static int fec_ptp_gettime(struct ptp_clock_info *ptp,
struct timespec64 *ts)
u64 ns;
unsigned long flags;
+ mutex_lock(>ptp_clk_mutex);
+ /* Check the ptp clock */
+ if (!adapter->ptp_clk_on) {
+ mutex_unlock(>ptp_clk_mutex);
+ return -EINVAL;
+ }
spin_lock_irqsave(>tmreg_lock, flags);
ns = timecounter_read(>tc);
spin_unlock_irqrestore(>tmreg_lock, flags);
+ mutex_unlock(>ptp_clk_mutex);
*ts = ns_to_timespec64(ns);
--
2.30.0
[PATCH v2 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
When accessing the timecounter register on an i.MX8MQ the kernel hangs. This is only the case when the interface is down. This can be reproduced by reading with 'phc_ctrl eth0 get'. Like described in the change in 91c0d987a9788dcc5fe26baafd73bf9242b68900 the igp clock is disabled when the interface is down and leads to a system hang. So we check if the ptp clock status before reading the timecounter register. Signed-off-by: Heiko Thiery --- v2: - add mutex (thanks to Richard) drivers/net/ethernet/freescale/fec_ptp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c index 2e344aada4c6..22f5e800c2d7 100644 --- a/drivers/net/ethernet/freescale/fec_ptp.c +++ b/drivers/net/ethernet/freescale/fec_ptp.c @@ -377,9 +377,15 @@ static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) u64 ns; unsigned long flags; + mutex_lock(>ptp_clk_mutex); + /* Check the ptp clock */ + if (!adapter->ptp_clk_on) + mutex_unlock(>ptp_clk_mutex); + return -EINVAL; spin_lock_irqsave(>tmreg_lock, flags); ns = timecounter_read(>tc); spin_unlock_irqrestore(>tmreg_lock, flags); + mutex_unlock(>ptp_clk_mutex); *ts = ns_to_timespec64(ns); -- 2.30.0
Re: [PATCH 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
Hi Richard, Am Do., 25. Feb. 2021 um 14:49 Uhr schrieb Heiko Thiery : > > Hi Richard, > > Am Di., 23. Feb. 2021 um 17:11 Uhr schrieb Richard Cochran > : > > > > On Tue, Feb 23, 2021 at 04:04:16PM +0100, Heiko Thiery wrote: > > > It is not only the PHC clock that stops. Rather, it is the entire > > > ethernet building block in the SOC that is disabled, including the > > > PHC. > > > > Sure, but why does the driver do that? > > That is a good question. I tried to understand the clock > infrastructure of the imx8 but it looks quite complicated. I cannot > find the point where all the stuff is disabled. But the explanation why it is currently disabled that way can be found in the commit 91c0d987a9788dcc5fe26baafd73bf9242b68900. -- Heiko
Re: [PATCH 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
Hi Richard, Am Di., 23. Feb. 2021 um 17:11 Uhr schrieb Richard Cochran : > > On Tue, Feb 23, 2021 at 04:04:16PM +0100, Heiko Thiery wrote: > > It is not only the PHC clock that stops. Rather, it is the entire > > ethernet building block in the SOC that is disabled, including the > > PHC. > > Sure, but why does the driver do that? That is a good question. I tried to understand the clock infrastructure of the imx8 but it looks quite complicated. I cannot find the point where all the stuff is disabled. -- Heiko
Re: next/master bisection: baseline.login on r8a77960-ulcb
Hi all, Am Do., 25. Feb. 2021 um 12:50 Uhr schrieb Thierry Reding : > > On Thu, Feb 25, 2021 at 11:14:57AM +, Robin Murphy wrote: > > On 2021-02-25 11:09, Thierry Reding wrote: > > > On Wed, Feb 24, 2021 at 10:39:42PM +0100, Heiko Thiery wrote: > > > > Hi Christoph and all, > > > > > > > > On 23.02.21 10:56, Guillaume Tucker wrote: > > > > > Hi Christoph, > > > > > > > > > > Please see the bisection report below about a boot failure on > > > > > r8a77960-ulcb on next-20210222. > > > > > > > > > > Reports aren't automatically sent to the public while we're > > > > > trialing new bisection features on kernelci.org but this one > > > > > looks valid. > > > > > > > > > > The log shows a kernel panic, more details can be found here: > > > > > > > > > > https://kernelci.org/test/case/id/6034bde034504edc9faddd2c/ > > > > > > > > > > Please let us know if you need any help to debug the issue or try > > > > > a fix on this platform. > > > > > > > > I am also seeing this problem on an iMX8MQ board and can help test if > > > > you > > > > have a fix. > > > > > > This is also causing boot failures on Jetson AGX Xavier. The origin is > > > slightly different from the above kernelci.org report, but the BUG_ON is > > > the same: > > > > > > [2.650447] [ cut here ] > > > [2.650588] kernel BUG at include/linux/iommu-helper.h:23! > > > [2.650729] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP > > > [2.654330] Modules linked in: > > > [2.657474] CPU: 2 PID: 67 Comm: kworker/2:1 Not tainted > > > 5.11.0-next-20210225-00025-gfd15609b3a81-dirty #120 > > > [2.667367] Hardware name: NVIDIA Jetson AGX Xavier Developer Kit > > > (DT) > > > [2.674096] Workqueue: events deferred_probe_work_func > > > [2.679169] pstate: 40400089 (nZcv daIf +PAN -UAO -TCO BTYPE=--) > > > [2.684949] pc : find_slots.isra.0+0x118/0x2f0 > > > [2.689494] lr : find_slots.isra.0+0x88/0x2f0 > > > [2.693696] sp : 800011faf950 > > > [2.697281] x29: 800011faf950 x28: 0001 > > > [2.702537] x27: 0001 x26: > > > [2.708131] x25: 0001 x24: 000105f03148 > > > [2.713556] x23: 0001 x22: 800011559000 > > > [2.718835] x21: 800011559a80 x20: edc0 > > > [2.724493] x19: x18: 0020 > > > [2.729770] x17: 0003ffd7d160 x16: 0068 > > > [2.735173] x15: 80b43150 x14: > > > [2.740944] x13: 82b5d791 x12: 0040 > > > [2.746113] x11: a248 x10: > > > [2.751882] x9 : x8 : 0003fed3 > > > [2.757139] x7 : x6 : > > > [2.762818] x5 : x4 : > > > [2.767984] x3 : 0001e8303148 x2 : 8000 > > > [2.773580] x1 : x0 : 001db800 > > > [2.778662] Call trace: > > > [2.781136] find_slots.isra.0+0x118/0x2f0 > > > [2.785137] swiotlb_tbl_map_single+0x80/0x1b4 > > > [2.789858] swiotlb_map+0x58/0x200 > > > [2.793355] dma_direct_map_page+0x148/0x1c0 > > > [2.797386] dma_map_page_attrs+0x2c/0x54 > > > [2.801411] dw_pcie_host_init+0x40c/0x4c0 > > > [2.805633] tegra_pcie_config_rp+0x7c/0x1f4 > > > [2.810155] tegra_pcie_dw_probe+0x3d0/0x60c > > > [2.814185] platform_probe+0x68/0xe0 > > > [2.817688] really_probe+0xe4/0x4c0 > > > [2.821362] driver_probe_device+0x58/0xc0 > > > [2.825386] __device_attach_driver+0xa8/0x104 > > > [2.829953] bus_for_each_drv+0x78/0xd0 > > > [2.833434] __device_attach+0xdc/0x17c > > > [2.837631] device_initial_probe+0x14/0x20 > > > [2.841680] bus_probe_device+0x9c/0xa4 > > > [2.845160] deferred_probe_work_func+0x74/0xb0 > > > [2.849734] process_one_work+0x1cc/0x350 > > > [2.853822] work
Re: next/master bisection: baseline.login on r8a77960-ulcb
Hi Christoph and all, On 23.02.21 10:56, Guillaume Tucker wrote: Hi Christoph, Please see the bisection report below about a boot failure on r8a77960-ulcb on next-20210222. Reports aren't automatically sent to the public while we're trialing new bisection features on kernelci.org but this one looks valid. The log shows a kernel panic, more details can be found here: https://kernelci.org/test/case/id/6034bde034504edc9faddd2c/ Please let us know if you need any help to debug the issue or try a fix on this platform. I am also seeing this problem on an iMX8MQ board and can help test if you have a fix. BR -- Heiko
Re: [PATCH 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
Hi Richard, Am Di., 23. Feb. 2021 um 15:27 Uhr schrieb Richard Cochran : > > On Tue, Feb 23, 2021 at 09:00:32AM +0100, Heiko Thiery wrote: > > HI Jakub, > > > > Am Di., 23. Feb. 2021 um 04:00 Uhr schrieb Jakub Kicinski : > > > Why is the PTP interface registered when it can't be accessed? > > > > > > Perhaps the driver should unregister the PTP clock when it's brought > > > down? > > I don't see any reason why a clock should stop ticking just because > the interface is down. This is a poor driver design, but sadly it > gets copied and even defended. It is not only the PHC clock that stops. Rather, it is the entire ethernet building block in the SOC that is disabled, including the PHC. > > Good question, but I do not know what happens e.g. with linuxptp when > > the device that was opened before will be gone. > > If a network interface goes down, ptp4l will notice via rtnl and close > the interface. Then it re-opens the sockets on rtnl up. However, the > file descriptor representing the dynamic posix clock stays opened. Thanks, -- Heiko
Re: [PATCH 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
HI Jakub, Am Di., 23. Feb. 2021 um 04:00 Uhr schrieb Jakub Kicinski : > > On Sat, 20 Feb 2021 07:56:55 +0100 Heiko Thiery wrote: > > When accessing the timecounter register on an i.MX8MQ the kernel hangs. > > This is only the case when the interface is down. This can be reproduced > > by reading with 'phc_ctrl eth0 get'. > > > > Like described in the change in 91c0d987a9788dcc5fe26baafd73bf9242b68900 > > the igp clock is disabled when the interface is down and leads to a > > system hang. > > > > So we check if the ptp clock status before reading the timecounter > > register. > > > > Signed-off-by: Heiko Thiery > > Please widen the CC list, you should CC Richard on PTP patches. > > > diff --git a/drivers/net/ethernet/freescale/fec_ptp.c > > b/drivers/net/ethernet/freescale/fec_ptp.c > > index 2e344aada4c6..c9882083da02 100644 > > --- a/drivers/net/ethernet/freescale/fec_ptp.c > > +++ b/drivers/net/ethernet/freescale/fec_ptp.c > > @@ -377,6 +377,9 @@ static int fec_ptp_gettime(struct ptp_clock_info *ptp, > > struct timespec64 *ts) > > u64 ns; > > unsigned long flags; > > > > + /* Check the ptp clock */ > > Comment is rather redundant. Drop it or say _when_ ptp_clk_on may not > be true. I just used the same comment as the one in the fec_ptp_settime() function. > > > + if (!adapter->ptp_clk_on) > > + return -EINVAL; > > Why is the PTP interface registered when it can't be accessed? > > Perhaps the driver should unregister the PTP clock when it's brought > down? Good question, but I do not know what happens e.g. with linuxptp when the device that was opened before will be gone. Maybe Richard can give a hint. > > > spin_lock_irqsave(>tmreg_lock, flags); > > ns = timecounter_read(>tc); > > spin_unlock_irqrestore(>tmreg_lock, flags); -- Heiko
[PATCH v3 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
Signed-off-by: Heiko Thiery
Reviewed-by: Krzysztof Kozlowski
---
v2:
- bring root nodes in alphabetical order
- remove pinctrl_gpio_keys for pciewake
- remove pinctrl_sai2 and pinctrl_spdfif1 since it is not used yet
Thanks to Michael Walle:
- add pinctrl for regulator-v-3v3-sd
- add name for regulator swbst
- add comment about currently unused audio codec
- put usb_phy entry in correct alphabetical order
Thanks to Krzysztof Kozlowski:
- use generic names for pcie-refclk, tpm, fan-controller, sensor
- remove empty line
- fix group name to match schema (ecspi2cs -> ecspi2csgrp)
v3:
Thanks to Michael Walle:
- set compatible as first in regulator-v-3v3-sd node
- remove audio-codec@1a node
Thanks to Krzysztof Kozlowski:
- use more generic name for pcie reference clock
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../freescale/imx8mq-kontron-pitx-imx8m.dts | 632 ++
2 files changed, 633 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..9fc2c6f64407 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
new file mode 100644
index ..2069f8439b40
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include
+
+/ {
+ model = "Kontron pITX-imx8m";
+ compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ mmc0 =
+ mmc1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ spi0 =
+ spi1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ pcie0_refclk: pcie0-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ pcie1_refclk: pcie1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ reg_usdhc2_vmmc: regulator-v-3v3-sd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2>;
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <2>;
+ enable-active-high;
+ };
+
+ tpm_reset: tpm-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+ reset-post-delay-ms = <60>;
+ #reset-cells = <0>;
+ };
+
+ usb_hub_reset: usb-hub-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <3000>;
+ reset-post-delay-ms = <50>;
+ #reset-cells = <0>;
+ };
+};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_ecspi2 _ecspi2_cs>;
+ cs-gpios = < 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670";
+ reg = <0>;
+ resets = <_reset>;
+ spi-max-frequency = <4300>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ phy-reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+
[PATCH v3 1/2] dt-bindings: arm: fsl: add Kontron pITX-imx8m board
Add the Kontron pITX-imx8m board. Signed-off-by: Heiko Thiery Reviewed-by: Krzysztof Kozlowski --- v2: - bring in correct alphabetical order v3: - no change Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..6d121bc9af8d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -733,6 +733,7 @@ properties: - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board - fsl,imx8mq-evk# i.MX8MQ EVK Board - google,imx8mq-phanbell# Google Coral Edge TPU + - kontron,pitx-imx8m# Kontron pITX-imx8m Board - purism,librem5-devkit # Purism Librem5 devkit - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk -- 2.30.0
[PATCH v3 0/2] add Kontron pITX-imx8m board
This patch series adds support for the Kontron pITX-imx8m board: https://www.kontron.com/products/boards-and-standard-form-factors/single-board-computer/pitx-imx8m.html Heiko Thiery (2): dt-bindings: arm: fsl: add Kontron pITX-imx8m board arm64: dts: fsl: add support for Kontron pitx-imx8m board .../devicetree/bindings/arm/fsl.yaml | 1 + arch/arm64/boot/dts/freescale/Makefile| 1 + .../freescale/imx8mq-kontron-pitx-imx8m.dts | 632 ++ 3 files changed, 634 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts -- 2.30.0
Re: [PATCH 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Krzysztof,
Am Mo., 22. Feb. 2021 um 19:39 Uhr schrieb Krzysztof Kozlowski
:
>
> On Mon, 22 Feb 2021 at 10:09, Heiko Thiery wrote:
> > > > > > +
> > > > > > + pcie0_refclk: pcie0-refclk {
> > > > >
> > > > > Generic node names (from the dt spec candidate is "clock").
> > > >
> > > > Should I simply set the node name to pcie0-clock? And pcie1-clock for
> > > > the next one?
> > >
> > > I am fine with "pcie0-clock" or just "clock-0".
> >
> > I saw now that in "imx8mq-zii-ultra.dtsi" the name
> > "clock-pcie0-refclk" is used. Can I use the same?
>
> It's not that generic anymore - but specific, but it's also not that
> important, so go ahead.
For me it is no problem to change this to pcie0-clock and pcie1-clock.
I need to make a new version anyway.
--
Heiko
Re: [PATCH v2 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Michael,
Am Mo., 22. Feb. 2021 um 16:15 Uhr schrieb Michael Walle :
>
> Am 2021-02-22 15:07, schrieb Heiko Thiery:
> > The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
> >
> > Signed-off-by: Heiko Thiery
> > ---
> > v2:
> > - bring root nodes in alphabetical order
> > - remove pinctrl_gpio_keys for pciewake
> > - remove pinctrl_sai2 and pinctrl_spdfif1 since it is not used yet
> >
> > Thanks to Michael Walle:
> > - add pinctrl for regulator-v-3v3-sd
> > - add name for regulator swbst
> > - add comment about currently unused audio codec
> > - put usb_phy entry in correct alphabetical order
> >
> > Thanks to Krzysztof Kozlowski:
> > - use generic names for pcie-refclk, tpm, fan-controller, sensor
> > - remove empty line
> > - fix group name to match schema (ecspi2cs -> ecspi2csgrp)
> >
> >
> > arch/arm64/boot/dts/freescale/Makefile| 1 +
> > .../freescale/imx8mq-kontron-pitx-imx8m.dts | 641 ++
> > 2 files changed, 642 insertions(+)
> > create mode 100644
> > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 6438db3822f8..9fc2c6f64407 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
> > diff --git
> > a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > new file mode 100644
> > index 0000..82364e394ed2
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > @@ -0,0 +1,641 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree File for the Kontron pitx-imx8m board.
> > + *
> > + * Copyright (C) 2021 Heiko Thiery
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mq.dtsi"
> > +#include
> > +
> > +/ {
> > + model = "Kontron pITX-imx8m";
> > + compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
> > +
> > + aliases {
> > + i2c0 =
> > + i2c1 =
> > + i2c2 =
> > + mmc0 =
> > + mmc1 =
> > + serial0 =
> > + serial1 =
> > + serial2 =
> > + spi0 =
> > + spi1 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial2:115200n8";
> > + };
> > +
> > + pcie0_refclk: clock-pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <1>;
> > + };
> > +
> > + pcie1_refclk: clock-pcie1-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <1>;
> > + };
> > +
> > + reg_usdhc2_vmmc: regulator-v-3v3-sd {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_reg_usdhc2>;
> > + compatible = "regulator-fixed";
>
> compatible comes first
Ups. I will fix that.
> > + regulator-name = "V_3V3_SD";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + gpio = < 19 GPIO_ACTIVE_HIGH>;
> > + off-on-delay-us = <2>;
> > + enable-active-high;
> > + };
> > +
> > + tpm_reset: tpm-reset {
> > + compatible = "gpio-reset";
> > + reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <2>;
> > + reset-post-delay-ms = <60>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + usb_
[PATCH v2 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
Signed-off-by: Heiko Thiery
---
v2:
- bring root nodes in alphabetical order
- remove pinctrl_gpio_keys for pciewake
- remove pinctrl_sai2 and pinctrl_spdfif1 since it is not used yet
Thanks to Michael Walle:
- add pinctrl for regulator-v-3v3-sd
- add name for regulator swbst
- add comment about currently unused audio codec
- put usb_phy entry in correct alphabetical order
Thanks to Krzysztof Kozlowski:
- use generic names for pcie-refclk, tpm, fan-controller, sensor
- remove empty line
- fix group name to match schema (ecspi2cs -> ecspi2csgrp)
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../freescale/imx8mq-kontron-pitx-imx8m.dts | 641 ++
2 files changed, 642 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..9fc2c6f64407 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
new file mode 100644
index ..82364e394ed2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -0,0 +1,641 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include
+
+/ {
+ model = "Kontron pITX-imx8m";
+ compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ mmc0 =
+ mmc1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ spi0 =
+ spi1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ pcie0_refclk: clock-pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ pcie1_refclk: clock-pcie1-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ reg_usdhc2_vmmc: regulator-v-3v3-sd {
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2>;
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <2>;
+ enable-active-high;
+ };
+
+ tpm_reset: tpm-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+ reset-post-delay-ms = <60>;
+ #reset-cells = <0>;
+ };
+
+ usb_hub_reset: usb-hub-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <3000>;
+ reset-post-delay-ms = <50>;
+ #reset-cells = <0>;
+ };
+};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_ecspi2 _ecspi2_cs>;
+ cs-gpios = < 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670";
+ reg = <0>;
+ resets = <_reset>;
+ spi-max-frequency = <4300>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ phy-reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethe
[PATCH v2 0/2] add Kontron pITX-imx8m board
This patch series adds support for the Kontron pITX-imx8m board: https://www.kontron.com/products/boards-and-standard-form-factors/single-board-computer/pitx-imx8m.html Heiko Thiery (2): dt-bindings: arm: fsl: add Kontron pITX-imx8m board arm64: dts: fsl: add support for Kontron pitx-imx8m board .../devicetree/bindings/arm/fsl.yaml | 1 + arch/arm64/boot/dts/freescale/Makefile| 1 + .../freescale/imx8mq-kontron-pitx-imx8m.dts | 641 ++ 3 files changed, 643 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts -- 2.30.0
[PATCH v2 1/2] dt-bindings: arm: fsl: add Kontron pITX-imx8m board
Add the Kontron pITX-imx8m board. Signed-off-by: Heiko Thiery --- v2: - bring in correct alphabetical order Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..6d121bc9af8d 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -733,6 +733,7 @@ properties: - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board - fsl,imx8mq-evk# i.MX8MQ EVK Board - google,imx8mq-phanbell# Google Coral Edge TPU + - kontron,pitx-imx8m# Kontron pITX-imx8m Board - purism,librem5-devkit # Purism Librem5 devkit - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk -- 2.30.0
Re: [PATCH 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Krzysztof,
Am Mo., 22. Feb. 2021 um 09:40 Uhr schrieb Krzysztof Kozlowski
:
>
> On Mon, Feb 22, 2021 at 08:46:52AM +0100, Heiko Thiery wrote:
> > Hi Krysztof,
> >
> > Am So., 21. Feb. 2021 um 13:11 Uhr schrieb Krzysztof Kozlowski
> > :
> > >
> > > On Thu, Feb 18, 2021 at 01:33:29PM +0100, Heiko Thiery wrote:
> > > > The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
> > > >
> > > > Signed-off-by: Heiko Thiery
> > > > ---
> > > > arch/arm64/boot/dts/freescale/Makefile| 1 +
> > > > .../freescale/imx8mq-kontron-pitx-imx8m.dts | 675 ++
> > > > 2 files changed, 676 insertions(+)
> > > > create mode 100644
> > > > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > > > b/arch/arm64/boot/dts/freescale/Makefile
> > > > index 6438db3822f8..9fc2c6f64407 100644
> > > > --- a/arch/arm64/boot/dts/freescale/Makefile
> > > > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > > > @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
> > > > +dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
> > > > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
> > > > diff --git
> > > > a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > > > new file mode 100644
> > > > index ..79805928204e
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > > > @@ -0,0 +1,675 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + * Device Tree File for the Kontron pitx-imx8m board.
> > > > + *
> > > > + * Copyright (C) 2021 Heiko Thiery
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include "imx8mq.dtsi"
> > > > +#include
> > > > +
> > > > +/ {
> > > > + model = "Kontron pITX-imx8m";
> > > > + compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
> > > > +
> > > > + aliases {
> > > > + i2c0 =
> > > > + i2c1 =
> > > > + i2c2 =
> > > > + mmc0 =
> > > > + mmc1 =
> > > > + serial0 =
> > > > + serial1 =
> > > > + serial2 =
> > > > + spi0 =
> > > > + spi1 =
> > > > + };
> > > > +
> > > > + chosen {
> > > > + stdout-path = "serial2:115200n8";
> > > > + };
> > > > +
> > > > + regulators {
> > > > + compatible = "simple-bus";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + reg_usdhc2_vmmc: regulator-v-3v3-sd {
> > >
> > > That's a messed unit addressing. You have here simple-bus but no unit
> > > addresses. Move it out of regulators node and run make dtc W=1 (it would
> > > point you this issue).
> >
> > Ok, I will change that.
> >
> > But I'm not able to run dtc on my dts. dtc throws an error.
> >
> > # dtc -I dts -O dtb imx8mq-kontron-pitx-imx8m.dts
> > Error: imx8mq-kontron-pitx-imx8m.dts:10.1-9 syntax error
> > FATAL ERROR: Unable to parse input tree
> >
> > It is about the includes. How can I run dtc for a intree dts to add
> > the -W option?
>
> make dtbs W=1
Ah ok. I was not aware of that.
>
> >
> > > > + compatible = "regulator-fixed";
> > > > + regulator-name = "V_3V3_SD";
> > > > + regulator-min-microvolt = <330>;
> > > > + regulator-max-microvolt = <330>;
> > >
Re: [PATCH 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Krysztof,
Am So., 21. Feb. 2021 um 13:11 Uhr schrieb Krzysztof Kozlowski
:
>
> On Thu, Feb 18, 2021 at 01:33:29PM +0100, Heiko Thiery wrote:
> > The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
> >
> > Signed-off-by: Heiko Thiery
> > ---
> > arch/arm64/boot/dts/freescale/Makefile| 1 +
> > .../freescale/imx8mq-kontron-pitx-imx8m.dts | 675 ++
> > 2 files changed, 676 insertions(+)
> > create mode 100644
> > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 6438db3822f8..9fc2c6f64407 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > new file mode 100644
> > index ..79805928204e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > @@ -0,0 +1,675 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree File for the Kontron pitx-imx8m board.
> > + *
> > + * Copyright (C) 2021 Heiko Thiery
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mq.dtsi"
> > +#include
> > +
> > +/ {
> > + model = "Kontron pITX-imx8m";
> > + compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
> > +
> > + aliases {
> > + i2c0 =
> > + i2c1 =
> > + i2c2 =
> > + mmc0 =
> > + mmc1 =
> > + serial0 =
> > + serial1 =
> > + serial2 =
> > + spi0 =
> > + spi1 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial2:115200n8";
> > + };
> > +
> > + regulators {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg_usdhc2_vmmc: regulator-v-3v3-sd {
>
> That's a messed unit addressing. You have here simple-bus but no unit
> addresses. Move it out of regulators node and run make dtc W=1 (it would
> point you this issue).
Ok, I will change that.
But I'm not able to run dtc on my dts. dtc throws an error.
# dtc -I dts -O dtb imx8mq-kontron-pitx-imx8m.dts
Error: imx8mq-kontron-pitx-imx8m.dts:10.1-9 syntax error
FATAL ERROR: Unable to parse input tree
It is about the includes. How can I run dtc for a intree dts to add
the -W option?
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_3V3_SD";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + gpio = < 19 GPIO_ACTIVE_HIGH>;
> > + off-on-delay-us = <2>;
> > + enable-active-high;
> > + };
> > + };
> > +
> > + usb_hub_reset: usb-hub-reset {
> > + compatible = "gpio-reset";
> > + reset-gpios = < 4 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <3000>;
> > + reset-post-delay-ms = <50>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + tpm_reset: tpm-reset {
> > + compatible = "gpio-reset";
> > + reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <2>;
> > + reset-post-delay-ms = <60>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + pcie0_refclk: pcie0-refclk {
>
> Generic node names (from the dt spec candidate is "clock").
Should I simply set the node name to pcie0-clock? And pcie1-clock for
the next one?
> > +
[PATCH 1/1] net: fec: ptp: avoid register access when ipg clock is disabled
When accessing the timecounter register on an i.MX8MQ the kernel hangs. This is only the case when the interface is down. This can be reproduced by reading with 'phc_ctrl eth0 get'. Like described in the change in 91c0d987a9788dcc5fe26baafd73bf9242b68900 the igp clock is disabled when the interface is down and leads to a system hang. So we check if the ptp clock status before reading the timecounter register. Signed-off-by: Heiko Thiery --- drivers/net/ethernet/freescale/fec_ptp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/ethernet/freescale/fec_ptp.c index 2e344aada4c6..c9882083da02 100644 --- a/drivers/net/ethernet/freescale/fec_ptp.c +++ b/drivers/net/ethernet/freescale/fec_ptp.c @@ -377,6 +377,9 @@ static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) u64 ns; unsigned long flags; + /* Check the ptp clock */ + if (!adapter->ptp_clk_on) + return -EINVAL; spin_lock_irqsave(>tmreg_lock, flags); ns = timecounter_read(>tc); spin_unlock_irqrestore(>tmreg_lock, flags); -- 2.30.0
Re: [PATCH 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
Hi Michael et all,
Am Do., 18. Feb. 2021 um 13:50 Uhr schrieb Michael Walle :
>
> Am 2021-02-18 13:33, schrieb Heiko Thiery:
> > The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
> >
> > Signed-off-by: Heiko Thiery
> > ---
> > arch/arm64/boot/dts/freescale/Makefile| 1 +
> > .../freescale/imx8mq-kontron-pitx-imx8m.dts | 675 ++
> > 2 files changed, 676 insertions(+)
> > create mode 100644
> > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 6438db3822f8..9fc2c6f64407 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
> > diff --git
> > a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > new file mode 100644
> > index ..79805928204e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> > @@ -0,0 +1,675 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree File for the Kontron pitx-imx8m board.
> > + *
> > + * Copyright (C) 2021 Heiko Thiery
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx8mq.dtsi"
> > +#include
> > +
> > +/ {
> > + model = "Kontron pITX-imx8m";
> > + compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
> > +
> > + aliases {
> > + i2c0 =
> > + i2c1 =
> > + i2c2 =
> > + mmc0 =
> > + mmc1 =
> > + serial0 =
> > + serial1 =
> > + serial2 =
> > + spi0 =
> > + spi1 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial2:115200n8";
> > + };
> > +
> > + regulators {
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg_usdhc2_vmmc: regulator-v-3v3-sd {
> > + compatible = "regulator-fixed";
> > + regulator-name = "V_3V3_SD";
> > + regulator-min-microvolt = <330>;
> > + regulator-max-microvolt = <330>;
> > + gpio = < 19 GPIO_ACTIVE_HIGH>;
> > + off-on-delay-us = <2>;
> > + enable-active-high;
> > + };
> > + };
> > +
> > + usb_hub_reset: usb-hub-reset {
> > + compatible = "gpio-reset";
> > + reset-gpios = < 4 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <3000>;
> > + reset-post-delay-ms = <50>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + tpm_reset: tpm-reset {
> > + compatible = "gpio-reset";
> > + reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> > + reset-delay-us = <2>;
> > + reset-post-delay-ms = <60>;
> > + #reset-cells = <0>;
> > + };
> > +
> > + pcie0_refclk: pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <1>;
> > + };
> > +
> > + pcie1_refclk: pcie1-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <1>;
> > + };
> > +
> > + gpio-keys {
> > + compatible = "gpio-keys";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_gpio_keys>;
> > +
> > + p
[PATCH 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board
The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
Signed-off-by: Heiko Thiery
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../freescale/imx8mq-kontron-pitx-imx8m.dts | 675 ++
2 files changed, 676 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..9fc2c6f64407 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
new file mode 100644
index ..79805928204e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include
+
+/ {
+ model = "Kontron pITX-imx8m";
+ compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+ aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ mmc0 =
+ mmc1 =
+ serial0 =
+ serial1 =
+ serial2 =
+ spi0 =
+ spi1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: regulator-v-3v3-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_SD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <2>;
+ enable-active-high;
+ };
+ };
+
+ usb_hub_reset: usb-hub-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <3000>;
+ reset-post-delay-ms = <50>;
+ #reset-cells = <0>;
+ };
+
+ tpm_reset: tpm-reset {
+ compatible = "gpio-reset";
+ reset-gpios = < 2 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+ reset-post-delay-ms = <60>;
+ #reset-cells = <0>;
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ pcie1_refclk: pcie1-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <_gpio_keys>;
+
+ pciewake {
+ label = "PCIE_Wake";
+ gpios = < 8 GPIO_ACTIVE_LOW>;
+ linux,input-type = <4>; /* EV_MSC */
+ linux,code = <3>; /* MSC_RAW */
+ gpio-key,wakeup;
+ };
+ };
+};
+
+ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_ecspi2 _ecspi2_cs>;
+ cs-gpios = < 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ slb9670@0 {
+ compatible = "infineon,slb9670";
+ reg = <0>;
+ resets = <_reset>;
+ spi-max-frequency = <4300>;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ phy-reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+
[PATCH 0/2] add Kontron pITX-imx8m board
This patch series adds support for the Kontron pITX-imx8m board: https://www.kontron.com/products/boards-and-standard-form-factors/single-board-computer/pitx-imx8m.html Heiko Thiery (2): dt-bindings: arm: fsl: add Kontron pITX-imx8m board arm64: dts: fsl: add support for Kontron pitx-imx8m board .../devicetree/bindings/arm/fsl.yaml | 1 + arch/arm64/boot/dts/freescale/Makefile| 1 + .../freescale/imx8mq-kontron-pitx-imx8m.dts | 675 ++ 3 files changed, 677 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts -- 2.30.0
[PATCH 1/2] dt-bindings: arm: fsl: add Kontron pITX-imx8m board
Add the Kontron pITX-imx8m board compatibles binding. Signed-off-by: Heiko Thiery --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..0a0d03dd5e31 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -734,6 +734,7 @@ properties: - fsl,imx8mq-evk# i.MX8MQ EVK Board - google,imx8mq-phanbell# Google Coral Edge TPU - purism,librem5-devkit # Purism Librem5 devkit + - kontron,pitx-imx8m# Kontron pITX-imx8m Board - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq -- 2.30.0
Re: [PATCH v2 4/4] mtd: spi-nor: implement OTP support for Winbond and similar flashes
HI Michael,
Am Sa., 12. Sept. 2020 um 00:26 Uhr schrieb Michael Walle :
>
> Use the new OTP ops to implement OTP access on Winbond flashes. Most
> Winbond flashes provides up to four different OTP areas ("Security
> Registers"). Newer flashes uses the first OTP area for SFDP data. Thus,
> for these flashes only the last three areas are handled and the first
> one is left untouched.
>
> This was tested on a Winbond W25Q32JW as well as on a W25Q32FW.
>
> Signed-off-by: Michael Walle
Reviewed-by: Heiko Thiery
> ---
> drivers/mtd/spi-nor/core.c| 161 ++
> drivers/mtd/spi-nor/core.h| 4 +
> drivers/mtd/spi-nor/winbond.c | 18 +++-
> include/linux/mtd/spi-nor.h | 10 +++
> 4 files changed, 191 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 348db19958e9..c150e3b6ee44 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2997,6 +2997,167 @@ int spi_nor_otp_is_locked_scur(struct spi_nor *nor,
> unsigned int region)
> return *scur & SCUR_LDSO;
> }
>
> +/**
> + * spi_nor_otp_read_secr() - read OTP data
> + * @nor: pointer to 'struct spi_nor'
> + * @from: offset to read from
> + * @len:number of bytes to read
> + * @buf:pointer to dst buffer
> + *
> + * Read OTP data by using the SPINOR_OP_RSECR commands. This method is used
> on
> + * GigaDevice and Winbond flashes.
> + *
> + * Return: number of bytes read successfully, -errno otherwise
> + */
> +int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, uint64_t len, u8
> *buf)
> +{
> + u8 addr_width, read_opcode, read_dummy;
> + struct spi_mem_dirmap_desc *rdesc;
> + enum spi_nor_protocol read_proto;
> + int ret;
> +
> + read_opcode = nor->read_opcode;
> + addr_width = nor->addr_width;
> + read_dummy = nor->read_dummy;
> + read_proto = nor->read_proto;
> + rdesc = nor->dirmap.rdesc;
> +
> + nor->read_opcode = SPINOR_OP_RSECR;
> + nor->addr_width = 3;
> + nor->read_dummy = 8;
> + nor->read_proto = SNOR_PROTO_1_1_1;
> + nor->dirmap.rdesc = NULL;
> +
> + ret = spi_nor_read_data(nor, addr, len, buf);
> +
> + nor->read_opcode = read_opcode;
> + nor->addr_width = addr_width;
> + nor->read_dummy = read_dummy;
> + nor->read_proto = read_proto;
> + nor->dirmap.rdesc = rdesc;
> +
> + return ret;
> +}
> +
> +/**
> + * spi_nor_otp_write_secr() - write OTP data
> + * @nor:pointer to 'struct spi_nor'
> + * @to: offset to write to
> + * @len:number of bytes to write
> + * @buf:pointer to src buffer
> + *
> + * Write OTP data by using the SPINOR_OP_PSECR commands. This method is used
> on
> + * GigaDevice and Winbond flashes.
> + *
> + * Return: number of bytes written successfully, -errno otherwise
> + */
> +int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, uint64_t len,
> u8 *buf)
> +{
> + enum spi_nor_protocol write_proto;
> + struct spi_mem_dirmap_desc *wdesc;
> + u8 addr_width, program_opcode;
> + int ret;
> +
> + program_opcode = nor->program_opcode;
> + addr_width = nor->addr_width;
> + write_proto = nor->write_proto;
> + wdesc = nor->dirmap.wdesc;
> +
> + nor->program_opcode = SPINOR_OP_PSECR;
> + nor->addr_width = 3;
> + nor->write_proto = SNOR_PROTO_1_1_1;
> + nor->dirmap.wdesc = NULL;
> +
> + /*
> +* We only support a write to one single page. For now all winbond
> +* flashes only have one page per OTP region.
> +*/
> + ret = spi_nor_write_enable(nor);
> + if (ret)
> + goto out;
> +
> + ret = spi_nor_write_data(nor, addr, len, buf);
> + if (ret < 0)
> + goto out;
> +
> + ret = spi_nor_wait_till_ready(nor);
> +
> +out:
> + nor->program_opcode = program_opcode;
> + nor->addr_width = addr_width;
> + nor->write_proto = write_proto;
> + nor->dirmap.wdesc = wdesc;
> +
> + return ret;
> +}
> +
> +static int spi_nor_otp_lock_bit_cr(unsigned int region)
> +{
> + static const int lock_bits[] = { SR2_LB1, SR2_LB2, SR2_LB3 };
> +
> + if (region >= ARRAY_SIZE(lock_bits))
> + return -EINVAL;
> +
> + return lock_bits[region];
> +}
> +
> +/**
> + * spi_nor_otp_lock_sr2() - lock the OTP region
> + * @nor:
Re: [PATCH v2 3/4] mtd: spi-nor: implement OTP support for Macronix and similar flashes
Hi Michael,
Am Sa., 12. Sept. 2020 um 00:26 Uhr schrieb Michael Walle :
>
> Use the new OTP ops to implement OTP access on Macronix flashes. The
> Macronix flashes provides one OTP area which is either programmed with
> an electrical serial number and locked by the factory or is empty and can
> be locked by the user. To keep things simple and because most devices
> will have unprogrammed OTP areas, we treat both options as user regions.
> If there will actually be an ESN preprogrammed, it will appear as a
> locked user region.
>
> This was tested on a Macronix MX25L6405D as well as on a Adesto
> AT25SL321.
>
> Signed-off-by: Michael Walle
Reviewed-by: Heiko Thiery
> ---
> drivers/mtd/spi-nor/atmel.c| 13 ++-
> drivers/mtd/spi-nor/core.c | 170 +
> drivers/mtd/spi-nor/core.h | 9 ++
> drivers/mtd/spi-nor/macronix.c | 13 ++-
> include/linux/mtd/spi-nor.h| 6 ++
> 5 files changed, 209 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 3f5f21a473a6..1688c9989c6b 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -19,7 +19,8 @@ static const struct flash_info atmel_parts[] = {
> { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
>
> { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64,
> -SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> },
> +SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> +OTP_INFO1(512, 0) },
>
> { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
> { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
> @@ -29,9 +30,19 @@ static const struct flash_info atmel_parts[] = {
> { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
> };
>
> +static const struct spi_nor_otp_ops atmel_otp_ops = {
> + .read = spi_nor_otp_read_otp_mode,
> + .write = spi_nor_otp_write_otp_mode,
> + .lock = spi_nor_otp_lock_scur,
> + .is_locked = spi_nor_otp_is_locked_scur,
> +};
> +
> static void atmel_default_init(struct spi_nor *nor)
> {
> nor->flags |= SNOR_F_HAS_LOCK;
> +
> + if (nor->params->otp_info.n_otps)
> + nor->params->otp_ops = _otp_ops;
> }
>
> static const struct spi_nor_fixups atmel_fixups = {
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 4244f98e4948..348db19958e9 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2828,6 +2828,176 @@ static int spi_nor_unlock_all(struct spi_nor *nor)
> return 0;
> }
>
> +/**
> + * spi_nor_set_secured_otp_mode() - Set secured OTP mode
> + * @nor: pointer to 'struct spi_nor'.
> + * @enable:true to enter the secured OTP mode, false to exit the secured
> + * OTP mode.
> + *
> + * Enter and exit OTP mode by using the command SPINOR_OP_ENSO (B1h) and
> + * SPINOR_EP_EXSO (C1h) command.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_set_secured_otp_mode(struct spi_nor *nor, bool enable)
> +{
> + u8 cmd = enable ? SPINOR_OP_ENSO : SPINOR_OP_EXSO;
> + int ret;
> +
> + ret = spi_nor_simple_cmd(nor, cmd);
> + if (ret)
> + dev_dbg(nor->dev, "error %d setting secured OTP mode\n", ret);
> +
> + return ret;
> +}
> +
> +/**
> + * spi_nor_read_scur() - Read the Security Register using the
> SPINOR_OP_RDSCUR (2Bh) command.
> + * @nor: pointer to 'struct spi_nor'
> + * @scur: pointer to a DMA-able buffer where the value of the
> + * Security Register will be written.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_read_scur(struct spi_nor *nor, u8 *scur)
> +{
> + int ret;
> +
> + ret = spi_nor_simple_cmd_din(nor, SPINOR_OP_RDSCUR, scur, 1);
> + if (ret)
> + dev_dbg(nor->dev, "error %d reading SCUR\n", ret);
> +
> + return ret;
> +}
> +
> +/**
> + * spi_nor_write_scur() - Write the Security Register using the
> SPINOR_OP_WRSCUR (2Fh) command.
> + * @nor: pointer to 'struct spi_nor'
> + *
> + * This register contains only one OTP bit. The command doesn't take any
> + * arguments. In fact it _must not_ take any arugments. Otherwise the command
> + * is ignored.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_write_scur(struct spi_nor *nor)
> +{
> + int ret;
> +
>
Re: [PATCH v2 2/4] mtd: spi-nor: add OTP support
Hi Michael,
Am Sa., 12. Sept. 2020 um 00:26 Uhr schrieb Michael Walle :
>
> Implement the MTD callbacks for the OTP methods for the SPI NOR
> subsystem.
>
> Usually, the OTP area of a SPI flash can be accessed like the normal
> memory, eg by offset addressing; except that you either have to use
> special read/write commands (Winbond) or you have to enter (and exit) a
> specific OTP mode (Macronix, Micron). Sometimes there are individual
> regions, which might have individual offsets. Therefore, it is possible
> to specify the starting address of the first regions as well as the
> distance between two regions (Winbond).
>
> Additionally, the regions might be locked down. Once locked, no further
> write access is possible.
>
> Cc: Rahul Bedarkar
> Signed-off-by: Michael Walle
Reviewed-by: Heiko Thiery
> ---
> drivers/mtd/chips/Kconfig | 2 +-
> drivers/mtd/spi-nor/core.c | 143 +
> drivers/mtd/spi-nor/core.h | 48 +
> 3 files changed, 192 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/chips/Kconfig b/drivers/mtd/chips/Kconfig
> index aef14990e5f7..3b7ba9448118 100644
> --- a/drivers/mtd/chips/Kconfig
> +++ b/drivers/mtd/chips/Kconfig
> @@ -152,7 +152,7 @@ config MTD_CFI_I8
>
> config MTD_OTP
> bool "Protection Registers aka one-time programmable (OTP) bits"
> - depends on MTD_CFI_ADV_OPTIONS
> + depends on MTD_CFI_ADV_OPTIONS || MTD_SPI_NOR
> default n
> help
> This enables support for reading, writing and locking so called
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index b06b160a5c9c..4244f98e4948 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2689,6 +2689,12 @@ static void spi_nor_info_init_params(struct spi_nor
> *nor)
> spi_nor_set_erase_type(>erase_type[i], info->sector_size,
>SPINOR_OP_SE);
> spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
> +
> + /* OTP parameters */
> + nor->params->otp_info.otp_size = info->otp_size;
> + nor->params->otp_info.n_otps = info->n_otps;
> + nor->params->otp_info.otp_start_addr = info->otp_start_addr;
> + nor->params->otp_info.otp_addr_offset = info->otp_addr_offset;
> }
>
> /**
> @@ -2972,6 +2978,127 @@ static const struct flash_info
> *spi_nor_get_flash_info(struct spi_nor *nor,
> return info;
> }
>
> +static loff_t spi_nor_otp_region_start(struct spi_nor *nor, int region)
> +{
> + struct spi_nor_otp_info *info = >params->otp_info;
> +
> + return info->otp_start_addr + region * info->otp_addr_offset;
> +}
> +
> +static loff_t spi_nor_otp_region_end(struct spi_nor *nor, int region)
> +{
> + struct spi_nor_otp_info *info = >params->otp_info;
> +
> + return spi_nor_otp_region_start(nor, region) + info->otp_size - 1;
> +}
> +
> +static int spi_nor_mtd_otp_info(struct mtd_info *mtd, size_t len,
> + size_t *retlen, struct otp_info *buf)
> +{
> + struct spi_nor *nor = mtd_to_spi_nor(mtd);
> + int locked;
> + int i;
> +
> + for (i = 0; i < nor->params->otp_info.n_otps; i++) {
> + buf[i].start = spi_nor_otp_region_start(nor, i);
> + buf[i].length = nor->params->otp_info.otp_size;
> +
> + locked = nor->params->otp_ops->is_locked(nor, i);
> + if (locked < 0)
> + return locked;
> +
> + buf[i].locked = !!locked;
> + }
> +
> + *retlen = nor->params->otp_info.n_otps * sizeof(*buf);
> +
> + return 0;
> +}
> +
> +static int spi_nor_otp_addr_to_region(struct spi_nor *nor, loff_t addr)
> +{
> + int i;
> +
> + for (i = 0; i < nor->params->otp_info.n_otps; i++)
> + if (addr >= spi_nor_otp_region_start(nor, i) &&
> + addr <= spi_nor_otp_region_end(nor, i))
> + return i;
> +
> + return -EINVAL;
> +}
> +
> +static int spi_nor_mtd_otp_read_write(struct mtd_info *mtd, loff_t ofs,
> + size_t len, size_t *retlen, u_char *buf,
> + bool is_write)
> +{
> + struct spi_nor *nor = mtd_to_spi_nor(mtd);
> + int region;
> + int ret;
> +
> + *retlen = 0;
> +
> + region = spi_nor_otp_addr_to_region(nor, ofs);
> + if (region < 0)
> + return 0;
&
