Re: [PATCH v2 18/25] drm/mediatek: add RDMA fifo size error handle

[YT Shen]

On Tue, 2019-04-16 at 16:37 +0800, Yongqiang Niu wrote:
> On Tue, 2019-04-16 at 16:00 +0800, CK Hu wrote:
> > Hi, Yongqiang:
> > 
> > On Wed, 2019-03-27 at 14:19 +0800, yongqiang@mediatek.com wrote:
> > > From: Yongqiang Niu 
> > > 
> > > This patch add RDMA fifo size error handle
> > > rdma fifo size will not always bigger than the calculated threshold
> > > if that case happened, we need set fifo size as the threshold
> > > 
> > > Signed-off-by: Yongqiang Niu 
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 -
> > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
> > > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > index b0a5cff..ead38ba 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > @@ -137,11 +137,14 @@ static void mtk_rdma_config(struct mtk_ddp_comp 
> > > *comp, unsigned int width,
> > >  {
> > >   unsigned int threshold;
> > >   unsigned int reg;
> > > + unsigned int rdma_fifo_size;
> > >   struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > >  
> > >   rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > >   rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xf, height);
> > >  
> > > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
> > > +
> > >   /*
> > >* Enable FIFO underflow since DSI and DPI can't be blocked.
> > >* Keep the FIFO pseudo size reset default of 8 KiB. Set the
> > > @@ -149,8 +152,12 @@ static void mtk_rdma_config(struct mtk_ddp_comp 
> > > *comp, unsigned int width,
> > >* account for blanking, and with a pixel depth of 4 bytes:
> > >*/
> > >   threshold = width * height * vrefresh * 4 * 7 / 100;
> > > +
> > > + if (threshold > rdma_fifo_size)
> > > + threshold = rdma_fifo_size;
> > 
> > I think this is a work around not a correct solution. Why MT8173 has no
> > this problem but MT8183 has? Is the formula of threshold different in
> > MT8173 and MT8183?
> > 
> > Regards,
> > CK
> > 
> 
> fifo size of RDMA0 and RDMA1 in MT8173 are same, which is SZ_8K.
> this formula calculate result will not overflow if the screen size is
> not big enough. 
> 
> but fifo size of RDMA1 in MT8183 only SZ_2K, if RDMA1 display with
> solution 1080p60hz, this formula calculate result 3483 will overflow
> SZ_2K. 
RDMA1 with SZ_2K can support up to 1080p60hz, even the formula shows
overflow, is it correct?

The formula shows all resolution something more than 1280x1080@60hz will
overflow SZ_2K, and in this patch all set to maximum value.

The patch should implement different FIFO size depends on RDMA0
(SZ_5K)and RDMA1 (SZ_2K), and use the value from the formula.

Regards,
yt.shen

> 
> > > +
> > >   reg = RDMA_FIFO_UNDERFLOW_EN |
> > > -   RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
> > > +   RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> > > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> > >   writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> > >  }
> > 
> > 
> 
> 

[PATCH 6/8] arm64: dts: add mmc nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 34 +++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e9856fe..4f0aa65 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -611,6 +611,40 @@
status = "disabled";
};
 
+   mmc0: mmc@1123 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1123 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_0>,
+< CLK_PERI_MSDC50_0_HCLK_EN>,
+< CLK_PERI_MSDC30_0_QTR_EN>,
+< CLK_PERI_MSDC50_0_EN>;
+   clock-names = "source", "hclk", "bus_clk", "source_cg";
+   status = "disabled";
+   };
+
+   mmc1: mmc@1124 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1124 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_1>,
+< CLK_TOP_AXI_SEL>,
+< CLK_PERI_MSDC30_1_EN>;
+   clock-names = "source", "hclk", "source_cg";
+   status = "disabled";
+   };
+
+   mmc2: mmc@1125 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1125 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_2>,
+< CLK_TOP_AXI_SEL>,
+< CLK_PERI_MSDC30_2_EN>;
+   clock-names = "source", "hclk", "source_cg";
+   status = "disabled";
+   };
+
ssusb: usb@11271000 {
compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
reg = <0 0x11271000 0 0x3000>,
-- 
1.9.1

[PATCH 2/8] arm64: dts: add iommu/smi nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 128 ++
 1 file changed, 128 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 6c228a2..d429770 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "mt2712-pinfunc.h"
@@ -313,12 +314,33 @@
status = "disabled";
};
 
+   iommu0: iommu@10205000 {
+   compatible = "mediatek,mt2712-m4u";
+   reg = <0 0x10205000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = <  
+  >;
+   #iommu-cells = <1>;
+   };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2712-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
 
+   iommu1: iommu@1020a000 {
+   compatible = "mediatek,mt2712-m4u";
+   reg = <0 0x1020a000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = <  >;
+   #iommu-cells = <1>;
+   };
+
mcucfg: syscon@1022 {
compatible = "mediatek,mt2712-mcucfg", "syscon";
reg = <0 0x1022 0 0x1000>;
@@ -543,12 +565,85 @@
#clock-cells = <1>;
};
 
+   larb0: larb@14021000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14021000 0 0x1000>;
+   mediatek,smi = <_common0>;
+   mediatek,larb-id = <0>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB0>,
+< CLK_MM_SMI_LARB0>;
+   clock-names = "apb", "smi";
+   };
+
+   smi_common0: smi@14022000 {
+   compatible = "mediatek,mt2712-smi-common";
+   reg = <0 0x14022000 0 0x1000>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON>,
+< CLK_MM_SMI_COMMON>;
+   clock-names = "apb", "smi";
+   };
+
+   larb4: larb@14027000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14027000 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <4>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB4>,
+< CLK_MM_SMI_LARB4>;
+   clock-names = "apb", "smi";
+   };
+
+   larb5: larb@1403 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x1403 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <5>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB5>,
+< CLK_MM_SMI_LARB5>;
+   clock-names = "apb", "smi";
+   };
+
+   smi_common1: smi@14031000 {
+   compatible = "mediatek,mt2712-smi-common";
+   reg = <0 0x14031000 0 0x1000>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON1>,
+< CLK_MM_SMI_COMMON1>;
+   clock-names = "apb", "smi";
+   };
+
+   larb7: larb@14032000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14032000 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <7>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB7>,
+< CLK_MM_SMI_LARB7>;
+   clock-names = "apb", "smi";
+   };
+
imgsys: syscon@1500 {
compatible = "mediatek,mt2712-imgsys", "syscon";
reg = <0 0x1500 0 0x1000>;
#clock-cells = <1>;
};
 
+   larb2: larb@15001000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x15001000 0 

[PATCH 0/8] add dts nodes to MT2712 SoC

[YT Shen]

This patch series based on v4.20-rc1, include MT2712 
usb/iommu/smi/i2c/spi/pwm/mmc/nand/pcie device nodes

Chunfeng Yun (1):
  arm64: dts: Add USB3 related nodes for MT2712

Honghui Zhang (1):
  arm64: dts: add pcie nodes for MT2712

YT Shen (6):
  arm64: dts: add iommu/smi nodes for MT2712
  arm64: dts: add i2c nodes for MT2712
  arm64: dts: add spi nodes for MT2712
  arm64: dts: add pwm nodes for MT2712
  arm64: dts: add mmc nodes for MT2712
  arm64: dts: add nand nodes for MT2712

 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  98 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 555 
 2 files changed, 653 insertions(+)

-- 
1.9.1

[PATCH 6/8] arm64: dts: add mmc nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 34 +++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e9856fe..4f0aa65 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -611,6 +611,40 @@
status = "disabled";
};
 
+   mmc0: mmc@1123 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1123 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_0>,
+< CLK_PERI_MSDC50_0_HCLK_EN>,
+< CLK_PERI_MSDC30_0_QTR_EN>,
+< CLK_PERI_MSDC50_0_EN>;
+   clock-names = "source", "hclk", "bus_clk", "source_cg";
+   status = "disabled";
+   };
+
+   mmc1: mmc@1124 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1124 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_1>,
+< CLK_TOP_AXI_SEL>,
+< CLK_PERI_MSDC30_1_EN>;
+   clock-names = "source", "hclk", "source_cg";
+   status = "disabled";
+   };
+
+   mmc2: mmc@1125 {
+   compatible = "mediatek,mt2712-mmc";
+   reg = <0 0x1125 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_PERI_MSDC30_2>,
+< CLK_TOP_AXI_SEL>,
+< CLK_PERI_MSDC30_2_EN>;
+   clock-names = "source", "hclk", "source_cg";
+   status = "disabled";
+   };
+
ssusb: usb@11271000 {
compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
reg = <0 0x11271000 0 0x3000>,
-- 
1.9.1

[PATCH 2/8] arm64: dts: add iommu/smi nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 128 ++
 1 file changed, 128 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 6c228a2..d429770 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "mt2712-pinfunc.h"
@@ -313,12 +314,33 @@
status = "disabled";
};
 
+   iommu0: iommu@10205000 {
+   compatible = "mediatek,mt2712-m4u";
+   reg = <0 0x10205000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = <  
+  >;
+   #iommu-cells = <1>;
+   };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2712-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
 
+   iommu1: iommu@1020a000 {
+   compatible = "mediatek,mt2712-m4u";
+   reg = <0 0x1020a000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_INFRA_M4U>;
+   clock-names = "bclk";
+   mediatek,larbs = <  >;
+   #iommu-cells = <1>;
+   };
+
mcucfg: syscon@1022 {
compatible = "mediatek,mt2712-mcucfg", "syscon";
reg = <0 0x1022 0 0x1000>;
@@ -543,12 +565,85 @@
#clock-cells = <1>;
};
 
+   larb0: larb@14021000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14021000 0 0x1000>;
+   mediatek,smi = <_common0>;
+   mediatek,larb-id = <0>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB0>,
+< CLK_MM_SMI_LARB0>;
+   clock-names = "apb", "smi";
+   };
+
+   smi_common0: smi@14022000 {
+   compatible = "mediatek,mt2712-smi-common";
+   reg = <0 0x14022000 0 0x1000>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON>,
+< CLK_MM_SMI_COMMON>;
+   clock-names = "apb", "smi";
+   };
+
+   larb4: larb@14027000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14027000 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <4>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB4>,
+< CLK_MM_SMI_LARB4>;
+   clock-names = "apb", "smi";
+   };
+
+   larb5: larb@1403 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x1403 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <5>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB5>,
+< CLK_MM_SMI_LARB5>;
+   clock-names = "apb", "smi";
+   };
+
+   smi_common1: smi@14031000 {
+   compatible = "mediatek,mt2712-smi-common";
+   reg = <0 0x14031000 0 0x1000>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_COMMON1>,
+< CLK_MM_SMI_COMMON1>;
+   clock-names = "apb", "smi";
+   };
+
+   larb7: larb@14032000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x14032000 0 0x1000>;
+   mediatek,smi = <_common1>;
+   mediatek,larb-id = <7>;
+   power-domains = < MT2712_POWER_DOMAIN_MM>;
+   clocks = < CLK_MM_SMI_LARB7>,
+< CLK_MM_SMI_LARB7>;
+   clock-names = "apb", "smi";
+   };
+
imgsys: syscon@1500 {
compatible = "mediatek,mt2712-imgsys", "syscon";
reg = <0 0x1500 0 0x1000>;
#clock-cells = <1>;
};
 
+   larb2: larb@15001000 {
+   compatible = "mediatek,mt2712-smi-larb";
+   reg = <0 0x15001000 0 

[PATCH 0/8] add dts nodes to MT2712 SoC

[YT Shen]

This patch series based on v4.20-rc1, include MT2712 
usb/iommu/smi/i2c/spi/pwm/mmc/nand/pcie device nodes

Chunfeng Yun (1):
  arm64: dts: Add USB3 related nodes for MT2712

Honghui Zhang (1):
  arm64: dts: add pcie nodes for MT2712

YT Shen (6):
  arm64: dts: add iommu/smi nodes for MT2712
  arm64: dts: add i2c nodes for MT2712
  arm64: dts: add spi nodes for MT2712
  arm64: dts: add pwm nodes for MT2712
  arm64: dts: add mmc nodes for MT2712
  arm64: dts: add nand nodes for MT2712

 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  98 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 555 
 2 files changed, 653 insertions(+)

-- 
1.9.1

[PATCH 4/8] arm64: dts: add spi nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 65 +++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 7bac8b6..4843376 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -463,6 +463,19 @@
status = "disabled";
};
 
+   spi0: spi@1100a000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x1100a000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI0>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
i2c3: i2c@1101 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x1101 0 0x90>,
@@ -508,6 +521,58 @@
status = "disabled";
};
 
+   spi2: spi@11015000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11015000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI2>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi3: spi@11016000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11016000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI3>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi4: spi@10012000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x10012000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_INFRA_AO_SPI0>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi5: spi@11018000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11018000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI5>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
 "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH 1/8] arm64: dts: Add USB3 related nodes for MT2712

[YT Shen]

From: Chunfeng Yun 

This patch adds USB3 related nodes for mt2712m1 platform.

Signed-off-by: Chunfeng Yun 
---
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  98 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 126 
 2 files changed, 224 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 98d6275..1353dad 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -6,6 +6,7 @@
  */
 
 /dts-v1/;
+#include 
 #include "mt2712e.dtsi"
 
 / {
@@ -41,6 +42,53 @@
regulator-max-microvolt = <100>;
};
 
+   extcon_usb: extcon_iddig {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = < 12 GPIO_ACTIVE_HIGH>;
+   };
+
+   extcon_usb1: extcon_iddig1 {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = < 14 GPIO_ACTIVE_HIGH>;
+   };
+
+   usb_p0_vbus: regulator@2 {
+   compatible = "regulator-fixed";
+   regulator-name = "p0_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 13 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p1_vbus: regulator@3 {
+   compatible = "regulator-fixed";
+   regulator-name = "p1_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 15 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p2_vbus: regulator@4 {
+   compatible = "regulator-fixed";
+   regulator-name = "p2_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 16 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p3_vbus: regulator@5 {
+   compatible = "regulator-fixed";
+   regulator-name = "p3_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 17 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   };
+
 };
 
  {
@@ -59,7 +107,57 @@
proc-supply = <_fixed_vproc1>;
 };
 
+ {
+   usb0_id_pins_float: usb0_iddig {
+   pins_iddig {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+
+   usb1_id_pins_float: usb1_iddig {
+   pins_iddig {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+};
+
+ {
+   vbus-supply = <_p0_vbus>;
+   extcon = <_usb>;
+   dr_mode = "otg";
+   wakeup-source;
+   mediatek,u3p-dis-msk = <0x1>;
+   //enable-manual-drd;
+   //maximum-speed = "full-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_id_pins_float>;
+   status = "okay";
+};
+
+ {
+   vbus-supply = <_p1_vbus>;
+   extcon = <_usb1>;
+   dr_mode = "otg";
+   //mediatek,u3p-dis-msk = <0x1>;
+   enable-manual-drd;
+   wakeup-source;
+   //maximum-speed = "full-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_id_pins_float>;
+   status = "okay";
+};
+
  {
status = "okay";
 };
 
+_host0 {
+   vbus-supply = <_p2_vbus>;
+   status = "okay";
+};
+
+_host1 {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index ee627a7..6c228a2 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "mt2712-pinfunc.h"
 
@@ -405,6 +406,131 @@
status = "disabled";
};
 
+   ssusb: usb@11271000 {
+   compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
+   reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280700 0 0x0100>;
+   reg-names = "mac", "ippc";
+   interrupts = ;
+   phys = < PHY_TYPE_USB2>,
+  < PHY_TYPE_USB2>;
+   power-domains = < MT2712_POWER_DOMAIN_USB>;
+   clocks = < CLK_TOP_USB30_SEL>;
+   clock-names = "sys_ck";
+   mediatek,syscon-wakeup = < 0x510 2>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   usb_host0: xhci@1127 {
+   compatible = "mediatek,mt2712-xhci",
+"mediatek,mtk-xhci";
+   reg = <0 0x1127 0 0x1000>;
+   reg-names = "mac";
+   interrupts = ;
+   

[PATCH 7/8] arm64: dts: add nand nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4f0aa65..e8afb54 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -504,6 +504,27 @@
status = "disabled";
};
 
+   nandc: nfi@1100e000 {
+   compatible = "mediatek,mt2712-nfc";
+   reg = <0 0x1100e000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_TOP_NFI2X_EN>, < CLK_PERI_NFI>;
+   clock-names = "nfi_clk", "pad_clk";
+   ecc-engine = <>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   bch: ecc@1100f000 {
+   compatible = "mediatek,mt2712-ecc";
+   reg = <0 0x1100f000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_TOP_NFI1X_CK_EN>;
+   clock-names = "nfiecc_clk";
+   status = "disabled";
+   };
+
i2c3: i2c@1101 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x1101 0 0x90>,
-- 
1.9.1

[PATCH 5/8] arm64: dts: add pwm nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4843376..e9856fe 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,34 @@
status = "disabled";
};
 
+   pwm: pwm@11006000 {
+   compatible = "mediatek,mt2712-pwm";
+   reg = <0 0x11006000 0 0x1000>;
+   #pwm-cells = <2>;
+   interrupts = ;
+   clocks = < CLK_TOP_PWM_SEL>,
+< CLK_PERI_PWM>,
+< CLK_PERI_PWM0>,
+< CLK_PERI_PWM1>,
+< CLK_PERI_PWM2>,
+< CLK_PERI_PWM3>,
+< CLK_PERI_PWM4>,
+< CLK_PERI_PWM5>,
+< CLK_PERI_PWM6>,
+< CLK_PERI_PWM7>;
+   clock-names = "top",
+ "main",
+ "pwm1",
+ "pwm2",
+ "pwm3",
+ "pwm4",
+ "pwm5",
+ "pwm6",
+ "pwm7",
+ "pwm8";
+   status = "disabled";
+   };
+
i2c0: i2c@11007000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11007000 0 0x90>,
-- 
1.9.1

[PATCH 3/8] arm64: dts: add i2c nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 90 +++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d429770..7bac8b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,96 @@
status = "disabled";
};
 
+   i2c0: i2c@11007000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11007000 0 0x90>,
+ <0 0x11000180 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C0>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@11008000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11008000 0 0x90>,
+ <0 0x11000200 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C1>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c2: i2c@11009000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11009000 0 0x90>,
+ <0 0x11000280 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C2>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@1101 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x1101 0 0x90>,
+ <0 0x11000300 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C3>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c4: i2c@11011000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11011000 0 0x90>,
+ <0 0x11000380 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C4>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c5: i2c@11013000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11013000 0 0x90>,
+ <0 0x11000100 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C5>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
 "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH 8/8] arm64: dts: add pcie nodes for MT2712

[YT Shen]

From: Honghui Zhang 

This patch add device node for mt2712 pcie.

Signed-off-by: Honghui Zhang 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 63 +++
 1 file changed, 63 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e8afb54..976d92a 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -791,6 +791,69 @@
};
};
 
+   pcie: pcie@1170 {
+   compatible = "mediatek,mt2712-pcie";
+   device_type = "pci";
+   reg = <0 0x1170 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+   reg-names = "port0", "port1";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupts = ,
+;
+   clocks = < CLK_TOP_PE2_MAC_P0_SEL>,
+< CLK_TOP_PE2_MAC_P1_SEL>,
+< CLK_PERI_PCIE0>,
+< CLK_PERI_PCIE1>;
+   clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+   phys = < PHY_TYPE_PCIE>, < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1";
+   bus-range = <0x00 0xff>;
+   ranges = <0x8200 0 0x2000  0x0 0x2000  0 
0x1000>;
+
+   pcie0: pcie@0,0 {
+   device_type = "pci";
+   status = "disabled";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   num-lanes = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc0 0>,
+   <0 0 0 2 _intc0 1>,
+   <0 0 0 3 _intc0 2>,
+   <0 0 0 4 _intc0 3>;
+   pcie_intc0: interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   };
+   };
+
+   pcie1: pcie@1,0 {
+   device_type = "pci";
+   status = "disabled";
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   num-lanes = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc1 0>,
+   <0 0 0 2 _intc1 1>,
+   <0 0 0 3 _intc1 2>,
+   <0 0 0 4 _intc1 3>;
+   pcie_intc1: interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   };
+   };
+   };
+
mfgcfg: syscon@1300 {
compatible = "mediatek,mt2712-mfgcfg", "syscon";
reg = <0 0x1300 0 0x1000>;
-- 
1.9.1

[PATCH 3/8] arm64: dts: add i2c nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 90 +++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index d429770..7bac8b6 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,96 @@
status = "disabled";
};
 
+   i2c0: i2c@11007000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11007000 0 0x90>,
+ <0 0x11000180 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C0>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@11008000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11008000 0 0x90>,
+ <0 0x11000200 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C1>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c2: i2c@11009000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11009000 0 0x90>,
+ <0 0x11000280 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C2>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@1101 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x1101 0 0x90>,
+ <0 0x11000300 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C3>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c4: i2c@11011000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11011000 0 0x90>,
+ <0 0x11000380 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C4>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   i2c5: i2c@11013000 {
+   compatible = "mediatek,mt2712-i2c";
+   reg = <0 0x11013000 0 0x90>,
+ <0 0x11000100 0 0x80>;
+   interrupts = ;
+   clock-div = <4>;
+   clocks = < CLK_PERI_I2C5>,
+< CLK_PERI_AP_DMA>;
+   clock-names = "main",
+ "dma";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
 "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH 8/8] arm64: dts: add pcie nodes for MT2712

[YT Shen]

From: Honghui Zhang 

This patch add device node for mt2712 pcie.

Signed-off-by: Honghui Zhang 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 63 +++
 1 file changed, 63 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index e8afb54..976d92a 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -791,6 +791,69 @@
};
};
 
+   pcie: pcie@1170 {
+   compatible = "mediatek,mt2712-pcie";
+   device_type = "pci";
+   reg = <0 0x1170 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+   reg-names = "port0", "port1";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupts = ,
+;
+   clocks = < CLK_TOP_PE2_MAC_P0_SEL>,
+< CLK_TOP_PE2_MAC_P1_SEL>,
+< CLK_PERI_PCIE0>,
+< CLK_PERI_PCIE1>;
+   clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+   phys = < PHY_TYPE_PCIE>, < PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1";
+   bus-range = <0x00 0xff>;
+   ranges = <0x8200 0 0x2000  0x0 0x2000  0 
0x1000>;
+
+   pcie0: pcie@0,0 {
+   device_type = "pci";
+   status = "disabled";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   num-lanes = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc0 0>,
+   <0 0 0 2 _intc0 1>,
+   <0 0 0 3 _intc0 2>,
+   <0 0 0 4 _intc0 3>;
+   pcie_intc0: interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   };
+   };
+
+   pcie1: pcie@1,0 {
+   device_type = "pci";
+   status = "disabled";
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   num-lanes = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 _intc1 0>,
+   <0 0 0 2 _intc1 1>,
+   <0 0 0 3 _intc1 2>,
+   <0 0 0 4 _intc1 3>;
+   pcie_intc1: interrupt-controller {
+   interrupt-controller;
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   };
+   };
+   };
+
mfgcfg: syscon@1300 {
compatible = "mediatek,mt2712-mfgcfg", "syscon";
reg = <0 0x1300 0 0x1000>;
-- 
1.9.1

[PATCH 7/8] arm64: dts: add nand nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4f0aa65..e8afb54 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -504,6 +504,27 @@
status = "disabled";
};
 
+   nandc: nfi@1100e000 {
+   compatible = "mediatek,mt2712-nfc";
+   reg = <0 0x1100e000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_TOP_NFI2X_EN>, < CLK_PERI_NFI>;
+   clock-names = "nfi_clk", "pad_clk";
+   ecc-engine = <>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   bch: ecc@1100f000 {
+   compatible = "mediatek,mt2712-ecc";
+   reg = <0 0x1100f000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_TOP_NFI1X_CK_EN>;
+   clock-names = "nfiecc_clk";
+   status = "disabled";
+   };
+
i2c3: i2c@1101 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x1101 0 0x90>,
-- 
1.9.1

[PATCH 5/8] arm64: dts: add pwm nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 4843376..e9856fe 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -418,6 +418,34 @@
status = "disabled";
};
 
+   pwm: pwm@11006000 {
+   compatible = "mediatek,mt2712-pwm";
+   reg = <0 0x11006000 0 0x1000>;
+   #pwm-cells = <2>;
+   interrupts = ;
+   clocks = < CLK_TOP_PWM_SEL>,
+< CLK_PERI_PWM>,
+< CLK_PERI_PWM0>,
+< CLK_PERI_PWM1>,
+< CLK_PERI_PWM2>,
+< CLK_PERI_PWM3>,
+< CLK_PERI_PWM4>,
+< CLK_PERI_PWM5>,
+< CLK_PERI_PWM6>,
+< CLK_PERI_PWM7>;
+   clock-names = "top",
+ "main",
+ "pwm1",
+ "pwm2",
+ "pwm3",
+ "pwm4",
+ "pwm5",
+ "pwm6",
+ "pwm7",
+ "pwm8";
+   status = "disabled";
+   };
+
i2c0: i2c@11007000 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x11007000 0 0x90>,
-- 
1.9.1

[PATCH 4/8] arm64: dts: add spi nodes for MT2712

[YT Shen]

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 65 +++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 7bac8b6..4843376 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -463,6 +463,19 @@
status = "disabled";
};
 
+   spi0: spi@1100a000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x1100a000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI0>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
i2c3: i2c@1101 {
compatible = "mediatek,mt2712-i2c";
reg = <0 0x1101 0 0x90>,
@@ -508,6 +521,58 @@
status = "disabled";
};
 
+   spi2: spi@11015000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11015000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI2>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi3: spi@11016000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11016000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI3>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi4: spi@10012000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x10012000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_INFRA_AO_SPI0>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
+   spi5: spi@11018000 {
+   compatible = "mediatek,mt2712-spi";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0x11018000 0 0x100>;
+   interrupts = ;
+   clocks = < CLK_TOP_UNIVPLL2_D4>,
+< CLK_TOP_SPI_SEL>,
+< CLK_PERI_SPI5>;
+   clock-names = "parent-clk", "sel-clk", "spi-clk";
+   status = "disabled";
+   };
+
uart4: serial@11019000 {
compatible = "mediatek,mt2712-uart",
 "mediatek,mt6577-uart";
-- 
1.9.1

[PATCH 1/8] arm64: dts: Add USB3 related nodes for MT2712

[YT Shen]

From: Chunfeng Yun 

This patch adds USB3 related nodes for mt2712m1 platform.

Signed-off-by: Chunfeng Yun 
---
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  98 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 126 
 2 files changed, 224 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 98d6275..1353dad 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -6,6 +6,7 @@
  */
 
 /dts-v1/;
+#include 
 #include "mt2712e.dtsi"
 
 / {
@@ -41,6 +42,53 @@
regulator-max-microvolt = <100>;
};
 
+   extcon_usb: extcon_iddig {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = < 12 GPIO_ACTIVE_HIGH>;
+   };
+
+   extcon_usb1: extcon_iddig1 {
+   compatible = "linux,extcon-usb-gpio";
+   id-gpio = < 14 GPIO_ACTIVE_HIGH>;
+   };
+
+   usb_p0_vbus: regulator@2 {
+   compatible = "regulator-fixed";
+   regulator-name = "p0_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 13 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p1_vbus: regulator@3 {
+   compatible = "regulator-fixed";
+   regulator-name = "p1_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 15 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p2_vbus: regulator@4 {
+   compatible = "regulator-fixed";
+   regulator-name = "p2_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 16 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   usb_p3_vbus: regulator@5 {
+   compatible = "regulator-fixed";
+   regulator-name = "p3_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 17 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   regulator-always-on;
+   };
+
 };
 
  {
@@ -59,7 +107,57 @@
proc-supply = <_fixed_vproc1>;
 };
 
+ {
+   usb0_id_pins_float: usb0_iddig {
+   pins_iddig {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+
+   usb1_id_pins_float: usb1_iddig {
+   pins_iddig {
+   pinmux = ;
+   bias-pull-up;
+   };
+   };
+};
+
+ {
+   vbus-supply = <_p0_vbus>;
+   extcon = <_usb>;
+   dr_mode = "otg";
+   wakeup-source;
+   mediatek,u3p-dis-msk = <0x1>;
+   //enable-manual-drd;
+   //maximum-speed = "full-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_id_pins_float>;
+   status = "okay";
+};
+
+ {
+   vbus-supply = <_p1_vbus>;
+   extcon = <_usb1>;
+   dr_mode = "otg";
+   //mediatek,u3p-dis-msk = <0x1>;
+   enable-manual-drd;
+   wakeup-source;
+   //maximum-speed = "full-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_id_pins_float>;
+   status = "okay";
+};
+
  {
status = "okay";
 };
 
+_host0 {
+   vbus-supply = <_p2_vbus>;
+   status = "okay";
+};
+
+_host1 {
+   status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index ee627a7..6c228a2 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "mt2712-pinfunc.h"
 
@@ -405,6 +406,131 @@
status = "disabled";
};
 
+   ssusb: usb@11271000 {
+   compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
+   reg = <0 0x11271000 0 0x3000>,
+ <0 0x11280700 0 0x0100>;
+   reg-names = "mac", "ippc";
+   interrupts = ;
+   phys = < PHY_TYPE_USB2>,
+  < PHY_TYPE_USB2>;
+   power-domains = < MT2712_POWER_DOMAIN_USB>;
+   clocks = < CLK_TOP_USB30_SEL>;
+   clock-names = "sys_ck";
+   mediatek,syscon-wakeup = < 0x510 2>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   status = "disabled";
+
+   usb_host0: xhci@1127 {
+   compatible = "mediatek,mt2712-xhci",
+"mediatek,mtk-xhci";
+   reg = <0 0x1127 0 0x1000>;
+   reg-names = "mac";
+   interrupts = ;
+   

[PATCH v6 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index da7bd13..7aa0e98 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -25,6 +26,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87a..07bf0b9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+   "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b6cf384..f73abff 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v6 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index da7bd13..7aa0e98 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -25,6 +26,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87a..07bf0b9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+   "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b6cf384..f73abff 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v6 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 171 
 3 files changed, 204 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..f323936 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..57d0396
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   baud_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   sys_clk: dummyclk {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>, <_clk>;
+   clock-names = "baud", "bus";
+   status = "disabled";
+   };
+
+   sysirq: inter

[PATCH v6 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 171 
 3 files changed, 204 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..f323936 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..57d0396
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   baud_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   sys_clk: dummyclk {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>, <_clk>;
+   clock-names = "baud", "bus";
+   status = "disabled";
+   };
+
+   sysirq: interrupt-controller@10220a80 {
+   compatible = "mediatek,mt2712-sysirq&q

[PATCH v6 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v5:
- remove the soc node

Changes compared to v4:
- rebase to 4.13-rc1
- use two clocks (baud_clk & sys_clk) instead of one uart_clk to the correct 
bindings

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 171 +
 6 files changed, 210 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v6 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v5:
- remove the soc node

Changes compared to v4:
- rebase to 4.13-rc1
- use two clocks (baud_clk & sys_clk) instead of one uart_clk to the correct 
bindings

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 171 +
 6 files changed, 210 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

Re: [PATCH v5 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-08-01 at 14:46 +0200, Matthias Brugger wrote:
> 
> On 08/01/2017 10:51 AM, Yingjoe Chen wrote:
> > On Fri, 2017-07-28 at 19:37 +0800, YT Shen wrote:
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> >> b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> >> new file mode 100644
> >> index 000..1e135af
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > <...>
> > 
> >> +  timer {
> >> +  compatible = "arm,armv8-timer";
> >> +  interrupt-parent = <>;
> >> +  interrupts =  >> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> >> +  };
> >> +
> >> +  soc {
> >> +  #address-cells = <2>;
> >> +  #size-cells = <2>;
> >> +  compatible = "simple-bus";
> >> +  ranges;
> > 
> > Matthias,
> > 
> > I notice this have soc node.
> > Do we need to get rid of it?
> > 
> 
> Good catch. Yes please get rid of it. We should avoid artificial bus nodes. 
> As 
> soc is no real bus, we should get rid of it.

OK, we will remove the soc node and send a new version.
Thanks.

> 
> Thanks,
> Matthias

Re: [PATCH v5 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-08-01 at 14:46 +0200, Matthias Brugger wrote:
> 
> On 08/01/2017 10:51 AM, Yingjoe Chen wrote:
> > On Fri, 2017-07-28 at 19:37 +0800, YT Shen wrote:
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> >> b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> >> new file mode 100644
> >> index 000..1e135af
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > <...>
> > 
> >> +  timer {
> >> +  compatible = "arm,armv8-timer";
> >> +  interrupt-parent = <>;
> >> +  interrupts =  >> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> >> +>> +(GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> >> +  };
> >> +
> >> +  soc {
> >> +  #address-cells = <2>;
> >> +  #size-cells = <2>;
> >> +  compatible = "simple-bus";
> >> +  ranges;
> > 
> > Matthias,
> > 
> > I notice this have soc node.
> > Do we need to get rid of it?
> > 
> 
> Good catch. Yes please get rid of it. We should avoid artificial bus nodes. 
> As 
> soc is no real bus, we should get rid of it.

OK, we will remove the soc node and send a new version.
Thanks.

> 
> Thanks,
> Matthias

[PATCH v5 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 178 
 3 files changed, 211 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..f323936 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..1e135af
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   baud_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   sys_clk: dummyclk {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   

[PATCH v5 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 178 
 3 files changed, 211 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 015eb07..f323936 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..1e135af
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   baud_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   sys_clk: dummyclk {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = &

[PATCH v5 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v4:
- rebase to 4.13-rc1
- use two clocks (baud_clk & sys_clk) instead of one uart_clk to the correct 
bindings

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 178 +
 6 files changed, 217 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v5 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index da7bd13..7aa0e98 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -25,6 +26,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87a..07bf0b9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+   "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b6cf384..f73abff 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v5 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v4:
- rebase to 4.13-rc1
- use two clocks (baud_clk & sys_clk) instead of one uart_clk to the correct 
bindings

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 178 +
 6 files changed, 217 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v5 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index da7bd13..7aa0e98 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -25,6 +26,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87a..07bf0b9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+   "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index b6cf384..f73abff 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

Re: [PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-07-19 at 11:26 +0200, Matthias Brugger wrote:
> 
> On 07/19/2017 08:48 AM, YT Shen wrote:
> > On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
> >>
> >> On 06/22/2017 11:32 AM, YT Shen wrote:
> >>> This adds basic chip support for Mediatek 2712
> 
> [...]
> 
> >>> +
> >>> + uart_clk: dummy26m {
> >>> + compatible = "fixed-clock";
> >>> + clock-frequency = <2600>;
> >>> + #clock-cells = <0>;
> >>> + };
> >>> +
> 
> [...]
> 
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + uart5: serial@1000f000 {
> >>> + compatible = "mediatek,mt2712-uart",
> >>> +  "mediatek,mt6577-uart";
> >>> + reg = <0 0x1000f000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <_clk>, <_clk>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>
> >> So baud and bus clock are both 26 MHz?
> > We didn't have CCF clock support in this series.
> > After we have clock source support, we could use the correct clocks to
> > the UARTs and drop the 26MHz fixed rate UART clock.
> > 
> > The bus clock is 26MHz.  The baud clock could be from another clock
> > source, using the same 26MHz fixed clock works also.
> > 
> > 
> > [1] https://patchwork.kernel.org/patch/9670877/
> > [2] https://patchwork.kernel.org/patch/6436021/
> > 
> 
> Yes, just using one 26 MHz clock works, but it uses an deprecated 
> binding, so we should not do this, as through copying from the source of 
> other SoCs we will keep it alive forever. Anyway that's not your case, 
> as you defined the two clocks.
> 
> The device tree should reflect the HW, that's why I asked for the clock 
> frequency of both clocks. I searched the git history and it was never 
> done right before. So you could be the first :)
> 
> Thanks,
> Matthias
Ok, I want to make it clear.  The following example

baud_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <2600>;
#clock-cells = <0>;
};

sys_clk: dummyclk {
compatible = "fixed-clock";
clock-frequency = <2600>;
#clock-cells = <0>;
};

uart0: serial@11002000 {
[...]
clocks = <_clk>, <_clk>;
[...]
}

Do you think it is clear to reflect the HW that the baud clock and sys
clock can be different source or we need to choose another frequency?
Thanks.

yt.shen

Re: [PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-07-19 at 11:26 +0200, Matthias Brugger wrote:
> 
> On 07/19/2017 08:48 AM, YT Shen wrote:
> > On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
> >>
> >> On 06/22/2017 11:32 AM, YT Shen wrote:
> >>> This adds basic chip support for Mediatek 2712
> 
> [...]
> 
> >>> +
> >>> + uart_clk: dummy26m {
> >>> + compatible = "fixed-clock";
> >>> + clock-frequency = <2600>;
> >>> + #clock-cells = <0>;
> >>> + };
> >>> +
> 
> [...]
> 
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + uart5: serial@1000f000 {
> >>> + compatible = "mediatek,mt2712-uart",
> >>> +  "mediatek,mt6577-uart";
> >>> + reg = <0 0x1000f000 0 0x400>;
> >>> + interrupts = ;
> >>> + clocks = <_clk>, <_clk>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>
> >> So baud and bus clock are both 26 MHz?
> > We didn't have CCF clock support in this series.
> > After we have clock source support, we could use the correct clocks to
> > the UARTs and drop the 26MHz fixed rate UART clock.
> > 
> > The bus clock is 26MHz.  The baud clock could be from another clock
> > source, using the same 26MHz fixed clock works also.
> > 
> > 
> > [1] https://patchwork.kernel.org/patch/9670877/
> > [2] https://patchwork.kernel.org/patch/6436021/
> > 
> 
> Yes, just using one 26 MHz clock works, but it uses an deprecated 
> binding, so we should not do this, as through copying from the source of 
> other SoCs we will keep it alive forever. Anyway that's not your case, 
> as you defined the two clocks.
> 
> The device tree should reflect the HW, that's why I asked for the clock 
> frequency of both clocks. I searched the git history and it was never 
> done right before. So you could be the first :)
> 
> Thanks,
> Matthias
Ok, I want to make it clear.  The following example

baud_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <2600>;
#clock-cells = <0>;
};

sys_clk: dummyclk {
compatible = "fixed-clock";
clock-frequency = <2600>;
#clock-cells = <0>;
};

uart0: serial@11002000 {
[...]
clocks = <_clk>, <_clk>;
[...]
}

Do you think it is clear to reflect the HW that the baud clock and sys
clock can be different source or we need to choose another frequency?
Thanks.

yt.shen

Re: [PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
> 
> On 06/22/2017 11:32 AM, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
> > 
> >   3 files changed, 205 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..8c804df
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..461ee0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x000>;
> > +   };
> > +
> > +   cpu1: cpu@1 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x001>;
> > +   enable-method = "psci";
> > +   };
> > +
> > +   cpu2: cpu@200 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a72";
> > +   reg = <0x200>;
> > +   enable-method = "psci";
> > +   };
> > +   };
> > +
> > +

Re: [PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
> 
> On 06/22/2017 11:32 AM, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen 
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
> > 
> >   3 files changed, 205 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..8c804df
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..461ee0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x000>;
> > +   };
> > +
> > +   cpu1: cpu@1 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x001>;
> > +   enable-method = "psci";
> > +   };
> > +
> > +   cpu2: cpu@200 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a72";
> > +   reg = <0x200>;
> > +   enable-method = "psci";
> > +   };
> > +   };
> > +
> > +   psci {
> > +   compatible = "arm,psci-0.2";
> >

Re: [PATCH v4 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

Hi Matthias,

Just a gentle ping.
Should I rebase to 4.13-rc1 and send v5?

Thanks
yt.shen

On Thu, 2017-06-22 at 17:32 +0800, YT Shen wrote:
> MT2712 is a SoC based on 64bit ARMv8 architecture.
> MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
> evaluation board, and boot to shell ok.
> 
> This series contains document bindings, device tree including interrupt and 
> uart.
> 
> Changes compared to v3:
> - use two uart clocks refer to the bindings
> 
> Changes compared to v2:
> - remove alias from serial1 to serial5
> - remove initrd-start and initrd-end
> - change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
> - change gic-400 reg range
> 
> Changes compared to v1:
> - change subject prefix for bindings
> - change device tree license to SPDX tag.
> - change bootargs parameter to DT usage.
> - change intpol-controller to interrupt-controller
> 
> YT Shen (2):
>   dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
>   arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
> Makefile
> 
>  Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
>  .../interrupt-controller/mediatek,sysirq.txt   |   1 +
>  .../devicetree/bindings/serial/mtk-uart.txt|   1 +
>  arch/arm64/boot/dts/mediatek/Makefile  |   1 +
>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 
> +
>  6 files changed, 211 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 

Re: [PATCH v4 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

Hi Matthias,

Just a gentle ping.
Should I rebase to 4.13-rc1 and send v5?

Thanks
yt.shen

On Thu, 2017-06-22 at 17:32 +0800, YT Shen wrote:
> MT2712 is a SoC based on 64bit ARMv8 architecture.
> MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
> evaluation board, and boot to shell ok.
> 
> This series contains document bindings, device tree including interrupt and 
> uart.
> 
> Changes compared to v3:
> - use two uart clocks refer to the bindings
> 
> Changes compared to v2:
> - remove alias from serial1 to serial5
> - remove initrd-start and initrd-end
> - change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
> - change gic-400 reg range
> 
> Changes compared to v1:
> - change subject prefix for bindings
> - change device tree license to SPDX tag.
> - change bootargs parameter to DT usage.
> - change intpol-controller to interrupt-controller
> 
> YT Shen (2):
>   dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
>   arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
> Makefile
> 
>  Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
>  .../interrupt-controller/mediatek,sysirq.txt   |   1 +
>  .../devicetree/bindings/serial/mtk-uart.txt|   1 +
>  arch/arm64/boot/dts/mediatek/Makefile  |   1 +
>  arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 
> +
>  6 files changed, 211 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> 

[PATCH v4 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
 3 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..461ee0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>, <_clk>;
+   clock-names = "baud", "bus";
+   status = 

[PATCH v4 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v4 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
 3 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..461ee0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>, <_clk>;
+   clock-names = "baud", "bus";
+   status = "disabled";
+   };
+
+   sysirq: interrupt-controller@10

[PATCH v4 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 +
 6 files changed, 211 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v4 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt and 
uart.

Changes compared to v3:
- use two uart clocks refer to the bindings

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 +
 6 files changed, 211 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

Re: [PATCH v3 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Fri, 2017-06-16 at 16:33 +0200, Matthias Brugger wrote:
> 
> On 16/06/17 15:45, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >   3 files changed, 199 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..8c804df
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..65cdd4a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> [...]
> > +
> > +   uart_clk: dummy26m {
> > +   compatible = "fixed-clock";
> > +   clock-frequency = <2600>;
> > +   #clock-cells = <0>;
> > +   };
> > +
> > +   timer {
> > +   compatible = "arm,armv8-timer";
> > +   interrupt-parent = <>;
> > +   interrupts =  > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> > +   };
> > +
> > +   soc {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   compatible = "simple-bus";
> > +   ranges;
> > +
> > +   uart5: serial@1000f000 {
> > +   compatible = "mediatek,mt2712-uart",
> > +"mediatek,mt6577-uart";
> > +   reg = <0 0x1000f000 0 0x400>;
> > +   interrupts = ;
> > +   clocks = <_clk>;
> 
> uart has two clocks, baud and bus clock. Please refer to the bindings 
> descrption for more information, that's what they are for.
> 
> Please define the two dummy clocks with the correct frequency and use them.
> 
> Regards,
> Matthias
Okay, after checking
Documentation/devicetree/bindings/serial/mtk-uart.txt, I will use baud
and bus clock in the next version.

yt.shen

Re: [PATCH v3 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Fri, 2017-06-16 at 16:33 +0200, Matthias Brugger wrote:
> 
> On 16/06/17 15:45, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen 
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >   3 files changed, 199 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..8c804df
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..65cdd4a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> [...]
> > +
> > +   uart_clk: dummy26m {
> > +   compatible = "fixed-clock";
> > +   clock-frequency = <2600>;
> > +   #clock-cells = <0>;
> > +   };
> > +
> > +   timer {
> > +   compatible = "arm,armv8-timer";
> > +   interrupt-parent = <>;
> > +   interrupts =  > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> > +   };
> > +
> > +   soc {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   compatible = "simple-bus";
> > +   ranges;
> > +
> > +   uart5: serial@1000f000 {
> > +   compatible = "mediatek,mt2712-uart",
> > +"mediatek,mt6577-uart";
> > +   reg = <0 0x1000f000 0 0x400>;
> > +   interrupts = ;
> > +   clocks = <_clk>;
> 
> uart has two clocks, baud and bus clock. Please refer to the bindings 
> descrption for more information, that's what they are for.
> 
> Please define the two dummy clocks with the correct frequency and use them.
> 
> Regards,
> Matthias
Okay, after checking
Documentation/devicetree/bindings/serial/mtk-uart.txt, I will use baud
and bus clock in the next version.

yt.shen

[PATCH v2] drm/mediatek: separate color module to fixup error memory reallocation

[YT Shen]

Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
hardware settings) calls devm_kfree() and then devm_kzalloc() to
reallocate color module data structure.  But this reallocation cannnot
guarantee the new address is unchanged, but the caller will use the
old address, which is wrong.

Fix it by separate color module from general components, this patch
separate color module to independent files, like mtk_disp_ovl.c and
mtk_disp_rdma.c do

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 185 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index bf2e5be..e37b55a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,5 @@
-mediatek-drm-y := mtk_disp_ovl.o \
+mediatek-drm-y := mtk_disp_color.o \
+ mtk_disp_ovl.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
  mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
new file mode 100644
index 000..ef79a6d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_COLOR_CFG_MAIN0x0400
+#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81730x0c00
+#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
+#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
+#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
+ 0x54)
+
+#define COLOR_BYPASS_ALL   BIT(7)
+#define COLOR_SEQ_SEL  BIT(13)
+
+struct mtk_disp_color_data {
+   unsigned int color_offset;
+};
+
+/**
+ * struct mtk_disp_color - DISP_COLOR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_color {
+   struct mtk_ddp_comp ddp_comp;
+   struct drm_crtc *crtc;
+   const struct mtk_disp_color_data*data;
+};
+
+static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_color, ddp_comp);
+}
+
+static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(w, comp->regs + DISP_COLOR_WIDTH(color));
+   writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
+}
+
+static void mtk_color_start(struct mtk_ddp_comp *comp)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
+  comp->regs + DISP_COLOR_CFG_MAIN);
+   writel(0x1, comp->regs + DISP_COLOR_START(color));
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = {
+   .config = mtk_color_config,
+   .start = mtk_color_start,
+};
+
+static int mtk_disp_color_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %s: %d\n",
+   dev->of_node->full_name, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_color_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+
+   mtk_ddp_comp_unreg

[PATCH v2] drm/mediatek: separate color module to fixup error memory reallocation

[YT Shen]

Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
hardware settings) calls devm_kfree() and then devm_kzalloc() to
reallocate color module data structure.  But this reallocation cannnot
guarantee the new address is unchanged, but the caller will use the
old address, which is wrong.

Fix it by separate color module from general components, this patch
separate color module to independent files, like mtk_disp_ovl.c and
mtk_disp_rdma.c do

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 185 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index bf2e5be..e37b55a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,5 @@
-mediatek-drm-y := mtk_disp_ovl.o \
+mediatek-drm-y := mtk_disp_color.o \
+ mtk_disp_ovl.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
  mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
new file mode 100644
index 000..ef79a6d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_COLOR_CFG_MAIN0x0400
+#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81730x0c00
+#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
+#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
+#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
+ 0x54)
+
+#define COLOR_BYPASS_ALL   BIT(7)
+#define COLOR_SEQ_SEL  BIT(13)
+
+struct mtk_disp_color_data {
+   unsigned int color_offset;
+};
+
+/**
+ * struct mtk_disp_color - DISP_COLOR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_color {
+   struct mtk_ddp_comp ddp_comp;
+   struct drm_crtc *crtc;
+   const struct mtk_disp_color_data*data;
+};
+
+static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_color, ddp_comp);
+}
+
+static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(w, comp->regs + DISP_COLOR_WIDTH(color));
+   writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
+}
+
+static void mtk_color_start(struct mtk_ddp_comp *comp)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
+  comp->regs + DISP_COLOR_CFG_MAIN);
+   writel(0x1, comp->regs + DISP_COLOR_START(color));
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = {
+   .config = mtk_color_config,
+   .start = mtk_color_start,
+};
+
+static int mtk_disp_color_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %s: %d\n",
+   dev->of_node->full_name, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_color_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+
+   mtk_ddp_comp_unregister(

Re: [PATCH] drm/mediatek: fixup error memory reallocation

[YT Shen]

On Wed, 2017-06-14 at 09:19 +0800, CK Hu wrote:
> On Mon, 2017-06-12 at 15:15 +0800, YT Shen wrote:
> > Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
> > hardware settings) calls devm_kfree() and then devm_kzalloc() to
> > reallocate color module data structure.  But this reallocation cannnot
> > guarantee the new address is unchanged, but the caller will use the
> > old address, which is wrong.
> > 
> > Fix it by separate color module from general components, this patch
> > separate color module to independent files, like mtk_disp_ovl.c and
> > mtk_disp_rdma.c do
> > 
> 
> Hi, YT:
> 
> I would like the title to be something like 'separate color module to
> fixup error memory reallocation' because this is a large modification
> and its major is separating color module.
> 
> Regards,
> CK
OK, I will update the title and send again, thanks.

yt.shen

> 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/Makefile   |   3 +-
> >  drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
> > 
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
> >  5 files changed, 185 insertions(+), 81 deletions(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile 
> > b/drivers/gpu/drm/mediatek/Makefile
> > index bf2e5be..e37b55a 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -1,4 +1,5 @@
> > -mediatek-drm-y := mtk_disp_ovl.o \
> > +mediatek-drm-y := mtk_disp_color.o \
> > + mtk_disp_ovl.o \
> >   mtk_disp_rdma.o \
> >   mtk_drm_crtc.o \
> >   mtk_drm_ddp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > new file mode 100644
> > index 000..ef79a6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > @@ -0,0 +1,176 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +
> > +#define DISP_COLOR_CFG_MAIN0x0400
> > +#define DISP_COLOR_START_MT27010x0f00
> > +#define DISP_COLOR_START_MT81730x0c00
> > +#define DISP_COLOR_START(comp) 
> > ((comp)->data->color_offset)
> > +#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) 
> > + 0x50)
> > +#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
> > + 0x54)
> > +
> > +#define COLOR_BYPASS_ALL   BIT(7)
> > +#define COLOR_SEQ_SEL  BIT(13)
> > +
> > +struct mtk_disp_color_data {
> > +   unsigned int color_offset;
> > +};
> > +
> > +/**
> > + * struct mtk_disp_color - DISP_COLOR driver structure
> > + * @ddp_comp - structure containing type enum and hardware resources
> > + * @crtc - associated crtc to report irq events to
> > + */
> > +struct mtk_disp_color {
> > +   struct mtk_ddp_comp ddp_comp;
> > +   struct drm_crtc *crtc;
> > +   const struct mtk_disp_color_data*data;
> > +};
> > +
> > +static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp 
> > *comp)
> > +{
> > +   return container_of(comp, struct mtk_disp_color, ddp_comp);
> > +}
> > +
> > +static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
> > +unsigned int h, unsigned int vrefresh,
> > +unsigned int bpc)
> > +{
> > +   struct m

Re: [PATCH] drm/mediatek: fixup error memory reallocation

[YT Shen]

On Wed, 2017-06-14 at 09:19 +0800, CK Hu wrote:
> On Mon, 2017-06-12 at 15:15 +0800, YT Shen wrote:
> > Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
> > hardware settings) calls devm_kfree() and then devm_kzalloc() to
> > reallocate color module data structure.  But this reallocation cannnot
> > guarantee the new address is unchanged, but the caller will use the
> > old address, which is wrong.
> > 
> > Fix it by separate color module from general components, this patch
> > separate color module to independent files, like mtk_disp_ovl.c and
> > mtk_disp_rdma.c do
> > 
> 
> Hi, YT:
> 
> I would like the title to be something like 'separate color module to
> fixup error memory reallocation' because this is a large modification
> and its major is separating color module.
> 
> Regards,
> CK
OK, I will update the title and send again, thanks.

yt.shen

> 
> > Signed-off-by: YT Shen 
> > ---
> >  drivers/gpu/drm/mediatek/Makefile   |   3 +-
> >  drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
> > 
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
> >  5 files changed, 185 insertions(+), 81 deletions(-)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile 
> > b/drivers/gpu/drm/mediatek/Makefile
> > index bf2e5be..e37b55a 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -1,4 +1,5 @@
> > -mediatek-drm-y := mtk_disp_ovl.o \
> > +mediatek-drm-y := mtk_disp_color.o \
> > + mtk_disp_ovl.o \
> >   mtk_disp_rdma.o \
> >   mtk_drm_crtc.o \
> >   mtk_drm_ddp.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > new file mode 100644
> > index 000..ef79a6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> > @@ -0,0 +1,176 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +
> > +#define DISP_COLOR_CFG_MAIN0x0400
> > +#define DISP_COLOR_START_MT27010x0f00
> > +#define DISP_COLOR_START_MT81730x0c00
> > +#define DISP_COLOR_START(comp) 
> > ((comp)->data->color_offset)
> > +#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) 
> > + 0x50)
> > +#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
> > + 0x54)
> > +
> > +#define COLOR_BYPASS_ALL   BIT(7)
> > +#define COLOR_SEQ_SEL  BIT(13)
> > +
> > +struct mtk_disp_color_data {
> > +   unsigned int color_offset;
> > +};
> > +
> > +/**
> > + * struct mtk_disp_color - DISP_COLOR driver structure
> > + * @ddp_comp - structure containing type enum and hardware resources
> > + * @crtc - associated crtc to report irq events to
> > + */
> > +struct mtk_disp_color {
> > +   struct mtk_ddp_comp ddp_comp;
> > +   struct drm_crtc *crtc;
> > +   const struct mtk_disp_color_data*data;
> > +};
> > +
> > +static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp 
> > *comp)
> > +{
> > +   return container_of(comp, struct mtk_disp_color, ddp_comp);
> > +}
> > +
> > +static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
> > +unsigned int h, unsigned int vrefresh,
> > +unsigned int bpc)
> > +{
> > +   struct mtk_disp_color *color = com

Re: [PATCH 3/3] arm: dts: mt2701: Add display subsystem related nodes for MT2701

[YT Shen]

On Mon, 2017-06-12 at 11:13 +0200, Matthias Brugger wrote:
> 
> On 01/06/17 08:08, Erin Lo wrote:
> > From: YT Shen <yt.s...@mediatek.com>
> > 
> > This patch adds the device nodes for the DISP function blocks for MT2701
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > Signed-off-by: Erin Lo <erin...@mediatek.com>
> > ---
> >   arch/arm/boot/dts/mt2701.dtsi | 84 
> > +++
> >   1 file changed, 84 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f110d5..e20b65c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include "skeleton64.dtsi"
> >   #include "mt2701-pinfunc.h"
> >   
> > @@ -24,6 +25,11 @@
> > compatible = "mediatek,mt2701";
> > interrupt-parent = <>;
> >   
> > +   aliases {
> > +   rdma0 = 
> > +   rdma1 = 
> > +   };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -201,6 +207,16 @@
> > power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > };
> >   
> > +   mipi_tx0: mipi-dphy@1001 {
> > +   compatible = "mediatek,mt2701-mipi-tx";
> > +   reg = <0 0x1001 0 0x90>;
> > +   clocks = <>;
> > +   clock-output-names = "mipi_tx0_pll";
> > +   #clock-cells = <0>;
> > +   #phy-cells = <0>;
> > +   status = "disabled";
> > +   };
> > +
> > sysirq: interrupt-controller@10200100 {
> > compatible = "mediatek,mt2701-sysirq",
> >  "mediatek,mt6577-sysirq";
> > @@ -366,6 +382,39 @@
> > #clock-cells = <1>;
> > };
> >   
> > +   display_components: dispsys@1400 {
> > +   compatible = "mediatek,mt2701-mmsys";
> > +   reg = <0 0x1400 0 0x1000>;
> > +   power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > +   };
> 
> Can you please rebase on a recent kernel version. mt2701-mmsys node is 
> already present.
> 
> Thanks,
> Matthias
OK, we will rebase the mt2701 device tree in the next version.
Thanks.

yt.shen

> 
> > +
> > +   ovl@14007000 {
> > +   compatible = "mediatek,mt2701-disp-ovl";
> > +   reg = <0 0x14007000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_OVL>;
> > +   iommus = < MT2701_M4U_PORT_DISP_OVL_0>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > +   rdma0: rdma@14008000 {
> > +   compatible = "mediatek,mt2701-disp-rdma";
> > +   reg = <0 0x14008000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_RDMA>;
> > +   iommus = < MT2701_M4U_PORT_DISP_RDMA>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > +   wdma@14009000 {
> > +   compatible = "mediatek,mt2701-disp-wdma";
> > +   reg = <0 0x14009000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_WDMA>;
> > +   iommus = < MT2701_M4U_PORT_DISP_WDMA>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > bls: bls@1400a000 {
> > compatible = "mediatek,mt2701-disp-pwm";
> > reg = <0 0x1400a000 0 0x1000>;
> > @@ -375,6 +424,32 @@
> > status = "disabled";
> > };
> >   
> > +   color@1400b000 {
> > +   compatible = "mediatek,mt2701-disp-color";
> > +   reg = <0 0x1400b000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_COLOR>;
> > +   };
> > +
> > +   dsi: dsi@1400c000 {
> > +   compatible = "mediatek,mt2701-dsi";
> > +   reg = <0 0x1400c000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DSI_ENGINE>, < CLK_MM_DSI_DIG>,
> > +<_tx0>;
> > +   clock-names = "engine", "digital", "hs";
> > +   phys = <_tx0>;
> > +   phy-names = "dphy";
> > +   status = "disabled";
> > +   };
> > +
> > +   mutex: mutex@1400e000 {
> > +   compatible = "mediatek,mt2701-disp-mutex";
> > +   reg = <0 0x1400e000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_MUTEX_32K>;
> > +   };
> > +
> > larb0: larb@1401 {
> > compatible = "mediatek,mt2701-smi-larb";
> > reg = <0 0x1401 0 0x1000>;
> > @@ -385,6 +460,15 @@
> > power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > };
> >   
> > +   rdma1: rdma@14012000 {
> > +   compatible = "mediatek,mt2701-disp-rdma";
> > +   reg = <0 0x14012000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_RDMA1>;
> > +   iommus = < MT2701_M4U_PORT_DISP_RDMA1>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > imgsys: syscon@1500 {
> > compatible = "mediatek,mt2701-imgsys", "syscon";
> > reg = <0 0x1500 0 0x1000>;
> > 

Re: [PATCH 3/3] arm: dts: mt2701: Add display subsystem related nodes for MT2701

[YT Shen]

On Mon, 2017-06-12 at 11:13 +0200, Matthias Brugger wrote:
> 
> On 01/06/17 08:08, Erin Lo wrote:
> > From: YT Shen 
> > 
> > This patch adds the device nodes for the DISP function blocks for MT2701
> > 
> > Signed-off-by: YT Shen 
> > Signed-off-by: Erin Lo 
> > ---
> >   arch/arm/boot/dts/mt2701.dtsi | 84 
> > +++
> >   1 file changed, 84 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index 4f110d5..e20b65c 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -17,6 +17,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include "skeleton64.dtsi"
> >   #include "mt2701-pinfunc.h"
> >   
> > @@ -24,6 +25,11 @@
> > compatible = "mediatek,mt2701";
> > interrupt-parent = <>;
> >   
> > +   aliases {
> > +   rdma0 = 
> > +   rdma1 = 
> > +   };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -201,6 +207,16 @@
> > power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > };
> >   
> > +   mipi_tx0: mipi-dphy@1001 {
> > +   compatible = "mediatek,mt2701-mipi-tx";
> > +   reg = <0 0x1001 0 0x90>;
> > +   clocks = <>;
> > +   clock-output-names = "mipi_tx0_pll";
> > +   #clock-cells = <0>;
> > +   #phy-cells = <0>;
> > +   status = "disabled";
> > +   };
> > +
> > sysirq: interrupt-controller@10200100 {
> > compatible = "mediatek,mt2701-sysirq",
> >  "mediatek,mt6577-sysirq";
> > @@ -366,6 +382,39 @@
> > #clock-cells = <1>;
> > };
> >   
> > +   display_components: dispsys@1400 {
> > +   compatible = "mediatek,mt2701-mmsys";
> > +   reg = <0 0x1400 0 0x1000>;
> > +   power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > +   };
> 
> Can you please rebase on a recent kernel version. mt2701-mmsys node is 
> already present.
> 
> Thanks,
> Matthias
OK, we will rebase the mt2701 device tree in the next version.
Thanks.

yt.shen

> 
> > +
> > +   ovl@14007000 {
> > +   compatible = "mediatek,mt2701-disp-ovl";
> > +   reg = <0 0x14007000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_OVL>;
> > +   iommus = < MT2701_M4U_PORT_DISP_OVL_0>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > +   rdma0: rdma@14008000 {
> > +   compatible = "mediatek,mt2701-disp-rdma";
> > +   reg = <0 0x14008000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_RDMA>;
> > +   iommus = < MT2701_M4U_PORT_DISP_RDMA>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > +   wdma@14009000 {
> > +   compatible = "mediatek,mt2701-disp-wdma";
> > +   reg = <0 0x14009000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_WDMA>;
> > +   iommus = < MT2701_M4U_PORT_DISP_WDMA>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > bls: bls@1400a000 {
> > compatible = "mediatek,mt2701-disp-pwm";
> > reg = <0 0x1400a000 0 0x1000>;
> > @@ -375,6 +424,32 @@
> > status = "disabled";
> > };
> >   
> > +   color@1400b000 {
> > +   compatible = "mediatek,mt2701-disp-color";
> > +   reg = <0 0x1400b000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_COLOR>;
> > +   };
> > +
> > +   dsi: dsi@1400c000 {
> > +   compatible = "mediatek,mt2701-dsi";
> > +   reg = <0 0x1400c000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DSI_ENGINE>, < CLK_MM_DSI_DIG>,
> > +<_tx0>;
> > +   clock-names = "engine", "digital", "hs";
> > +   phys = <_tx0>;
> > +   phy-names = "dphy";
> > +   status = "disabled";
> > +   };
> > +
> > +   mutex: mutex@1400e000 {
> > +   compatible = "mediatek,mt2701-disp-mutex";
> > +   reg = <0 0x1400e000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_MUTEX_32K>;
> > +   };
> > +
> > larb0: larb@1401 {
> > compatible = "mediatek,mt2701-smi-larb";
> > reg = <0 0x1401 0 0x1000>;
> > @@ -385,6 +460,15 @@
> > power-domains = < MT2701_POWER_DOMAIN_DISP>;
> > };
> >   
> > +   rdma1: rdma@14012000 {
> > +   compatible = "mediatek,mt2701-disp-rdma";
> > +   reg = <0 0x14012000 0 0x1000>;
> > +   interrupts = ;
> > +   clocks = < CLK_MM_DISP_RDMA1>;
> > +   iommus = < MT2701_M4U_PORT_DISP_RDMA1>;
> > +   mediatek,larb = <>;
> > +   };
> > +
> > imgsys: syscon@1500 {
> > compatible = "mediatek,mt2701-imgsys", "syscon";
> > reg = <0 0x1500 0 0x1000>;
> > 

[PATCH v3 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
 3 files changed, 199 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..65cdd4a
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>;
+   status = "disabled";
+   };
+
+   sysirq: interrupt-controller

[PATCH v3 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  32 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
 3 files changed, 199 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..65cdd4a
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+   interrupts = ;
+   clocks = <_clk>;
+   status = "disabled";
+   };
+
+   sysirq: interrupt-controller@10220a80 {
+   compatible = "mediatek,mt2712-sysirq",
+

[PATCH v3 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v3 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v3 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt
and uart.

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller


YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 166 +
 6 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v3 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt
and uart.

Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller


YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  32 
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 166 +
 6 files changed, 205 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH] drm/mediatek: fixup error memory reallocation

[YT Shen]

Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
hardware settings) calls devm_kfree() and then devm_kzalloc() to
reallocate color module data structure.  But this reallocation cannnot
guarantee the new address is unchanged, but the caller will use the
old address, which is wrong.

Fix it by separate color module from general components, this patch
separate color module to independent files, like mtk_disp_ovl.c and
mtk_disp_rdma.c do

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 185 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index bf2e5be..e37b55a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,5 @@
-mediatek-drm-y := mtk_disp_ovl.o \
+mediatek-drm-y := mtk_disp_color.o \
+ mtk_disp_ovl.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
  mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
new file mode 100644
index 000..ef79a6d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_COLOR_CFG_MAIN0x0400
+#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81730x0c00
+#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
+#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
+#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
+ 0x54)
+
+#define COLOR_BYPASS_ALL   BIT(7)
+#define COLOR_SEQ_SEL  BIT(13)
+
+struct mtk_disp_color_data {
+   unsigned int color_offset;
+};
+
+/**
+ * struct mtk_disp_color - DISP_COLOR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_color {
+   struct mtk_ddp_comp ddp_comp;
+   struct drm_crtc *crtc;
+   const struct mtk_disp_color_data*data;
+};
+
+static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_color, ddp_comp);
+}
+
+static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(w, comp->regs + DISP_COLOR_WIDTH(color));
+   writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
+}
+
+static void mtk_color_start(struct mtk_ddp_comp *comp)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
+  comp->regs + DISP_COLOR_CFG_MAIN);
+   writel(0x1, comp->regs + DISP_COLOR_START(color));
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = {
+   .config = mtk_color_config,
+   .start = mtk_color_start,
+};
+
+static int mtk_disp_color_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %s: %d\n",
+   dev->of_node->full_name, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_color_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+
+   mtk_ddp_comp_unreg

[PATCH] drm/mediatek: fixup error memory reallocation

[YT Shen]

Previous patch (c5f228ef6c drm/mediatek: add *driver_data for different
hardware settings) calls devm_kfree() and then devm_kzalloc() to
reallocate color module data structure.  But this reallocation cannnot
guarantee the new address is unchanged, but the caller will use the
old address, which is wrong.

Fix it by separate color module from general components, this patch
separate color module to independent files, like mtk_disp_ovl.c and
mtk_disp_rdma.c do

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_color.c   | 176 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  80 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   6 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 185 insertions(+), 81 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_color.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index bf2e5be..e37b55a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,4 +1,5 @@
-mediatek-drm-y := mtk_disp_ovl.o \
+mediatek-drm-y := mtk_disp_color.o \
+ mtk_disp_ovl.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
  mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
new file mode 100644
index 000..ef79a6d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_COLOR_CFG_MAIN0x0400
+#define DISP_COLOR_START_MT27010x0f00
+#define DISP_COLOR_START_MT81730x0c00
+#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
+#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
+#define DISP_COLOR_HEIGHT(comp)(DISP_COLOR_START(comp) 
+ 0x54)
+
+#define COLOR_BYPASS_ALL   BIT(7)
+#define COLOR_SEQ_SEL  BIT(13)
+
+struct mtk_disp_color_data {
+   unsigned int color_offset;
+};
+
+/**
+ * struct mtk_disp_color - DISP_COLOR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_color {
+   struct mtk_ddp_comp ddp_comp;
+   struct drm_crtc *crtc;
+   const struct mtk_disp_color_data*data;
+};
+
+static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_color, ddp_comp);
+}
+
+static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(w, comp->regs + DISP_COLOR_WIDTH(color));
+   writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
+}
+
+static void mtk_color_start(struct mtk_ddp_comp *comp)
+{
+   struct mtk_disp_color *color = comp_to_color(comp);
+
+   writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
+  comp->regs + DISP_COLOR_CFG_MAIN);
+   writel(0x1, comp->regs + DISP_COLOR_START(color));
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = {
+   .config = mtk_color_config,
+   .start = mtk_color_start,
+};
+
+static int mtk_disp_color_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %s: %d\n",
+   dev->of_node->full_name, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_color_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_color *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+
+   mtk_ddp_comp_unregister(

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 13:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >   3 files changed, 206 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> 
> Just declare serial0 here, as you don't use the others.
Ok, will remove the others.

Sorry for the late reply.

> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   linux,initrd-start = <0x4500>;
> > +   linux,initrd-end   = <0x4a00>;
> 
> initrd-start and end should be dynamically set by the bootloader and not 
> via a chosen node. Is your bootloader not able to do that?
OK, will remove initrd start and end later.
Yes, current bootloader I used is new development and it does not send
any parameters now

> 
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> 
> do you mean cortex-a53?
No, the cpu is cortex-a35.
Although I ca

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote:
> 
> On 31/05/17 13:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen 
> > ---
> >   arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >   arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
> >   arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >   3 files changed, 206 insertions(+)
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >   create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >   dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> 
> Just declare serial0 here, as you don't use the others.
Ok, will remove the others.

Sorry for the late reply.

> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   linux,initrd-start = <0x4500>;
> > +   linux,initrd-end   = <0x4a00>;
> 
> initrd-start and end should be dynamically set by the bootloader and not 
> via a chosen node. Is your bootloader not able to do that?
OK, will remove initrd start and end later.
Yes, current bootloader I used is new development and it does not send
any parameters now

> 
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> 
> do you mean cortex-a53?
No, the cpu is cortex-a35.
Although I cannot find other cortex-a35 description in mainline kernel.

Thanks for the r

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >  3 files changed, 206 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   linux,initrd-start = <0x4500>;
> > +   linux,initrd-end   = <0x4a00>;
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x000>;
> > +   };
> > +
> > +   cpu1: cpu@1 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x001>;
> > +   enable-method = "psci";
> > +   };
> > +
> > +   cpu2: cpu@200 {
> > +   device_type = 

Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen 
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
> > 
> >  3 files changed, 206 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..e526c0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,39 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:921600n8";
> > +   linux,initrd-start = <0x4500>;
> > +   linux,initrd-end   = <0x4a00>;
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..6df0da9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,166 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   core1 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +
> > +   cluster1 {
> > +   core0 {
> > +   cpu = <>;
> > +   };
> > +   };
> > +   };
> > +
> > +   cpu0: cpu@0 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x000>;
> > +   };
> > +
> > +   cpu1: cpu@1 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a35";
> > +   reg = <0x001>;
> > +   enable-method = "psci";
> > +   };
> > +
> > +   cpu2: cpu@200 {
> > +   device_type = "cpu";
> > +   compatible = "arm,cortex-a72";
> > +   

[PATCH v2 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
 3 files changed, 206 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..e526c0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   linux,initrd-start = <0x4500>;
+   linux,initrd-end   = <0x4a00>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..6df0da9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+

[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt, uart.

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  39 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 166 +
 6 files changed, 212 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  39 +++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 166 
 3 files changed, 206 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..e526c0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   stdout-path = "serial0:921600n8";
+   linux,initrd-start = <0x4500>;
+   linux,initrd-end   = <0x4a00>;
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..6df0da9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupt-parent = <>;
+   interrupts = ,
+,
+,
+;
+   };
+
+   soc {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   compatible = "simple-bus";
+   ranges;
+
+   uart5: serial@1000f000 {
+   compatible = "mediatek,mt2712-uart",
+"mediatek,mt6577-uart";
+   reg = <0 0x1000f000 0 0x400>;
+ 

[PATCH v2 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested on MT2712 
evaluation board, and boot to shell ok.

This series contains document bindings, device tree including interrupt, uart.

Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller

YT Shen (2):
  dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  39 +
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 166 +
 6 files changed, 212 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH v2 1/2] dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

Re: [PATCH 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-05-23 at 10:01 -0500, Rob Herring wrote:
> On Fri, May 19, 2017 at 07:09:46PM +0800, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen <yt.s...@mediatek.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  44 +++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
> > 
> >  3 files changed, 217 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..40b0c91
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,44 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> 
> You may want to dual license this. Not sure what the rest of Mediatek 
> dts files do though. Also, you can use SPDX tag here if you want.
Okay, will change to SPDX tag and dual license in the next version.
  SPDX-License-Identifier: (GPL-2.0 OR MIT)

> 
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   bootargs = "console=ttyS0,921600n1 initrd=0x4500,90M";
> 
> Both of these have a way to be expressed in DT. For the initrd, the 
> bootloader should be setting the address and size anyway.
OK, will change to DT usage.
  stdout-path = "serial0:921600n8";
  linux,initrd-start = <...>;
  linux,initrd-end = <...>;

> 
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..40747a9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <yt.s...@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
>

Re: [PATCH 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

On Tue, 2017-05-23 at 10:01 -0500, Rob Herring wrote:
> On Fri, May 19, 2017 at 07:09:46PM +0800, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> > 
> > Signed-off-by: YT Shen 
> > ---
> >  arch/arm64/boot/dts/mediatek/Makefile   |   1 +
> >  arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  44 +++
> >  arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
> > 
> >  3 files changed, 217 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> >  create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
> > b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> >  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
> > b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 000..40b0c91
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,44 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> 
> You may want to dual license this. Not sure what the rest of Mediatek 
> dts files do though. Also, you can use SPDX tag here if you want.
Okay, will change to SPDX tag and dual license in the next version.
  SPDX-License-Identifier: (GPL-2.0 OR MIT)

> 
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > +   model = "MediaTek MT2712 evaluation board";
> > +   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > +   aliases {
> > +   serial0 = 
> > +   serial1 = 
> > +   serial2 = 
> > +   serial3 = 
> > +   serial4 = 
> > +   serial5 = 
> > +   };
> > +
> > +   memory@4000 {
> > +   device_type = "memory";
> > +   reg = <0 0x4000 0 0x8000>;
> > +   };
> > +
> > +   chosen {
> > +   bootargs = "console=ttyS0,921600n1 initrd=0x4500,90M";
> 
> Both of these have a way to be expressed in DT. For the initrd, the 
> bootloader should be setting the address and size anyway.
OK, will change to DT usage.
  stdout-path = "serial0:921600n8";
  linux,initrd-start = <...>;
  linux,initrd-end = <...>;

> 
> > +   };
> > +};
> > +
> > + {
> > +   status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> > b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 000..40747a9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +/ {
> > +   compatible = "mediatek,mt2712";
> > +   interrupt-parent = <>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +
> > +   cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +
> > +   cpu-map {
> > +   cluster0 {
>

[PATCH 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  44 +++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
 3 files changed, 217 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..40b0c91
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   bootargs = "console=ttyS0,921600n1 initrd=0x4500,90M";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..40747a9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <yt.s...@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };

[PATCH 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile

[YT Shen]

This adds basic chip support for Mediatek 2712

Signed-off-by: YT Shen 
---
 arch/arm64/boot/dts/mediatek/Makefile   |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts |  44 +++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi   | 172 
 3 files changed, 217 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile 
b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 000..40b0c91
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+   model = "MediaTek MT2712 evaluation board";
+   compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   };
+
+   memory@4000 {
+   device_type = "memory";
+   reg = <0 0x4000 0 0x8000>;
+   };
+
+   chosen {
+   bootargs = "console=ttyS0,921600n1 initrd=0x4500,90M";
+   };
+};
+
+ {
+   status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 000..40747a9
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+/ {
+   compatible = "mediatek,mt2712";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <>;
+   };
+   core1 {
+   cpu = <>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <>;
+   };
+   };
+   };
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x000>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a35";
+   reg = <0x001>;
+   enable-method = "psci";
+   };
+
+   cpu2: cpu@200 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72";
+   reg = <0x200>;
+   enable-method = "psci";
+   };
+   };
+
+   psci {
+   compatible = "arm,psci-0.2";
+   method = "smc";
+   };
+
+   uart_clk: dummy26m {
+   compatible = "fixed-clock";
+   clock-frequency = <2600>;
+   #clock-cells = <0>;
+   };
+
+   timer {
+   compatible = "arm,armv8-timer";
+

[PATCH 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested
on MT2712 evaluation board, and boot to shell ok.

This series contains document bindings, device tree including
interrupt, uart.

YT Shen (2):
  Document: DT: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  44 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 +
 6 files changed, 223 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH 0/2] Add basic support for Mediatek MT2712 SoC

[YT Shen]

MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173.  This patchset was tested
on MT2712 evaluation board, and boot to shell ok.

This series contains document bindings, device tree including
interrupt, uart.

YT Shen (2):
  Document: DT: Add bindings for Mediatek MT2712 SoC Platform
  arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile

 Documentation/devicetree/bindings/arm/mediatek.txt |   4 +
 .../interrupt-controller/mediatek,sysirq.txt   |   1 +
 .../devicetree/bindings/serial/mtk-uart.txt|   1 +
 arch/arm64/boot/dts/mediatek/Makefile  |   1 +
 arch/arm64/boot/dts/mediatek/mt2712-evb.dts|  44 ++
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi  | 172 +
 6 files changed, 223 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi

-- 
1.9.1

[PATCH 1/2] Document: DT: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH 1/2] Document: DT: Add bindings for Mediatek MT2712 SoC Platform

[YT Shen]

This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.

Signed-off-by: YT Shen 
---
 Documentation/devicetree/bindings/arm/mediatek.txt| 4 
 .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt  | 1 +
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 3 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
 
 compatible: Must contain one of
"mediatek,mt2701"
+   "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
 - Evaluation board for MT2701:
 Required root node properties:
   - compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+Required root node properties:
+  - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
 - Evaluation board for MT6580:
 Required root node properties:
   - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt 
b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+   "mediatek,mt2712-sysirq"
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
 - interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt 
b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
 Required properties:
 - compatible should contain:
   * "mediatek,mt2701-uart" for MT2701 compatible UARTS
+  * "mediatek,mt2712-uart" for MT2712 compatible UARTS
   * "mediatek,mt6580-uart" for MT6580 compatible UARTS
   * "mediatek,mt6582-uart" for MT6582 compatible UARTS
   * "mediatek,mt6589-uart" for MT6589 compatible UARTS
-- 
1.9.1

[PATCH v13 04/12] drm/mediatek: add shadow register support

[YT Shen]

We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 -
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 25 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |  2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |  1 +
 4 files changed, 74 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index a73de1e..4988e50 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -329,6 +329,42 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc 
*mtk_crtc)
pm_runtime_put(drm->dev);
 }
 
+static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
+{
+   struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
+   struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+   unsigned int i;
+
+   /*
+* TODO: instead of updating the registers here, we should prepare
+* working registers in atomic_commit and let the hardware command
+* queue update module registers on vblank.
+*/
+   if (state->pending_config) {
+   mtk_ddp_comp_config(ovl, state->pending_width,
+   state->pending_height,
+   state->pending_vrefresh, 0);
+
+   state->pending_config = false;
+   }
+
+   if (mtk_crtc->pending_planes) {
+   for (i = 0; i < OVL_LAYER_NR; i++) {
+   struct drm_plane *plane = _crtc->planes[i];
+   struct mtk_plane_state *plane_state;
+
+   plane_state = to_mtk_plane_state(plane->state);
+
+   if (plane_state->pending.config) {
+   mtk_ddp_comp_layer_config(ovl, i, plane_state);
+   plane_state->pending.config = false;
+   }
+   }
+   mtk_crtc->pending_planes = false;
+   }
+}
+
 static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
@@ -405,6 +441,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  struct drm_crtc_state *old_crtc_state)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_drm_private *priv = crtc->dev->dev_private;
unsigned int pending_planes = 0;
int i;
 
@@ -426,6 +463,12 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc 
*crtc,
if (crtc->state->color_mgmt_changed)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+
+   if (priv->data->shadow_register) {
+   mtk_disp_mutex_acquire(mtk_crtc->mutex);
+   mtk_crtc_ddp_config(crtc);
+   mtk_disp_mutex_release(mtk_crtc->mutex);
+   }
 }
 
 static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -471,36 +514,10 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
-   unsigned int i;
+   struct mtk_drm_private *priv = crtc->dev->dev_private;
 
-   /*
-* TODO: instead of updating the registers here, we should prepare
-* working registers in atomic_commit and let the hardware command
-* queue update module registers on vblank.
-*/
-   if (state->pending_config) {
-   mtk_ddp_comp_config(ovl, state->pending_width,
-   state->pending_height,
-   state->pending_vrefresh, 0);
-
-   state->pending_config = false;
-   }
-
-   if (mtk_crtc->pending_planes) {
-   for (i = 0; i < OVL_LAYER_NR; i++) {
-   struct drm_plane *plane = _crtc->planes[i];
-   struct mtk_plane_state *plane_state;
-
-   plane_state = to_mtk_plane_state(plane->state);
-
-   if (plane_state->pending.config) {
-   mtk_ddp_comp_layer_config(ovl, i, plane_state);
-   plane_state->pending.config = false;
-   }
-   }
-   mtk_crtc->pending_planes = false;
-   }
+   if (!priv->data->shadow_register)
+   mtk_crtc_dd

[PATCH v13 04/12] drm/mediatek: add shadow register support

[YT Shen]

We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.

Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 -
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 25 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |  2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |  1 +
 4 files changed, 74 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index a73de1e..4988e50 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -329,6 +329,42 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc 
*mtk_crtc)
pm_runtime_put(drm->dev);
 }
 
+static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
+{
+   struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
+   struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+   unsigned int i;
+
+   /*
+* TODO: instead of updating the registers here, we should prepare
+* working registers in atomic_commit and let the hardware command
+* queue update module registers on vblank.
+*/
+   if (state->pending_config) {
+   mtk_ddp_comp_config(ovl, state->pending_width,
+   state->pending_height,
+   state->pending_vrefresh, 0);
+
+   state->pending_config = false;
+   }
+
+   if (mtk_crtc->pending_planes) {
+   for (i = 0; i < OVL_LAYER_NR; i++) {
+   struct drm_plane *plane = _crtc->planes[i];
+   struct mtk_plane_state *plane_state;
+
+   plane_state = to_mtk_plane_state(plane->state);
+
+   if (plane_state->pending.config) {
+   mtk_ddp_comp_layer_config(ovl, i, plane_state);
+   plane_state->pending.config = false;
+   }
+   }
+   mtk_crtc->pending_planes = false;
+   }
+}
+
 static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
@@ -405,6 +441,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  struct drm_crtc_state *old_crtc_state)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_drm_private *priv = crtc->dev->dev_private;
unsigned int pending_planes = 0;
int i;
 
@@ -426,6 +463,12 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc 
*crtc,
if (crtc->state->color_mgmt_changed)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+
+   if (priv->data->shadow_register) {
+   mtk_disp_mutex_acquire(mtk_crtc->mutex);
+   mtk_crtc_ddp_config(crtc);
+   mtk_disp_mutex_release(mtk_crtc->mutex);
+   }
 }
 
 static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -471,36 +514,10 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
-   unsigned int i;
+   struct mtk_drm_private *priv = crtc->dev->dev_private;
 
-   /*
-* TODO: instead of updating the registers here, we should prepare
-* working registers in atomic_commit and let the hardware command
-* queue update module registers on vblank.
-*/
-   if (state->pending_config) {
-   mtk_ddp_comp_config(ovl, state->pending_width,
-   state->pending_height,
-   state->pending_vrefresh, 0);
-
-   state->pending_config = false;
-   }
-
-   if (mtk_crtc->pending_planes) {
-   for (i = 0; i < OVL_LAYER_NR; i++) {
-   struct drm_plane *plane = _crtc->planes[i];
-   struct mtk_plane_state *plane_state;
-
-   plane_state = to_mtk_plane_state(plane->state);
-
-   if (plane_state->pending.config) {
-   mtk_ddp_comp_layer_config(ovl, i, plane_state);
-   plane_state->pending.config = false;
-   }
-   }
-   mtk_crtc->pending_planes = false;
-   }
+   if (!priv->data->shadow_register)
+   mtk_crtc_ddp_config(crtc);
 
mtk_drm_finish_page_flip(mtk_c

[PATCH v13 12/12] drm/mediatek: add support for Mediatek SoC MT2701

[YT Shen]

This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |  8 
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|  6 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 17 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  7 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 29 +
 drivers/gpu/drm/mediatek/mtk_dsi.c  |  1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c  |  6 ++
 7 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4552178..a14d7d6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -35,6 +35,7 @@
 #define DISP_REG_OVL_PITCH(n)  (0x0044 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_CTRL(n)  (0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)   (0x00c8 + 0x20 * (n))
+#define DISP_REG_OVL_ADDR_MT2701   0x0040
 #define DISP_REG_OVL_ADDR_MT8173   0x0f40
 #define DISP_REG_OVL_ADDR(ovl, n)  ((ovl)->data->addr + 0x20 * (n))
 
@@ -303,12 +304,19 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT2701,
+   .fmt_rgb565_is_0 = false,
+};
+
 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT8173,
.fmt_rgb565_is_0 = true,
 };
 
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = _ovl_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index e5e5318..b68a513 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -236,11 +236,17 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
+   .fifo_size = SZ_4K,
+};
+
 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
.fifo_size = SZ_8K,
 };
 
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-rdma",
+ .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
  .data = _rdma_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index a9b209c..8130f3d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -60,6 +60,13 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
 #define MT8173_MUTEX_MOD_DISP_OD   BIT(25)
 
+#define MT2701_MUTEX_MOD_DISP_OVL  BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS  BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1BIT(12)
+
 #define MUTEX_SOF_SINGLE_MODE  0
 #define MUTEX_SOF_DSI0 1
 #define MUTEX_SOF_DSI1 2
@@ -92,6 +99,15 @@ struct mtk_ddp {
const unsigned int  *mutex_mod;
 };
 
+static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
+   [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
+   [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
+   [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
+};
+
 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id ddp_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f6e853a..8b52416 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -39,6 +39,7 @@
 #define DISP_REG_UFO_START 0x
 
 #define 

[PATCH v13 12/12] drm/mediatek: add support for Mediatek SoC MT2701

[YT Shen]

This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.

Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |  8 
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|  6 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 17 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  7 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  | 29 +
 drivers/gpu/drm/mediatek/mtk_dsi.c  |  1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c  |  6 ++
 7 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4552178..a14d7d6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -35,6 +35,7 @@
 #define DISP_REG_OVL_PITCH(n)  (0x0044 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_CTRL(n)  (0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)   (0x00c8 + 0x20 * (n))
+#define DISP_REG_OVL_ADDR_MT2701   0x0040
 #define DISP_REG_OVL_ADDR_MT8173   0x0f40
 #define DISP_REG_OVL_ADDR(ovl, n)  ((ovl)->data->addr + 0x20 * (n))
 
@@ -303,12 +304,19 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT2701,
+   .fmt_rgb565_is_0 = false,
+};
+
 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT8173,
.fmt_rgb565_is_0 = true,
 };
 
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = _ovl_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index e5e5318..b68a513 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -236,11 +236,17 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
+   .fifo_size = SZ_4K,
+};
+
 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
.fifo_size = SZ_8K,
 };
 
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-rdma",
+ .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
  .data = _rdma_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index a9b209c..8130f3d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -60,6 +60,13 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
 #define MT8173_MUTEX_MOD_DISP_OD   BIT(25)
 
+#define MT2701_MUTEX_MOD_DISP_OVL  BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS  BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1BIT(12)
+
 #define MUTEX_SOF_SINGLE_MODE  0
 #define MUTEX_SOF_DSI0 1
 #define MUTEX_SOF_DSI1 2
@@ -92,6 +99,15 @@ struct mtk_ddp {
const unsigned int  *mutex_mod;
 };
 
+static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
+   [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
+   [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
+   [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
+};
+
 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -390,6 +406,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id ddp_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
 };
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f6e853a..8b52416 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -39,6 +39,7 @@
 #define DISP_REG_UFO_START 0x
 
 #define DISP_COLOR_CFG_MAIN0x0400
+#def

[PATCH v13 10/12] drm/mediatek: add non-continuous clock mode and EOT packet control

[YT Shen]

This patch will update dsi clock control method.
1. dsi non-continue clock mode will enhance antistatic effect for panel
2. EOT packet control will judge whether dsi send end of packet or not
by customize

Signed-off-by: shaoming chen <shaoming.c...@mediatek.com>
Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2e2cc3a..09528e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -431,6 +431,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
break;
}
 
+   tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+   tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 }
 
-- 
1.9.1

[PATCH v13 11/12] drm/mediatek: update DSI sub driver flow for sending commands to panel

[YT Shen]

This patch update enable/disable flow of DSI module.
Original flow works on there is a bridge chip: DSI -> bridge -> panel.
In this case: DSI -> panel, the DSI sub driver flow should be updated.
We need to initialize DSI first so that we can send commands to panel.

Signed-off-by: shaoming chen <shaoming.c...@mediatek.com>
Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 259 ++---
 1 file changed, 158 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 09528e2..b6eac92 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -126,6 +126,10 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)
 
+#define DSI_VM_CMD_CON 0x130
+#define VM_CMD_EN  BIT(0)
+#define TS_VFP_EN  BIT(5)
+
 #define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
@@ -239,85 +243,6 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 }
 
-static int mtk_dsi_poweron(struct mtk_dsi *dsi)
-{
-   struct device *dev = dsi->dev;
-   int ret;
-   u64 pixel_clock, total_bits;
-   u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
-
-   if (++dsi->refcount != 1)
-   return 0;
-
-   switch (dsi->format) {
-   case MIPI_DSI_FMT_RGB565:
-   bit_per_pixel = 16;
-   break;
-   case MIPI_DSI_FMT_RGB666_PACKED:
-   bit_per_pixel = 18;
-   break;
-   case MIPI_DSI_FMT_RGB666:
-   case MIPI_DSI_FMT_RGB888:
-   default:
-   bit_per_pixel = 24;
-   break;
-   }
-
-   /**
-* vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
-* htotal_time = htotal * byte_per_pixel / num_lanes
-* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
-* mipi_ratio = (htotal_time + overhead_time) / htotal_time
-* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
-*/
-   pixel_clock = dsi->vm.pixelclock * 1000;
-   htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
-   dsi->vm.hsync_len;
-   htotal_bits = htotal * bit_per_pixel;
-
-   overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
-   T_HS_EXIT;
-   overhead_bits = overhead_cycles * dsi->lanes * 8;
-   total_bits = htotal_bits + overhead_bits;
-
-   dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
- htotal * dsi->lanes);
-
-   ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
-   if (ret < 0) {
-   dev_err(dev, "Failed to set data rate: %d\n", ret);
-   goto err_refcount;
-   }
-
-   phy_power_on(dsi->phy);
-
-   ret = clk_prepare_enable(dsi->engine_clk);
-   if (ret < 0) {
-   dev_err(dev, "Failed to enable engine clock: %d\n", ret);
-   goto err_phy_power_off;
-   }
-
-   ret = clk_prepare_enable(dsi->digital_clk);
-   if (ret < 0) {
-   dev_err(dev, "Failed to enable digital clock: %d\n", ret);
-   goto err_disable_engine_clk;
-   }
-
-   mtk_dsi_enable(dsi);
-   mtk_dsi_reset_engine(dsi);
-   mtk_dsi_phy_timconfig(dsi);
-
-   return 0;
-
-err_disable_engine_clk:
-   clk_disable_unprepare(dsi->engine_clk);
-err_phy_power_off:
-   phy_power_off(dsi->phy);
-err_refcount:
-   dsi->refcount--;
-   return ret;
-}
-
 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -365,16 +290,23 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
u32 vid_mode = CMD_MODE;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
-   vid_mode = SYNC_PULSE_MODE;
-
-   if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
-   !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
+   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
vid_mode = BURST_MODE;
+   else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+   vid_mode = SYNC_PULSE_MODE;
+   else
+   vid_mode = SYNC_EVENT_MODE;
}
 
writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 }
 
+static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
+{
+   mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, V

[PATCH v13 10/12] drm/mediatek: add non-continuous clock mode and EOT packet control

[YT Shen]

This patch will update dsi clock control method.
1. dsi non-continue clock mode will enhance antistatic effect for panel
2. EOT packet control will judge whether dsi send end of packet or not
by customize

Signed-off-by: shaoming chen 
Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2e2cc3a..09528e2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -431,6 +431,9 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
break;
}
 
+   tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
+   tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 }
 
-- 
1.9.1

[PATCH v13 11/12] drm/mediatek: update DSI sub driver flow for sending commands to panel

[YT Shen]

This patch update enable/disable flow of DSI module.
Original flow works on there is a bridge chip: DSI -> bridge -> panel.
In this case: DSI -> panel, the DSI sub driver flow should be updated.
We need to initialize DSI first so that we can send commands to panel.

Signed-off-by: shaoming chen 
Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 259 ++---
 1 file changed, 158 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 09528e2..b6eac92 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -126,6 +126,10 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)
 
+#define DSI_VM_CMD_CON 0x130
+#define VM_CMD_EN  BIT(0)
+#define TS_VFP_EN  BIT(5)
+
 #define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
@@ -239,85 +243,6 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 }
 
-static int mtk_dsi_poweron(struct mtk_dsi *dsi)
-{
-   struct device *dev = dsi->dev;
-   int ret;
-   u64 pixel_clock, total_bits;
-   u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
-
-   if (++dsi->refcount != 1)
-   return 0;
-
-   switch (dsi->format) {
-   case MIPI_DSI_FMT_RGB565:
-   bit_per_pixel = 16;
-   break;
-   case MIPI_DSI_FMT_RGB666_PACKED:
-   bit_per_pixel = 18;
-   break;
-   case MIPI_DSI_FMT_RGB666:
-   case MIPI_DSI_FMT_RGB888:
-   default:
-   bit_per_pixel = 24;
-   break;
-   }
-
-   /**
-* vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
-* htotal_time = htotal * byte_per_pixel / num_lanes
-* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
-* mipi_ratio = (htotal_time + overhead_time) / htotal_time
-* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
-*/
-   pixel_clock = dsi->vm.pixelclock * 1000;
-   htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
-   dsi->vm.hsync_len;
-   htotal_bits = htotal * bit_per_pixel;
-
-   overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
-   T_HS_EXIT;
-   overhead_bits = overhead_cycles * dsi->lanes * 8;
-   total_bits = htotal_bits + overhead_bits;
-
-   dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
- htotal * dsi->lanes);
-
-   ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
-   if (ret < 0) {
-   dev_err(dev, "Failed to set data rate: %d\n", ret);
-   goto err_refcount;
-   }
-
-   phy_power_on(dsi->phy);
-
-   ret = clk_prepare_enable(dsi->engine_clk);
-   if (ret < 0) {
-   dev_err(dev, "Failed to enable engine clock: %d\n", ret);
-   goto err_phy_power_off;
-   }
-
-   ret = clk_prepare_enable(dsi->digital_clk);
-   if (ret < 0) {
-   dev_err(dev, "Failed to enable digital clock: %d\n", ret);
-   goto err_disable_engine_clk;
-   }
-
-   mtk_dsi_enable(dsi);
-   mtk_dsi_reset_engine(dsi);
-   mtk_dsi_phy_timconfig(dsi);
-
-   return 0;
-
-err_disable_engine_clk:
-   clk_disable_unprepare(dsi->engine_clk);
-err_phy_power_off:
-   phy_power_off(dsi->phy);
-err_refcount:
-   dsi->refcount--;
-   return ret;
-}
-
 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -365,16 +290,23 @@ static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
u32 vid_mode = CMD_MODE;
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
-   vid_mode = SYNC_PULSE_MODE;
-
-   if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
-   !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
+   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
vid_mode = BURST_MODE;
+   else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+   vid_mode = SYNC_PULSE_MODE;
+   else
+   vid_mode = SYNC_EVENT_MODE;
}
 
writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 }
 
+static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
+{
+   mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
+   mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
+}
+
 static vo

[PATCH v13 08/12] drm/mediatek: add dsi interrupt control

[YT Shen]

From: shaoming chen 

add dsi interrupt control

Signed-off-by: shaoming chen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d66b98..57955636 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,6 +30,16 @@
 
 #define DSI_START  0x00
 
+#define DSI_INTEN  0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG   BIT(0)
+#define CMD_DONE_INT_FLAG  BIT(1)
+#define TE_RDY_INT_FLAGBIT(2)
+#define VM_DONE_INT_FLAG   BIT(3)
+#define EXT_TE_RDY_INT_FLAGBIT(4)
+#define DSI_BUSY   BIT(31)
+
 #define DSI_CON_CTRL   0x10
 #define DSI_RESET  BIT(0)
 #define DSI_EN BIT(1)
@@ -71,6 +82,9 @@
 
 #define DSI_HSTX_CKL_WC0x64
 
+#define DSI_RACK   0x84
+#define RACK   BIT(0)
+
 #define DSI_PHY_LCCON  0x104
 #define LC_HS_TX_ENBIT(0)
 #define LC_ULPM_EN BIT(1)
@@ -137,6 +151,8 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+   u32 irq_data;
+   wait_queue_head_t irq_wait_queue;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -469,6 +485,64 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
 }
 
+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+   u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
+
+   writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
+{
+   dsi->irq_data |= irq_bit;
+}
+
+static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 
irq_bit)
+{
+   dsi->irq_data &= ~irq_bit;
+}
+
+static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 
irq_flag,
+unsigned int timeout)
+{
+   s32 ret = 0;
+   unsigned long jiffies = msecs_to_jiffies(timeout);
+
+   ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
+  dsi->irq_data & irq_flag,
+  jiffies);
+   if (ret == 0) {
+   DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
+
+   mtk_dsi_enable(dsi);
+   mtk_dsi_reset_engine(dsi);
+   }
+
+   return ret;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+   struct mtk_dsi *dsi = dev_id;
+   u32 status, tmp;
+   u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
+
+   status = readl(dsi->regs + DSI_INTSTA) & flag;
+
+   if (status) {
+   do {
+   mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+   tmp = readl(dsi->regs + DSI_INTSTA);
+   } while (tmp & DSI_BUSY);
+
+   mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
+   mtk_dsi_irq_data_set(dsi, status);
+   wake_up_interruptible(>irq_wait_queue);
+   }
+
+   return IRQ_HANDLED;
+}
+
 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 {
if (WARN_ON(dsi->refcount == 0))
@@ -517,6 +591,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 
mtk_dsi_ps_control_vact(dsi);
mtk_dsi_config_vdo_timing(dsi);
+   mtk_dsi_set_interrupt_enable(dsi);
 
mtk_dsi_set_mode(dsi);
mtk_dsi_clk_hs_mode(dsi, 1);
@@ -800,6 +875,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *remote_node, *endpoint;
struct resource *regs;
+   int irq_num;
int comp_id;
int ret;
 
@@ -876,6 +952,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
 
+   irq_num = platform_get_irq(pdev, 0);
+   if (irq_num < 0) {
+   dev_err(>dev, "failed to request dsi irq resource\n");
+   return -EPROBE_DEFER;
+   }
+
+   irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
+   ret = devm_request_irq(>dev, irq_num, mtk_dsi_irq,
+  IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
+   if (ret) {
+   dev_err(>dev, "failed to request mediatek dsi irq\n");
+   return -EPROBE_DEFER;
+   }
+
+   init_waitqueue_head(>irq_wait_queue);
+
platform_set_drvdata(pdev, dsi);
 
return component_add(>dev, _dsi_component_ops);
-- 
1.9.1

[PATCH v13 09/12] drm/mediatek: add dsi transfer function

[YT Shen]

From: shaoming chen 

add dsi read/write commands for transfer function

Signed-off-by: shaoming chen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 168 -
 1 file changed, 166 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 57955636..2e2cc3a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mtk_drm_ddp_comp.h"
@@ -80,8 +81,16 @@
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
 
+#define DSI_CMDQ_SIZE  0x60
+#define CMDQ_SIZE  0x3f
+
 #define DSI_HSTX_CKL_WC0x64
 
+#define DSI_RX_DATA0   0x74
+#define DSI_RX_DATA1   0x78
+#define DSI_RX_DATA2   0x7c
+#define DSI_RX_DATA3   0x80
+
 #define DSI_RACK   0x84
 #define RACK   BIT(0)
 
@@ -117,6 +126,15 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)
 
+#define DSI_CMDQ0  0x180
+#define CONFIG (0xff << 0)
+#define SHORT_PACKET   0
+#define LONG_PACKET2
+#define BTABIT(2)
+#define DATA_ID(0xff << 8)
+#define DATA_0 (0xff << 16)
+#define DATA_1 (0xff << 24)
+
 #define T_LPX  5
 #define T_HS_PREP  6
 #define T_HS_TRAIL 8
@@ -125,6 +143,12 @@
 
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
+#define MTK_DSI_HOST_IS_READ(type) \
+   ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+   (type == MIPI_DSI_DCS_READ))
+
 struct phy;
 
 struct mtk_dsi {
@@ -497,12 +521,12 @@ static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 
irq_bit)
dsi->irq_data |= irq_bit;
 }
 
-static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 
irq_bit)
+static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 {
dsi->irq_data &= ~irq_bit;
 }
 
-static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 
irq_flag,
+static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 unsigned int timeout)
 {
s32 ret = 0;
@@ -814,9 +838,149 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
return 0;
 }
 
+static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
+{
+   u32 timeout_ms = 50; /* total 1s ~ 2s timeout */
+
+   while (timeout_ms--) {
+   if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
+   break;
+
+   usleep_range(2, 4);
+   }
+
+   if (timeout_ms == 0) {
+   DRM_WARN("polling dsi wait not busy timeout!\n");
+
+   mtk_dsi_enable(dsi);
+   mtk_dsi_reset_engine(dsi);
+   }
+}
+
+static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
+{
+   switch (type) {
+   case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+   case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+   return 1;
+   case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+   case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+   return 2;
+   case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+   case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+   return read_data[1] + read_data[2] * 16;
+   case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+   DRM_INFO("type is 0x02, try again\n");
+   break;
+   default:
+   DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
+   break;
+   }
+
+   return 0;
+}
+
+static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
+{
+   const char *tx_buf = msg->tx_buf;
+   u8 config, cmdq_size, cmdq_off, type = msg->type;
+   u32 reg_val, cmdq_mask, i;
+
+   if (MTK_DSI_HOST_IS_READ(type))
+   config = BTA;
+   else
+   config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+   if (msg->tx_len > 2) {
+   cmdq_size = 1 + (msg->tx_len + 3) / 4;
+   cmdq_off = 4;
+   cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+   reg_val = (msg->tx_len << 16) | (type << 8) | config;
+   } else {
+   cmdq_size = 1;
+   cmdq_off = 2;
+   cmdq_mask = CONFIG | DATA_ID;
+   reg_val = (type << 8) | config;
+   }
+
+   for (i = 0; i < msg->tx_len; i++)
+   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+
+   

[PATCH v13 08/12] drm/mediatek: add dsi interrupt control

[YT Shen]

From: shaoming chen 

add dsi interrupt control

Signed-off-by: shaoming chen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 92 ++
 1 file changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d66b98..57955636 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,6 +30,16 @@
 
 #define DSI_START  0x00
 
+#define DSI_INTEN  0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG   BIT(0)
+#define CMD_DONE_INT_FLAG  BIT(1)
+#define TE_RDY_INT_FLAGBIT(2)
+#define VM_DONE_INT_FLAG   BIT(3)
+#define EXT_TE_RDY_INT_FLAGBIT(4)
+#define DSI_BUSY   BIT(31)
+
 #define DSI_CON_CTRL   0x10
 #define DSI_RESET  BIT(0)
 #define DSI_EN BIT(1)
@@ -71,6 +82,9 @@
 
 #define DSI_HSTX_CKL_WC0x64
 
+#define DSI_RACK   0x84
+#define RACK   BIT(0)
+
 #define DSI_PHY_LCCON  0x104
 #define LC_HS_TX_ENBIT(0)
 #define LC_ULPM_EN BIT(1)
@@ -137,6 +151,8 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+   u32 irq_data;
+   wait_queue_head_t irq_wait_queue;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -469,6 +485,64 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
 }
 
+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+   u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
+
+   writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
+{
+   dsi->irq_data |= irq_bit;
+}
+
+static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 
irq_bit)
+{
+   dsi->irq_data &= ~irq_bit;
+}
+
+static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 
irq_flag,
+unsigned int timeout)
+{
+   s32 ret = 0;
+   unsigned long jiffies = msecs_to_jiffies(timeout);
+
+   ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
+  dsi->irq_data & irq_flag,
+  jiffies);
+   if (ret == 0) {
+   DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
+
+   mtk_dsi_enable(dsi);
+   mtk_dsi_reset_engine(dsi);
+   }
+
+   return ret;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+   struct mtk_dsi *dsi = dev_id;
+   u32 status, tmp;
+   u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
+
+   status = readl(dsi->regs + DSI_INTSTA) & flag;
+
+   if (status) {
+   do {
+   mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+   tmp = readl(dsi->regs + DSI_INTSTA);
+   } while (tmp & DSI_BUSY);
+
+   mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
+   mtk_dsi_irq_data_set(dsi, status);
+   wake_up_interruptible(>irq_wait_queue);
+   }
+
+   return IRQ_HANDLED;
+}
+
 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 {
if (WARN_ON(dsi->refcount == 0))
@@ -517,6 +591,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 
mtk_dsi_ps_control_vact(dsi);
mtk_dsi_config_vdo_timing(dsi);
+   mtk_dsi_set_interrupt_enable(dsi);
 
mtk_dsi_set_mode(dsi);
mtk_dsi_clk_hs_mode(dsi, 1);
@@ -800,6 +875,7 @@ static int mtk_dsi_probe(struct platform_device *pdev)
struct device *dev = >dev;
struct device_node *remote_node, *endpoint;
struct resource *regs;
+   int irq_num;
int comp_id;
int ret;
 
@@ -876,6 +952,22 @@ static int mtk_dsi_probe(struct platform_device *pdev)
return ret;
}
 
+   irq_num = platform_get_irq(pdev, 0);
+   if (irq_num < 0) {
+   dev_err(>dev, "failed to request dsi irq resource\n");
+   return -EPROBE_DEFER;
+   }
+
+   irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
+   ret = devm_request_irq(>dev, irq_num, mtk_dsi_irq,
+  IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
+   if (ret) {
+   dev_err(>dev, "failed to request mediatek dsi irq\n");
+   return -EPROBE_DEFER;
+   }
+
+   init_waitqueue_head(>irq_wait_queue);
+
platform_set_drvdata(pdev, dsi);
 
return component_add(>dev, _dsi_component_ops);
-- 
1.9.1

[PATCH v13 09/12] drm/mediatek: add dsi transfer function

[YT Shen]

From: shaoming chen 

add dsi read/write commands for transfer function

Signed-off-by: shaoming chen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 168 -
 1 file changed, 166 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 57955636..2e2cc3a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mtk_drm_ddp_comp.h"
@@ -80,8 +81,16 @@
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
 
+#define DSI_CMDQ_SIZE  0x60
+#define CMDQ_SIZE  0x3f
+
 #define DSI_HSTX_CKL_WC0x64
 
+#define DSI_RX_DATA0   0x74
+#define DSI_RX_DATA1   0x78
+#define DSI_RX_DATA2   0x7c
+#define DSI_RX_DATA3   0x80
+
 #define DSI_RACK   0x84
 #define RACK   BIT(0)
 
@@ -117,6 +126,15 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)
 
+#define DSI_CMDQ0  0x180
+#define CONFIG (0xff << 0)
+#define SHORT_PACKET   0
+#define LONG_PACKET2
+#define BTABIT(2)
+#define DATA_ID(0xff << 8)
+#define DATA_0 (0xff << 16)
+#define DATA_1 (0xff << 24)
+
 #define T_LPX  5
 #define T_HS_PREP  6
 #define T_HS_TRAIL 8
@@ -125,6 +143,12 @@
 
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
+#define MTK_DSI_HOST_IS_READ(type) \
+   ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+   (type == MIPI_DSI_DCS_READ))
+
 struct phy;
 
 struct mtk_dsi {
@@ -497,12 +521,12 @@ static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 
irq_bit)
dsi->irq_data |= irq_bit;
 }
 
-static __maybe_unused void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 
irq_bit)
+static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 {
dsi->irq_data &= ~irq_bit;
 }
 
-static __maybe_unused s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 
irq_flag,
+static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 unsigned int timeout)
 {
s32 ret = 0;
@@ -814,9 +838,149 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
return 0;
 }
 
+static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
+{
+   u32 timeout_ms = 50; /* total 1s ~ 2s timeout */
+
+   while (timeout_ms--) {
+   if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
+   break;
+
+   usleep_range(2, 4);
+   }
+
+   if (timeout_ms == 0) {
+   DRM_WARN("polling dsi wait not busy timeout!\n");
+
+   mtk_dsi_enable(dsi);
+   mtk_dsi_reset_engine(dsi);
+   }
+}
+
+static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
+{
+   switch (type) {
+   case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+   case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+   return 1;
+   case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+   case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+   return 2;
+   case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+   case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+   return read_data[1] + read_data[2] * 16;
+   case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+   DRM_INFO("type is 0x02, try again\n");
+   break;
+   default:
+   DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
+   break;
+   }
+
+   return 0;
+}
+
+static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
+{
+   const char *tx_buf = msg->tx_buf;
+   u8 config, cmdq_size, cmdq_off, type = msg->type;
+   u32 reg_val, cmdq_mask, i;
+
+   if (MTK_DSI_HOST_IS_READ(type))
+   config = BTA;
+   else
+   config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
+
+   if (msg->tx_len > 2) {
+   cmdq_size = 1 + (msg->tx_len + 3) / 4;
+   cmdq_off = 4;
+   cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
+   reg_val = (msg->tx_len << 16) | (type << 8) | config;
+   } else {
+   cmdq_size = 1;
+   cmdq_off = 2;
+   cmdq_mask = CONFIG | DATA_ID;
+   reg_val = (type << 8) | config;
+   }
+
+   for (i = 0; i < msg->tx_len; i++)
+   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+
+   mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+   mtk_dsi_mask(dsi, 

[PATCH v13 00/12] MT2701 DRM support

[YT Shen]

This is MT2701 DRM support PATCH v13, based on 4.11-rc1.
We add DSI interrupt control, transfer function for MIPI DSI panel support.
Most codes are the same, except some register changed.

For example:
 - DISP_OVL address offset changed, color format definition changed.
 - DISP_RDMA fifo size changed.
 - DISP_COLOR offset changed.
 - MIPI_TX setting changed.

We add a new component DDP_COMPONENT_BLS, and the connections are updated.
OVL -> RDMA -> COLOR -> BLS -> DSI
RDMA -> DPI
And we have shadow register support in MT2701.

Changes since v12:
- Fix DSI enable flow we changed at v12

Changes since v11:
- Update mtk_dsi_poweron() and mtk_output_dsi_enable() to symmetric flow

Changes since v10:
- Add binding descriptions for newly added bindings
- Remove color data pointer from generic mtk_ddp_comp
- Remove "drm/mediatek: add mipi_tx data rate check" from the patch series
- Remove "drm/mediatek: add dsi ulp mode control" from the patch series
- Update descriptions for "drm/mediatek: add non-continuous clock mode and EOT 
packet control"
- Fix DSI disable flow

Changes since v9:
- Split DSI patches into smaller parts
- Use a real linux errno for return value
- Add error handling in mtk_output_dsi_enable()
- Remove unused changes and redundant delays
- Add helpers and macros for configuration
- Combine "drm/mediatek: rename macros, add chip prefix" and "drm/mediatek: add 
*driver_data for different hardware setting"

Changes since v8:
- enable 3 DSI interrupts only
- move mtk_dsi_wait_for_irq_done() to the patch of irq control
- use the name BLS in DRM driver part
- move BLS declaration to a separate patch
- update mtk_dsi_switch_to_cmd_mode()
- update mtk_output_dsi_enable() and mtk_output_dsi_disable()

Changes since v7:
- Remove redundant codes
- Move the definition of DDP_COMPONENT_BLS to patch of "drm/mediatek: update 
display module connections"
- Move _dsi_irq_wait_queue into platform driver data
- Move mtk_dsi_irq_data_clear() to patch of "drm/mediatek: add dsi interrupt 
control"
- Add more descriptions in the commit messages

Changes since v6:
- Change data type of irq_data to u32
- Rewrite mtk_dsi_host_transfer() for simplify
- Move some MIPI_TX config to patch of "drm/mediatek: add *driver_data for 
different hardware settings".
- Remove device tree from this patch series

Changes since v5:
- Remove DPI device tree and compatible string
- Use one wait queue to handle interrupt status
- Update the interrupt check flow and DSI_INT_ALL_BITS
- Use same function for host read/write command
- various fixes

Changes since v4:
- Add messages when timeout in mtk_disp_mutex_acquire()
- Add descriptions for DISP_REG_MUTEX registers
- Move connection settings for display modules to a separate patch
- Remove 'mt2701-disp-wdma' because it is unused
- Move cleaning up and renaming to a separate patch
- Use wait_event_interruptible_timeout() to replace polling
- Remove irq_num from mtk_dsi structure
- Remove redundant and debug codes

Changes since v3:
- Add DSI support for MIPI DSI panels
- Update BLS binding to PWM nodes
- Remove ufoe device nodes
- Remove redundant parentheses
- Remove global variable initialization

Changes since v2:
- Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
- Update mt2701_mtk_ddp_ext components
- Changed to prefix naming
- Reorder the patch series
- Use of_device_get_match_data() to get driver private data
- Use iopoll macros to implement mtk_disp_mutex_acquire()
- Removed empty device tree nodes

Changes since v1:
- Removed BLS bindings and codes, which belong to pwm driver
- Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
- Split patch into smaller parts
- Added const keyword to constant structure
- Removed codes for special memory align

Thanks,
yt.shen

YT Shen (10):
  dt-bindings: display: mediatek: update supported chips
  drm/mediatek: add helpers for coverting from the generic components
  drm/mediatek: add *driver_data for different hardware settings
  drm/mediatek: add shadow register support
  drm/mediatek: add BLS component
  drm/mediatek: update display module connections
  drm/mediatek: cleaning up and refine
  drm/mediatek: add non-continuous clock mode and EOT packet control
  drm/mediatek: update DSI sub driver flow for sending commands to panel
  drm/mediatek: add support for Mediatek SoC MT2701

shaoming chen (2):
  drm/mediatek: add dsi interrupt control
  drm/mediatek: add dsi transfer function

 .../bindings/display/mediatek/mediatek,disp.txt|   2 +
 .../bindings/display/mediatek/mediatek,dsi.txt |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c|  64 ++-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c   |  39 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c|  75 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 138 +++--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_c

[PATCH v13 00/12] MT2701 DRM support

[YT Shen]

This is MT2701 DRM support PATCH v13, based on 4.11-rc1.
We add DSI interrupt control, transfer function for MIPI DSI panel support.
Most codes are the same, except some register changed.

For example:
 - DISP_OVL address offset changed, color format definition changed.
 - DISP_RDMA fifo size changed.
 - DISP_COLOR offset changed.
 - MIPI_TX setting changed.

We add a new component DDP_COMPONENT_BLS, and the connections are updated.
OVL -> RDMA -> COLOR -> BLS -> DSI
RDMA -> DPI
And we have shadow register support in MT2701.

Changes since v12:
- Fix DSI enable flow we changed at v12

Changes since v11:
- Update mtk_dsi_poweron() and mtk_output_dsi_enable() to symmetric flow

Changes since v10:
- Add binding descriptions for newly added bindings
- Remove color data pointer from generic mtk_ddp_comp
- Remove "drm/mediatek: add mipi_tx data rate check" from the patch series
- Remove "drm/mediatek: add dsi ulp mode control" from the patch series
- Update descriptions for "drm/mediatek: add non-continuous clock mode and EOT 
packet control"
- Fix DSI disable flow

Changes since v9:
- Split DSI patches into smaller parts
- Use a real linux errno for return value
- Add error handling in mtk_output_dsi_enable()
- Remove unused changes and redundant delays
- Add helpers and macros for configuration
- Combine "drm/mediatek: rename macros, add chip prefix" and "drm/mediatek: add 
*driver_data for different hardware setting"

Changes since v8:
- enable 3 DSI interrupts only
- move mtk_dsi_wait_for_irq_done() to the patch of irq control
- use the name BLS in DRM driver part
- move BLS declaration to a separate patch
- update mtk_dsi_switch_to_cmd_mode()
- update mtk_output_dsi_enable() and mtk_output_dsi_disable()

Changes since v7:
- Remove redundant codes
- Move the definition of DDP_COMPONENT_BLS to patch of "drm/mediatek: update 
display module connections"
- Move _dsi_irq_wait_queue into platform driver data
- Move mtk_dsi_irq_data_clear() to patch of "drm/mediatek: add dsi interrupt 
control"
- Add more descriptions in the commit messages

Changes since v6:
- Change data type of irq_data to u32
- Rewrite mtk_dsi_host_transfer() for simplify
- Move some MIPI_TX config to patch of "drm/mediatek: add *driver_data for 
different hardware settings".
- Remove device tree from this patch series

Changes since v5:
- Remove DPI device tree and compatible string
- Use one wait queue to handle interrupt status
- Update the interrupt check flow and DSI_INT_ALL_BITS
- Use same function for host read/write command
- various fixes

Changes since v4:
- Add messages when timeout in mtk_disp_mutex_acquire()
- Add descriptions for DISP_REG_MUTEX registers
- Move connection settings for display modules to a separate patch
- Remove 'mt2701-disp-wdma' because it is unused
- Move cleaning up and renaming to a separate patch
- Use wait_event_interruptible_timeout() to replace polling
- Remove irq_num from mtk_dsi structure
- Remove redundant and debug codes

Changes since v3:
- Add DSI support for MIPI DSI panels
- Update BLS binding to PWM nodes
- Remove ufoe device nodes
- Remove redundant parentheses
- Remove global variable initialization

Changes since v2:
- Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
- Update mt2701_mtk_ddp_ext components
- Changed to prefix naming
- Reorder the patch series
- Use of_device_get_match_data() to get driver private data
- Use iopoll macros to implement mtk_disp_mutex_acquire()
- Removed empty device tree nodes

Changes since v1:
- Removed BLS bindings and codes, which belong to pwm driver
- Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
- Split patch into smaller parts
- Added const keyword to constant structure
- Removed codes for special memory align

Thanks,
yt.shen

YT Shen (10):
  dt-bindings: display: mediatek: update supported chips
  drm/mediatek: add helpers for coverting from the generic components
  drm/mediatek: add *driver_data for different hardware settings
  drm/mediatek: add shadow register support
  drm/mediatek: add BLS component
  drm/mediatek: update display module connections
  drm/mediatek: cleaning up and refine
  drm/mediatek: add non-continuous clock mode and EOT packet control
  drm/mediatek: update DSI sub driver flow for sending commands to panel
  drm/mediatek: add support for Mediatek SoC MT2701

shaoming chen (2):
  drm/mediatek: add dsi interrupt control
  drm/mediatek: add dsi transfer function

 .../bindings/display/mediatek/mediatek,disp.txt|   2 +
 .../bindings/display/mediatek/mediatek,dsi.txt |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c|  64 ++-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c   |  39 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c|  75 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 138 +++--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_c

[PATCH v13 06/12] drm/mediatek: update display module connections

[YT Shen]

update connections for OVL, RDMA, BLS, DSI

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index b77d456..a9b209c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -32,6 +32,10 @@
 #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
 #define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
 
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+
 #define DISP_REG_MUTEX_EN(n)   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)  (0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)  (0x28 + 0x20 * (n))
@@ -71,6 +75,10 @@
 #define DPI0_SEL_IN_RDMA1  0x1
 #define COLOR1_SEL_IN_OVL1 0x1
 
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define DSI_SEL_IN_BLS 0x0
+
 struct mtk_disp_mutex {
int id;
bool claimed;
@@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id 
cur,
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
+   } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+   value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
@@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
+   } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+   *addr = DISP_REG_CONFIG_DSI_SEL;
+   value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
@@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id 
cur,
return value;
 }
 
+static void mtk_ddp_sout_sel(void __iomem *config_regs,
+enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
+   writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+  config_regs + DISP_REG_CONFIG_OUT_SEL);
+}
+
 void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
  enum mtk_ddp_comp_id cur,
  enum mtk_ddp_comp_id next)
@@ -167,6 +190,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
writel_relaxed(reg, config_regs + addr);
}
 
+   mtk_ddp_sout_sel(config_regs, cur, next);
+
value = mtk_ddp_sel_in(cur, next, );
if (value) {
reg = readl_relaxed(config_regs + addr) | value;
-- 
1.9.1

[PATCH v13 07/12] drm/mediatek: cleaning up and refine

[YT Shen]

cleaning up unused define and refine function name and variable

Signed-off-by: shaoming chen <shaoming.c...@mediatek.com>
Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 73 --
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c |  8 ++--
 2 files changed, 39 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index dd71cbb..5d66b98 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -27,9 +27,6 @@
 
 #include "mtk_drm_ddp_comp.h"
 
-#define DSI_VIDEO_FIFO_DEPTH   (1920 / 4)
-#define DSI_HOST_FIFO_DEPTH64
-
 #define DSI_START  0x00
 
 #define DSI_CON_CTRL   0x10
@@ -46,7 +43,7 @@
 #define MIX_MODE   BIT(17)
 
 #define DSI_TXRX_CTRL  0x18
-#define VC_NUM (2 << 0)
+#define VC_NUM BIT(1)
 #define LANE_NUM   (0xf << 2)
 #define DIS_EOTBIT(6)
 #define NULL_ENBIT(7)
@@ -164,7 +161,7 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, 
u32 mask, u32 data)
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 }
 
-static void dsi_phy_timconfig(struct mtk_dsi *dsi)
+static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
@@ -196,7 +193,7 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 }
 
-static void mtk_dsi_reset(struct mtk_dsi *dsi)
+static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
@@ -267,8 +264,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
-   mtk_dsi_reset(dsi);
-   dsi_phy_timconfig(dsi);
+   mtk_dsi_reset_engine(dsi);
+   mtk_dsi_phy_timconfig(dsi);
 
return 0;
 
@@ -281,33 +278,33 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
return ret;
 }
 
-static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 }
 
-static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 }
 
-static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 }
 
-static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 }
 
-static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
+static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 {
u32 tmp_reg1;
 
@@ -315,15 +312,15 @@ static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 }
 
-static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
+static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 {
-   if (enter && !dsi_clk_hs_state(dsi))
+   if (enter && !mtk_dsi_clk_hs_state(dsi))
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
-   else if (!enter && dsi_clk_hs_state(dsi))
+   else if (!enter && mtk_dsi_clk_hs_state(dsi))
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 }
 
-static void dsi_set_mode(struct mtk_dsi *dsi)
+static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 {
u32 vid_mode = CMD_MODE;
 
@@ -338,7 +335,7 @@ static void dsi_set_mode(struct mtk_dsi *dsi)
writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 }
 
-static void dsi_ps_control_vact(struct mtk_dsi *dsi)
+static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 {
struct videomode *vm = >vm;
u32 dsi_buf_bpp, ps_wc;
@@ -372,7 +369,7 @@ static void dsi_ps_control_vact(struct mtk_dsi *dsi)
writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 }
 
-static void dsi_rxtx_control(struct mtk_dsi *dsi)
+static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 {
u32 tmp_reg;
 
@@ -397,9 +394,9 @@ static void dsi_rxtx_control(struct mtk_dsi *dsi)
writel(tmp_reg

[PATCH v13 06/12] drm/mediatek: update display module connections

[YT Shen]

update connections for OVL, RDMA, BLS, DSI

Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index b77d456..a9b209c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -32,6 +32,10 @@
 #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
 #define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
 
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+
 #define DISP_REG_MUTEX_EN(n)   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)  (0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)  (0x28 + 0x20 * (n))
@@ -71,6 +75,10 @@
 #define DPI0_SEL_IN_RDMA1  0x1
 #define COLOR1_SEL_IN_OVL1 0x1
 
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define DSI_SEL_IN_BLS 0x0
+
 struct mtk_disp_mutex {
int id;
bool claimed;
@@ -111,6 +119,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id 
cur,
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
+   } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+   value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
@@ -148,6 +159,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
+   } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+   *addr = DISP_REG_CONFIG_DSI_SEL;
+   value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
@@ -155,6 +169,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id 
cur,
return value;
 }
 
+static void mtk_ddp_sout_sel(void __iomem *config_regs,
+enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0)
+   writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+  config_regs + DISP_REG_CONFIG_OUT_SEL);
+}
+
 void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
  enum mtk_ddp_comp_id cur,
  enum mtk_ddp_comp_id next)
@@ -167,6 +190,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
writel_relaxed(reg, config_regs + addr);
}
 
+   mtk_ddp_sout_sel(config_regs, cur, next);
+
value = mtk_ddp_sel_in(cur, next, );
if (value) {
reg = readl_relaxed(config_regs + addr) | value;
-- 
1.9.1

[PATCH v13 07/12] drm/mediatek: cleaning up and refine

[YT Shen]

cleaning up unused define and refine function name and variable

Signed-off-by: shaoming chen 
Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 73 --
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c |  8 ++--
 2 files changed, 39 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index dd71cbb..5d66b98 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -27,9 +27,6 @@
 
 #include "mtk_drm_ddp_comp.h"
 
-#define DSI_VIDEO_FIFO_DEPTH   (1920 / 4)
-#define DSI_HOST_FIFO_DEPTH64
-
 #define DSI_START  0x00
 
 #define DSI_CON_CTRL   0x10
@@ -46,7 +43,7 @@
 #define MIX_MODE   BIT(17)
 
 #define DSI_TXRX_CTRL  0x18
-#define VC_NUM (2 << 0)
+#define VC_NUM BIT(1)
 #define LANE_NUM   (0xf << 2)
 #define DIS_EOTBIT(6)
 #define NULL_ENBIT(7)
@@ -164,7 +161,7 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, 
u32 mask, u32 data)
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 }
 
-static void dsi_phy_timconfig(struct mtk_dsi *dsi)
+static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
@@ -196,7 +193,7 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 }
 
-static void mtk_dsi_reset(struct mtk_dsi *dsi)
+static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
@@ -267,8 +264,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
-   mtk_dsi_reset(dsi);
-   dsi_phy_timconfig(dsi);
+   mtk_dsi_reset_engine(dsi);
+   mtk_dsi_phy_timconfig(dsi);
 
return 0;
 
@@ -281,33 +278,33 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
return ret;
 }
 
-static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 }
 
-static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 }
 
-static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 }
 
-static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 }
 
-static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
+static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 {
u32 tmp_reg1;
 
@@ -315,15 +312,15 @@ static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 }
 
-static void dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
+static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 {
-   if (enter && !dsi_clk_hs_state(dsi))
+   if (enter && !mtk_dsi_clk_hs_state(dsi))
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
-   else if (!enter && dsi_clk_hs_state(dsi))
+   else if (!enter && mtk_dsi_clk_hs_state(dsi))
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 }
 
-static void dsi_set_mode(struct mtk_dsi *dsi)
+static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 {
u32 vid_mode = CMD_MODE;
 
@@ -338,7 +335,7 @@ static void dsi_set_mode(struct mtk_dsi *dsi)
writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 }
 
-static void dsi_ps_control_vact(struct mtk_dsi *dsi)
+static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 {
struct videomode *vm = >vm;
u32 dsi_buf_bpp, ps_wc;
@@ -372,7 +369,7 @@ static void dsi_ps_control_vact(struct mtk_dsi *dsi)
writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 }
 
-static void dsi_rxtx_control(struct mtk_dsi *dsi)
+static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 {
u32 tmp_reg;
 
@@ -397,9 +394,9 @@ static void dsi_rxtx_control(struct mtk_dsi *dsi)
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 }
 
-static void dsi_ps_control(struct mtk_dsi *

[PATCH v13 01/12] dt-bindings: display: mediatek: update supported chips

[YT Shen]

Add decriptions about supported chips, including MT2701 & MT8173

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 ++
 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt  | 2 ++
 2 files changed, 4 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 708f566..383183a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -40,6 +40,7 @@ Required properties (all function blocks):
"mediatek,-dpi"- DPI controller, see mediatek,dpi.txt
"mediatek,-disp-mutex" - display mutex
"mediatek,-disp-od"- overdrive
+  the supported chips are mt2701 and mt8173.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except 
for
   merge and split function blocks).
@@ -54,6 +55,7 @@ Required properties (DMA function blocks):
"mediatek,-disp-ovl"
"mediatek,-disp-rdma"
"mediatek,-disp-wdma"
+  the supported chips are mt2701 and mt8173.
 - larb: Should contain a phandle pointing to the local arbiter device as 
defined
   in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
 - iommus: Should point to the respective IOMMU block with master port as
diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index 2b1585a..fadf327 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,6 +7,7 @@ channel output.
 
 Required properties:
 - compatible: "mediatek,-dsi"
+  the supported chips are mt2701 and mt8173.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks
@@ -25,6 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,-mipi-tx"
+  the supported chips are mt2701 and mt8173.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder
-- 
1.9.1

[PATCH v13 02/12] drm/mediatek: add helpers for coverting from the generic components

[YT Shen]

define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl'
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma'

Signed-off-by: YT Shen <yt.s...@mediatek.com>
Acked-by: CK Hu <ck...@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c  | 15 +--
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +--
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index c703102..ce2759f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -57,6 +57,11 @@ struct mtk_disp_ovl {
struct drm_crtc *crtc;
 };
 
+static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_ovl, ddp_comp);
+}
+
 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
 {
struct mtk_disp_ovl *priv = dev_id;
@@ -76,20 +81,18 @@ static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void 
*dev_id)
 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
  struct drm_crtc *crtc)
 {
-   struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
-ddp_comp);
+   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
 
-   priv->crtc = crtc;
+   ovl->crtc = crtc;
writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
 }
 
 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
 {
-   struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
-ddp_comp);
+   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
 
-   priv->crtc = NULL;
+   ovl->crtc = NULL;
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
 }
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0df05f9..21eff6f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -49,6 +49,11 @@ struct mtk_disp_rdma {
struct drm_crtc *crtc;
 };
 
+static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_rdma, ddp_comp);
+}
+
 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
 {
struct mtk_disp_rdma *priv = dev_id;
@@ -77,20 +82,18 @@ static void rdma_update_bits(struct mtk_ddp_comp *comp, 
unsigned int reg,
 static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
   struct drm_crtc *crtc)
 {
-   struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
- ddp_comp);
+   struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
 
-   priv->crtc = crtc;
+   rdma->crtc = crtc;
rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
 RDMA_FRAME_END_INT);
 }
 
 static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
 {
-   struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
- ddp_comp);
+   struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
 
-   priv->crtc = NULL;
+   rdma->crtc = NULL;
rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
 }
 
-- 
1.9.1

[PATCH v13 02/12] drm/mediatek: add helpers for coverting from the generic components

[YT Shen]

define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl'
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma'

Signed-off-by: YT Shen 
Acked-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c  | 15 +--
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 15 +--
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index c703102..ce2759f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -57,6 +57,11 @@ struct mtk_disp_ovl {
struct drm_crtc *crtc;
 };
 
+static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_ovl, ddp_comp);
+}
+
 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
 {
struct mtk_disp_ovl *priv = dev_id;
@@ -76,20 +81,18 @@ static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void 
*dev_id)
 static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
  struct drm_crtc *crtc)
 {
-   struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
-ddp_comp);
+   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
 
-   priv->crtc = crtc;
+   ovl->crtc = crtc;
writel(0x0, comp->regs + DISP_REG_OVL_INTSTA);
writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
 }
 
 static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
 {
-   struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
-ddp_comp);
+   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
 
-   priv->crtc = NULL;
+   ovl->crtc = NULL;
writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
 }
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0df05f9..21eff6f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -49,6 +49,11 @@ struct mtk_disp_rdma {
struct drm_crtc *crtc;
 };
 
+static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_rdma, ddp_comp);
+}
+
 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
 {
struct mtk_disp_rdma *priv = dev_id;
@@ -77,20 +82,18 @@ static void rdma_update_bits(struct mtk_ddp_comp *comp, 
unsigned int reg,
 static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
   struct drm_crtc *crtc)
 {
-   struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
- ddp_comp);
+   struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
 
-   priv->crtc = crtc;
+   rdma->crtc = crtc;
rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
 RDMA_FRAME_END_INT);
 }
 
 static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
 {
-   struct mtk_disp_rdma *priv = container_of(comp, struct mtk_disp_rdma,
- ddp_comp);
+   struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
 
-   priv->crtc = NULL;
+   rdma->crtc = NULL;
rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
 }
 
-- 
1.9.1