> From: Peng Fan <peng....@nxp.com>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Configure PMPROT to let ARM core could run into HSRUN mode.
> In LDO-enabled mode, HSRUN mode is not allowed, so add a check before
> configure PMPROT.
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> arch/arm/mach-imx/pm-imx7ulp.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/mach-imx/pm-imx7ulp.c
> b/arch/arm/mach-imx/pm-imx7ulp.c index 2e756d8191fa..393faf1e8382
> 100644
> --- a/arch/arm/mach-imx/pm-imx7ulp.c
> +++ b/arch/arm/mach-imx/pm-imx7ulp.c
> @@ -11,6 +11,10 @@
>
> #include "common.h"
>
> +#define PMC0_CTRL 0x28
> +#define BM_CTRL_LDOEN BIT(31)
> +
> +#define SMC_PMPROT 0x8
> #define SMC_PMCTRL 0x10
> #define BP_PMCTRL_PSTOPO 16
> #define PSTOPO_PSTOP3 0x3
> @@ -25,7 +29,10 @@
> #define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
> #define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
>
> +#define BM_PMPROT_AHSRUN BIT(7)
> +
> static void __iomem *smc1_base;
> +static void __iomem *pmc0_base;
>
> int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) { @@ -65,5 +72,13
> @@ void __init imx7ulp_pm_init(void)
> of_node_put(np);
> WARN_ON(!smc1_base);
>
> + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0");
> + pmc0_base = of_iomap(np, 0);
> + WARN_ON(!pmc0_base);
> + of_node_put(np);
> +
> + if (!(readl_relaxed(pmc0_base + PMC0_CTRL) & BM_CTRL_LDOEN))
> + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT);
When will HSRUN mode be enabled? E.g. RUNM=HSRUN
It seems RUNM will be cleared in the following imx7ulp_set_lpm().
Regards
Aisheng
> +
> imx7ulp_set_lpm(ULP_PM_RUN);
> }
> --
> 2.28.0
