[Mesa-dev] [PATCH 12/18] radeon/vce: make firmware check compatible with new firmware
From: Leo Liu leo@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_vce.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index d1495a2..b8b35b3 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -428,7 +428,7 @@ error:
*/
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
{
- return rscreen-info.vce_fw_version == ((40 24) | (2 16) | (2
8));
+ return rscreen-info.vce_fw_version = ((40 24) | (2 16) | (2
8));
}
/**
--
2.1.0
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[Mesa-dev] [PATCH 14/18] radeon/video: add 4K support for decode/encode parameters
From: Leo Liu leo@amd.com Signed-off-by: Leo Liu leo@amd.com Reviewed-by: Christian König christian.koe...@amd.com Acked-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/radeon/radeon_video.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index 826e076..65949fb 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -214,9 +214,9 @@ int rvid_get_video_param(struct pipe_screen *screen, case PIPE_VIDEO_CAP_NPOT_TEXTURES: return 1; case PIPE_VIDEO_CAP_MAX_WIDTH: - return 2048; + return (rscreen-family CHIP_TONGA) ? 2048 : 4096; case PIPE_VIDEO_CAP_MAX_HEIGHT: - return 1152; + return (rscreen-family CHIP_TONGA) ? 1152 : 2304; case PIPE_VIDEO_CAP_PREFERED_FORMAT: return PIPE_FORMAT_NV12; case PIPE_VIDEO_CAP_PREFERS_INTERLACED: @@ -268,9 +268,9 @@ int rvid_get_video_param(struct pipe_screen *screen, case PIPE_VIDEO_CAP_NPOT_TEXTURES: return 1; case PIPE_VIDEO_CAP_MAX_WIDTH: - return 2048; + return (rscreen-family CHIP_TONGA) ? 2048 : 4096; case PIPE_VIDEO_CAP_MAX_HEIGHT: - return 1152; + return (rscreen-family CHIP_TONGA) ? 1152 : 2304; case PIPE_VIDEO_CAP_PREFERED_FORMAT: return PIPE_FORMAT_NV12; case PIPE_VIDEO_CAP_PREFERS_INTERLACED: -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 13/18] radeon/vce: adapt new firmware interface changes
From: Leo Liu leo@amd.com
v2: make this also compatible with original released firmware
v3: rebase by Marek
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_vce.c| 1 +
src/gallium/drivers/radeon/radeon_vce.h| 1 +
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 13 +++--
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index b8b35b3..d5ae26d 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -353,6 +353,7 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
if (!enc)
return NULL;
+ enc-fw_ver = rscreen-info.vce_fw_version;
if (rscreen-info.drm_major == 3)
enc-use_vm = true;
if ((rscreen-info.drm_major 2) || (rscreen-info.drm_minor = 42))
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 67ba333..7d37320 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -100,6 +100,7 @@ struct rvce_encoder {
struct rvid_buffer cpb;
struct pipe_h264_enc_picture_desc pic;
booluse_vm;
+ unsignedfw_ver;
booluse_vui;
};
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 1e7f278..f1f4cce 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -44,6 +44,8 @@
#include radeon_video.h
#include radeon_vce.h
+#define FW_40_2_2 ((40 24) | (2 16) | (2 8))
+
static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
static struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
@@ -145,6 +147,10 @@ static void rate_control(struct rvce_encoder *enc)
RVCE_CS(0x); // encBPicsDeltaQP
RVCE_CS(0x); // encReferenceBPicsDeltaQP
RVCE_CS(0x); // encRateControlReInitDisable
+ if (enc-fw_ver FW_40_2_2) {
+ RVCE_CS(0x); // encLCVBRInitQPFlag
+ RVCE_CS(0x); // encLCVBRSATDBasedNonlinearBitBudgetFlag
+ }
RVCE_END();
}
@@ -314,7 +320,10 @@ static void encode(struct rvce_encoder *enc)
RVCE_END();
RVCE_BEGIN(0x0301); // encode
- RVCE_CS(0x); // insertHeaders
+ if ((enc-fw_ver FW_40_2_2) (!enc-pic.frame_num))
+ RVCE_CS(0x0011); // insertHeaders
+ else
+ RVCE_CS(0x); // insertHeaders
RVCE_CS(0x); // pictureStructure
RVCE_CS(enc-bs_size); // allowedMaxBitstreamSize
RVCE_CS(0x); // forceRefreshMap
@@ -328,7 +337,7 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(align(enc-luma-npix_y, 16)); // encInputFrameYPitch
RVCE_CS(enc-luma-level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc-chroma-level[0].pitch_bytes); // encInputPicChromaPitch
- RVCE_CS(0x); // encInputPic(Addr|Array)Mode
+ RVCE_CS(0x); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
RVCE_CS(0x); // encInputPicTileConfig
RVCE_CS(enc-pic.picture_type); // encPicType
RVCE_CS(enc-pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); //
encIdrFlag
--
2.1.0
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[Mesa-dev] [PATCH 18/18] radeonsi: add new VI PCI IDs
From: Marek Olšák marek.ol...@amd.com --- include/pci_ids/radeonsi_pci_ids.h | 20 1 file changed, 20 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 571e863..ca81f76 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -155,3 +155,23 @@ CHIPSET(0x67B8, HAWAII_67B8, HAWAII) CHIPSET(0x67B9, HAWAII_67B9, HAWAII) CHIPSET(0x67BA, HAWAII_67BA, HAWAII) CHIPSET(0x67BE, HAWAII_67BE, HAWAII) + +CHIPSET(0x6900, ICELAND_, ICELAND) +CHIPSET(0x6901, ICELAND_, ICELAND) +CHIPSET(0x6902, ICELAND_, ICELAND) +CHIPSET(0x6903, ICELAND_, ICELAND) +CHIPSET(0x6907, ICELAND_, ICELAND) + +CHIPSET(0x6920, TONGA_, TONGA) +CHIPSET(0x6921, TONGA_, TONGA) +CHIPSET(0x6928, TONGA_, TONGA) +CHIPSET(0x692B, TONGA_, TONGA) +CHIPSET(0x692F, TONGA_, TONGA) +CHIPSET(0x6938, TONGA_, TONGA) +CHIPSET(0x6939, TONGA_, TONGA) + +CHIPSET(0x9870, CARRIZO_, CARRIZO) +CHIPSET(0x9874, CARRIZO_, CARRIZO) +CHIPSET(0x9875, CARRIZO_, CARRIZO) +CHIPSET(0x9876, CARRIZO_, CARRIZO) +CHIPSET(0x9877, CARRIZO_, CARRIZO) -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/18] gallium/radeon: add h264 performance HW decoder support
From: Leo Liu leo@amd.com
v2: -make tonga use new h264 performance HW decoder;
-integrate it scaling buffer to msg_fb buffer
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_uvd.c | 63 +
src/gallium/drivers/radeon/radeon_uvd.h | 2 ++
2 files changed, 43 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index ac850a2..b0bfb3b 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -57,6 +57,7 @@
#define FB_BUFFER_OFFSET 0x1000
#define FB_BUFFER_SIZE 2048
+#define IT_SCALING_TABLE_SIZE 224
/* UVD decoder representation */
struct ruvd_decoder {
@@ -65,6 +66,7 @@ struct ruvd_decoder {
ruvd_set_dtbset_dtb;
unsignedstream_handle;
+ unsignedstream_type;
unsignedframe_number;
struct pipe_screen *screen;
@@ -73,9 +75,10 @@ struct ruvd_decoder {
unsignedcur_buffer;
- struct rvid_buffer msg_fb_buffers[NUM_BUFFERS];
+ struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
struct ruvd_msg *msg;
uint32_t*fb;
+ uint8_t *it;
struct rvid_buffer bs_buffers[NUM_BUFFERS];
void* bs_ptr;
@@ -121,14 +124,14 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned
cmd,
set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd 1);
}
-/* map the next available message/feedback buffer */
-static void map_msg_fb_buf(struct ruvd_decoder *dec)
+/* map the next available message/feedback/itscaling buffer */
+static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
{
struct rvid_buffer* buf;
uint8_t *ptr;
/* grab the current message/feedback buffer */
- buf = dec-msg_fb_buffers[dec-cur_buffer];
+ buf = dec-msg_fb_it_buffers[dec-cur_buffer];
/* and map it for CPU access */
ptr = dec-ws-buffer_map(buf-res-cs_buf, dec-cs,
PIPE_TRANSFER_WRITE);
@@ -136,6 +139,8 @@ static void map_msg_fb_buf(struct ruvd_decoder *dec)
/* calc buffer offsets */
dec-msg = (struct ruvd_msg *)ptr;
dec-fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
+ if (dec-stream_type == RUVD_CODEC_H264_PERF)
+ dec-it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + FB_BUFFER_SIZE);
}
/* unmap and send a message command to the VCPU */
@@ -148,12 +153,14 @@ static void send_msg_buf(struct ruvd_decoder *dec)
return;
/* grab the current message buffer */
- buf = dec-msg_fb_buffers[dec-cur_buffer];
+ buf = dec-msg_fb_it_buffers[dec-cur_buffer];
/* unmap the buffer */
dec-ws-buffer_unmap(buf-res-cs_buf);
dec-msg = NULL;
dec-fb = NULL;
+ if (dec-stream_type == RUVD_CODEC_H264_PERF)
+ dec-it = NULL;
/* and send it to the hardware */
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf-res-cs_buf, 0,
@@ -168,11 +175,12 @@ static void next_buffer(struct ruvd_decoder *dec)
}
/* convert the profile into something UVD understands */
-static uint32_t profile2stream_type(enum pipe_video_profile profile)
+static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
{
- switch (u_reduce_video_profile(profile)) {
+ switch (u_reduce_video_profile(dec-base.profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- return RUVD_CODEC_H264;
+ return (family = CHIP_TONGA) ?
+ RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
case PIPE_VIDEO_FORMAT_VC1:
return RUVD_CODEC_VC1;
@@ -565,7 +573,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
assert(decoder);
- map_msg_fb_buf(dec);
+ map_msg_fb_it_buf(dec);
memset(dec-msg, 0, sizeof(*dec-msg));
dec-msg-size = sizeof(*dec-msg);
dec-msg-msg_type = RUVD_MSG_DESTROY;
@@ -577,7 +585,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
dec-ws-cs_destroy(dec-cs);
for (i = 0; i NUM_BUFFERS; ++i) {
- rvid_destroy_buffer(dec-msg_fb_buffers[i]);
+ rvid_destroy_buffer(dec-msg_fb_it_buffers[i]);
rvid_destroy_buffer(dec-bs_buffers[i]);
}
@@ -679,7 +687,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
{
struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder;
struct radeon_winsys_cs_handle *dt;
- struct rvid_buffer *msg_fb_buf, *bs_buf;
+ struct rvid_buffer *msg_fb_it_buf, *bs_buf;
unsigned bs_size;
assert(decoder);
@@ -687,32 +695,37 @@ static void ruvd_end_frame(struct
[Mesa-dev] [PATCH 15/18] radeon/uvd: recalculate dbp buffer size
From: Leo Liu leo@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/drivers/radeon/radeon_uvd.c | 81 -
1 file changed, 59 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index b0bfb3b..38eb3d1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -198,16 +198,16 @@ static uint32_t profile2stream_type(struct ruvd_decoder
*dec, unsigned family)
}
/* calculate size of reference picture buffer */
-static unsigned calc_dpb_size(const struct pipe_video_codec *templ)
+static unsigned calc_dpb_size(struct ruvd_decoder *dec)
{
unsigned width_in_mb, height_in_mb, image_size, dpb_size;
// always align them to MB size for dpb calculation
- unsigned width = align(templ-width, VL_MACROBLOCK_WIDTH);
- unsigned height = align(templ-height, VL_MACROBLOCK_HEIGHT);
+ unsigned width = align(dec-base.width, VL_MACROBLOCK_WIDTH);
+ unsigned height = align(dec-base.height, VL_MACROBLOCK_HEIGHT);
// always one more for currently decoded picture
- unsigned max_references = templ-max_references + 1;
+ unsigned max_references = dec-base.max_references + 1;
// aligned size of a single frame
image_size = width * height;
@@ -218,20 +218,57 @@ static unsigned calc_dpb_size(const struct
pipe_video_codec *templ)
width_in_mb = width / VL_MACROBLOCK_WIDTH;
height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
- switch (u_reduce_video_profile(templ-profile)) {
- case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- // the firmware seems to allways assume a minimum of ref frames
- max_references = MAX2(NUM_H264_REFS, max_references);
-
- // reference picture buffer
- dpb_size = image_size * max_references;
-
- // macroblock context buffer
- dpb_size += width_in_mb * height_in_mb * max_references * 192;
-
- // IT surface buffer
- dpb_size += width_in_mb * height_in_mb * 32;
+ switch (u_reduce_video_profile(dec-base.profile)) {
+ case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
+ if (!dec-use_legacy) {
+ unsigned fs_in_mb = width_in_mb * height_in_mb;
+ unsigned alignment = 64, num_dpb_buffer;
+
+ if (dec-stream_type == RUVD_CODEC_H264_PERF)
+ alignment = 256;
+ switch(dec-base.level) {
+ case 30:
+ num_dpb_buffer = 8100 / fs_in_mb;
+ break;
+ case 31:
+ num_dpb_buffer = 18000 / fs_in_mb;
+ break;
+ case 32:
+ num_dpb_buffer = 20480 / fs_in_mb;
+ break;
+ case 41:
+ num_dpb_buffer = 32768 / fs_in_mb;
+ break;
+ case 42:
+ num_dpb_buffer = 34816 / fs_in_mb;
+ break;
+ case 50:
+ num_dpb_buffer = 110400 / fs_in_mb;
+ break;
+ case 51:
+ num_dpb_buffer = 184320 / fs_in_mb;
+ break;
+ default:
+ num_dpb_buffer = 184320 / fs_in_mb;
+ break;
+ }
+ num_dpb_buffer++;
+ max_references = MAX2(MIN2(NUM_H264_REFS,
num_dpb_buffer), max_references);
+ dpb_size = image_size * max_references;
+ dpb_size += max_references * align(width_in_mb *
height_in_mb * 192, alignment);
+ dpb_size += align(width_in_mb * height_in_mb * 32,
alignment);
+ } else {
+ // the firmware seems to allways assume a minimum of
ref frames
+ max_references = MAX2(NUM_H264_REFS, max_references);
+ // reference picture buffer
+ dpb_size = image_size * max_references;
+ // macroblock context buffer
+ dpb_size += width_in_mb * height_in_mb * max_references
* 192;
+ // IT surface buffer
+ dpb_size += width_in_mb * height_in_mb * 32;
+ }
break;
+ }
case PIPE_VIDEO_FORMAT_VC1:
// the firmware seems to allways assume a minimum of ref frames
@@ -303,10 +340,8 @@ static struct ruvd_h264
[Mesa-dev] [PATCH 17/18] radeon/vce: implement VCE two pipe support
From: Leo Liu leo@amd.com
v2: rebase by Marek
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/drivers/radeon/radeon_vce.c| 5 +
src/gallium/drivers/radeon/radeon_vce.h| 4
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 17 +
3 files changed, 26 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index d5ae26d..79b0909 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -358,6 +358,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
enc-use_vm = true;
if ((rscreen-info.drm_major 2) || (rscreen-info.drm_minor = 42))
enc-use_vui = true;
+ if (rscreen-info.family = CHIP_TONGA)
+ enc-use_2p = true;
enc-base = *templ;
enc-base.context = context;
@@ -397,6 +399,9 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
cpb_size = cpb_size * align(tmp_surf-npix_y, 16);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc-cpb_num;
+ if (enc-use_2p)
+ cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
+ RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
tmp_buf-destroy(tmp_buf);
if (!rvid_create_buffer(enc-screen, enc-cpb, cpb_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR(Can't create CPB buffer.\n);
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 7d37320..4d07204 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -43,6 +43,9 @@
#define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf),
RADEON_USAGE_READWRITE, (domain), (off))
#define RVCE_END() *begin = (enc-cs-buf[enc-cs-cdw] - begin) * 4; }
+#define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5)
+#define RVCE_MAX_AUX_BUFFER_NUM 4
+
struct r600_common_screen;
/* driver dependent callback */
@@ -102,6 +105,7 @@ struct rvce_encoder {
booluse_vm;
unsignedfw_ver;
booluse_vui;
+ booluse_2p;
};
struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index f1f4cce..970d572 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -319,6 +319,23 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc-bs_size); // videoBitstreamRingSize
RVCE_END();
+ if (enc-use_2p) {
+ unsigned aux_offset = enc-cpb.res-buf-size -
+ RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
+ RVCE_BEGIN(0x0502); // auxiliary buffer
+ for (i = 0; i 4; ++i) {
+ RVCE_CS(aux_offset);
+ aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
+ }
+ for (i = 0; i 4; ++i)
+ RVCE_CS(0x);
+ for (i = 0; i 4; ++i)
+ RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE);
+ for (i = 0; i 4; ++i)
+ RVCE_CS(0x);
+ RVCE_END();
+ }
+
RVCE_BEGIN(0x0301); // encode
if ((enc-fw_ver FW_40_2_2) (!enc-pic.frame_num))
RVCE_CS(0x0011); // insertHeaders
--
2.1.0
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Re: [Mesa-dev] [PATCH] vc4: with primconvert, quads follow provoking vertex convention
On Mon, Apr 20, 2015 at 8:30 PM, Eric Anholt e...@anholt.net wrote: Ilia Mirkin imir...@alum.mit.edu writes: Signed-off-by: Ilia Mirkin imir...@alum.mit.edu But we don't have provoking vertex convention support in the first place, so we actually just need to introduce caps to not expose the extension. Ah yeah, sorry, I just assumed that provoking vertex worked for triangles already. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/5] gallium/radeon: print winsys info with R600_DEBUG=info
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 27 +++
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 2b27e0a..c6d7918 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -306,6 +306,7 @@ static const struct debug_named_value
common_debug_options[] = {
{ compute, DBG_COMPUTE, Print compute info },
{ vm, DBG_VM, Print virtual addresses when creating resources },
{ trace_cs, DBG_TRACE_CS, Trace cs and write rlockup_csid.c file
with faulty cs },
+ { info, DBG_INFO, Print driver information },
/* shaders */
{ fs, DBG_FS, Print fetch shaders },
@@ -874,6 +875,32 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
}
}
+ if (rscreen-debug_flags DBG_INFO) {
+ printf(pci_id = 0x%x\n, rscreen-info.pci_id);
+ printf(family = %i\n, rscreen-info.family);
+ printf(chip_class = %i\n, rscreen-info.chip_class);
+ printf(gart_size = %i MB\n, (int)(rscreen-info.gart_size
20));
+ printf(vram_size = %i MB\n, (int)(rscreen-info.vram_size
20));
+ printf(max_sclk = %i\n, rscreen-info.max_sclk);
+ printf(max_compute_units = %i\n,
rscreen-info.max_compute_units);
+ printf(max_se = %i\n, rscreen-info.max_se);
+ printf(max_sh_per_se = %i\n, rscreen-info.max_sh_per_se);
+ printf(drm = %i.%i.%i\n, rscreen-info.drm_major,
+ rscreen-info.drm_minor, rscreen-info.drm_patchlevel);
+ printf(has_uvd = %i\n, rscreen-info.has_uvd);
+ printf(vce_fw_version = %i\n, rscreen-info.vce_fw_version);
+ printf(r600_num_backends = %i\n,
rscreen-info.r600_num_backends);
+ printf(r600_clock_crystal_freq = %i\n,
rscreen-info.r600_clock_crystal_freq);
+ printf(r600_tiling_config = 0x%x\n,
rscreen-info.r600_tiling_config);
+ printf(r600_num_tile_pipes = %i\n,
rscreen-info.r600_num_tile_pipes);
+ printf(r600_max_pipes = %i\n, rscreen-info.r600_max_pipes);
+ printf(r600_virtual_address = %i\n,
rscreen-info.r600_virtual_address);
+ printf(r600_has_dma = %i\n, rscreen-info.r600_has_dma);
+ printf(r600_backend_map = %i\n,
rscreen-info.r600_backend_map);
+ printf(r600_backend_map_valid = %i\n,
rscreen-info.r600_backend_map_valid);
+ printf(si_tile_mode_array_valid = %i\n,
rscreen-info.si_tile_mode_array_valid);
+ printf(cik_macrotile_mode_array_valid = %i\n,
rscreen-info.cik_macrotile_mode_array_valid);
+ }
return true;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index febd2a1..384a9a6 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -84,6 +84,7 @@
#define DBG_SWITCH_ON_EOP (1 15)
#define DBG_FORCE_DMA (1 16)
#define DBG_PRECOMPILE (1 17)
+#define DBG_INFO (1 18)
/* The maximum allowed bit is 20. */
#define R600_MAP_BUFFER_ALIGNMENT 64
--
2.1.0
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[Mesa-dev] [PATCH 4/5] radeonsi: remove deprecated and useless registers
From: Marek Olšák marek.ol...@amd.com --- src/gallium/drivers/radeonsi/si_state.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 4bb6f2b..f24cbbd 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3035,18 +3035,8 @@ void si_init_config(struct si_context *sctx) si_cmd_context_control(pm4); - si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); - si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); - si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); - si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); - si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); - si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); - si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); /* FIXME calculate these values somehow ??? */ si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80); -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/5] winsys/radeon: make radeon_bo_vtbl static
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index e609d68..061c814 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -42,7 +42,7 @@
#include fcntl.h
#include stdio.h
-extern const struct pb_vtbl radeon_bo_vtbl;
+static const struct pb_vtbl radeon_bo_vtbl;
static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
{
@@ -471,7 +471,7 @@ static void radeon_bo_fence(struct pb_buffer *buf,
{
}
-const struct pb_vtbl radeon_bo_vtbl = {
+static const struct pb_vtbl radeon_bo_vtbl = {
radeon_bo_destroy,
NULL, /* never called */
NULL, /* never called */
--
2.1.0
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[Mesa-dev] [PATCH 3/5] radeonsi: remove useless includes
From: Marek Olšák marek.ol...@amd.com --- src/gallium/drivers/radeonsi/si_pipe.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 5dc657c..e68c30e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -30,9 +30,6 @@ #include util/u_memory.h #include vl/vl_decoder.h -#include llvm-c/Target.h -#include llvm-c/TargetMachine.h - /* * pipe_context */ -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/5] radeonsi: set an optimal value for DB_Z_INFO_ZRANGE_PRECISION
From: Marek Olšák marek.ol...@amd.com Required because of a VI hw bug. --- src/gallium/drivers/radeonsi/si_state.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index f24cbbd..dc19d29 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1948,12 +1948,6 @@ static void si_init_depth_surface(struct si_context *sctx, z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1); - /* This is optimal for the clear value of 1.0 and using -* the LESS and LEQUAL test functions. Set this to 0 -* for the opposite case. This can only be changed when -* clearing. */ - z_info |= S_028040_ZRANGE_PRECISION(1); - /* Use all of the htile_buffer for depth, because we don't * use HTILE for stencil because of FAST_STENCIL_DISABLE. */ s_info |= S_028044_TILE_STENCIL_DISABLE(1); @@ -2183,7 +2177,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); radeon_emit(cs, zb-db_depth_info); /* R_02803C_DB_DEPTH_INFO */ - radeon_emit(cs, zb-db_z_info); /* R_028040_DB_Z_INFO */ + radeon_emit(cs, zb-db_z_info | /* R_028040_DB_Z_INFO */ + S_028040_ZRANGE_PRECISION(rtex-depth_clear_value != 0)); radeon_emit(cs, zb-db_stencil_info); /* R_028044_DB_STENCIL_INFO */ radeon_emit(cs, zb-db_depth_base); /* R_028048_DB_Z_READ_BASE */ radeon_emit(cs, zb-db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Initial amdgpu driver release
I'm pleased to announce the initial release of the new amdgpu driver. This is a partial replacement for the radeon driver for newer AMD asics. A number of components are still shared. Here is a comparison of the radeon and amdgpu stacks: 1. radeon stack kernel driver: radeon.ko libdrm: libdrm_radeon mesa: radeon, r200, r300, r600, radeonsi ddx: xf86-video-ati 2. amdgpu stack kernel driver: amdgpu.ko libdrm: libdrm_amdgpu mesa: radeonsi ddx: xf86-video-amdgpu Older asics will continue to be supported by the radeon stack; new asics will be supported by the amdgpu stack. CI (Sea Islands) asics have support in both driver stacks, but this is purely for testing purposes. CI parts are officially supported in the radeon stack. Support for CI on the amdgpu stack is determined by a config option in the kernel. CI support is not enabled by default for amdgpu. Most of our focus has been on Carrizo support, so there are some gaps in the dGPU support for Tonga and Iceland, notably power management. Those gaps will be filled in eventually. Also included in this code base are full register headers for just about every block on the asics. Barring the gaps mentioned above, the driver stack is functionally on par with radeon including: - OpenGL 3.3 support using the radeonsi mesa driver - Video decode support using UVD - Video encode support using VCE The code can be found in the amdgpu branches of the following git trees. xf86-video-amdgpu: http://cgit.freedesktop.org/~agd5f/xf86-video-amdgpu/log/?h=amdgpu libdrm: http://cgit.freedesktop.org/~agd5f/drm/log/?h=amdgpu kernel: http://cgit.freedesktop.org/~agd5f/linux/log/?h=amdgpu mesa: http://cgit.freedesktop.org/~mareko/mesa/log/?h=amdgpu To test the new driver stack you will need to specify a device section in your xorg.conf with the driver set to amdgpu rather than radeon. Please review! Thanks, The AMD Linux Driver Team ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Initial amdgpu driver release
On Mon, Apr 20, 2015 at 6:33 PM, Alex Deucher alexdeuc...@gmail.com wrote: I'm pleased to announce the initial release of the new amdgpu driver. This is a partial replacement for the radeon driver for newer AMD asics. A number of components are still shared. Here is a comparison of the radeon and amdgpu stacks: 1. radeon stack kernel driver: radeon.ko libdrm: libdrm_radeon mesa: radeon, r200, r300, r600, radeonsi ddx: xf86-video-ati 2. amdgpu stack kernel driver: amdgpu.ko libdrm: libdrm_amdgpu mesa: radeonsi ddx: xf86-video-amdgpu Older asics will continue to be supported by the radeon stack; new asics will be supported by the amdgpu stack. CI (Sea Islands) asics have support in both driver stacks, but this is purely for testing purposes. CI parts are officially supported in the radeon stack. Support for CI on the amdgpu stack is determined by a config option in the kernel. CI support is not enabled by default for amdgpu. Most of our focus has been on Carrizo support, so there are some gaps in the dGPU support for Tonga and Iceland, notably power management. Those gaps will be filled in eventually. Also included in this code base are full register headers for just about every block on the asics. Barring the gaps mentioned above, the driver stack is functionally on par with radeon including: - OpenGL 3.3 support using the radeonsi mesa driver - Video decode support using UVD - Video encode support using VCE The code can be found in the amdgpu branches of the following git trees. xf86-video-amdgpu: http://cgit.freedesktop.org/~agd5f/xf86-video-amdgpu/log/?h=amdgpu libdrm: http://cgit.freedesktop.org/~agd5f/drm/log/?h=amdgpu kernel: http://cgit.freedesktop.org/~agd5f/linux/log/?h=amdgpu mesa: http://cgit.freedesktop.org/~mareko/mesa/log/?h=amdgpu I forgot to mention, the latest ucode can be found here: http://people.freedesktop.org/~agd5f/radeon_ucode/ Alex To test the new driver stack you will need to specify a device section in your xorg.conf with the driver set to amdgpu rather than radeon. Please review! Thanks, The AMD Linux Driver Team ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] vc4: with primconvert, quads follow provoking vertex convention
Ilia Mirkin imir...@alum.mit.edu writes: Signed-off-by: Ilia Mirkin imir...@alum.mit.edu But we don't have provoking vertex convention support in the first place, so we actually just need to introduce caps to not expose the extension. signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] clover: compile all sources with c++11
Later we can remove the compat code. --- src/gallium/state_trackers/clover/Makefile.am | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/state_trackers/clover/Makefile.am b/src/gallium/state_trackers/clover/Makefile.am index 62c13fa..54b6fff 100644 --- a/src/gallium/state_trackers/clover/Makefile.am +++ b/src/gallium/state_trackers/clover/Makefile.am @@ -3,6 +3,7 @@ AUTOMAKE_OPTIONS = subdir-objects include Makefile.sources AM_CPPFLAGS = \ + -std=c++11 \ $(GALLIUM_PIPE_LOADER_DEFINES) \ -DPIPE_SEARCH_DIR=\$(libdir)/gallium-pipe\ \ -I$(top_srcdir)/include \ @@ -35,7 +36,6 @@ endif noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la libcltgsi_la_CXXFLAGS = \ - -std=c++0x \ $(VISIBILITY_CXXFLAGS) libcltgsi_la_SOURCES = $(TGSI_SOURCES) @@ -51,7 +51,6 @@ libclllvm_la_CXXFLAGS = \ libclllvm_la_SOURCES = $(LLVM_SOURCES) libclover_la_CXXFLAGS = \ - -std=c++11 \ $(VISIBILITY_CXXFLAGS) libclover_la_LIBADD = \ -- 2.4.0.rc2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] st/vdpau: add h264 decoder level support
From: Leo Liu leo@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/state_trackers/vdpau/decode.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/state_trackers/vdpau/decode.c
b/src/gallium/state_trackers/vdpau/decode.c
index 767d311..0634ba7 100644
--- a/src/gallium/state_trackers/vdpau/decode.c
+++ b/src/gallium/state_trackers/vdpau/decode.c
@@ -118,6 +118,11 @@ vlVdpDecoderCreate(VdpDevice device,
templat.height = height;
templat.max_references = max_references;
+ if (u_reduce_video_profile(templat.profile) ==
+ PIPE_VIDEO_FORMAT_MPEG4_AVC)
+ templat.level = u_get_h264_level(templat.width, templat.height,
+templat.max_references);
+
vldecoder-decoder = pipe-create_video_codec(pipe, templat);
if (!vldecoder-decoder) {
--
2.1.0
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[Mesa-dev] [PATCH 4/6] vl: add level idc in sps
From: Leo Liu leo@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/include/pipe/p_video_state.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/include/pipe/p_video_state.h
b/src/gallium/include/pipe/p_video_state.h
index 6621dbd..3713cd9 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -271,6 +271,7 @@ struct pipe_vc1_picture_desc
struct pipe_h264_sps
{
+ uint8_t level_idc;
uint8_t chroma_format_idc;
uint8_t separate_colour_plane_flag;
uint8_t bit_depth_luma_minus8;
--
2.1.0
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[Mesa-dev] [PATCH 6/6] st/va: add h264 decoder level support
From: Leo Liu leo@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/state_trackers/va/context.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/state_trackers/va/context.c
b/src/gallium/state_trackers/va/context.c
index a7a55f9..0a733b3 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -167,6 +167,11 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID
config_id, int picture_width,
templat.max_references = num_render_targets;
templat.expect_chunked_decode = true;
+ if (u_reduce_video_profile(templat.profile) ==
+ PIPE_VIDEO_FORMAT_MPEG4_AVC)
+ templat.level = u_get_h264_level(templat.width, templat.height,
+templat.max_references);
+
context-decoder = drv-pipe-create_video_codec(drv-pipe, templat);
if (!context-decoder) {
FREE(context);
--
2.1.0
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[Mesa-dev] [PATCH 5/6] st/omx/dec: add h264 decoder level support
From: Leo Liu leo@amd.com
v2: use sps level idc as level to driver
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/state_trackers/omx/vid_dec_h264.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c
b/src/gallium/state_trackers/omx/vid_dec_h264.c
index 7c90dee..18d8803 100644
--- a/src/gallium/state_trackers/omx/vid_dec_h264.c
+++ b/src/gallium/state_trackers/omx/vid_dec_h264.c
@@ -33,6 +33,7 @@
#include pipe/p_video_codec.h
#include util/u_memory.h
+#include util/u_video.h
#include vl/vl_rbsp.h
#include entrypoint.h
@@ -113,10 +114,11 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType
*priv)
templat.profile = priv-profile;
templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
- templat.max_references = 2;
+ templat.max_references = priv-picture.h264.num_ref_frames;
templat.expect_chunked_decode = true;
templat.width = port-sPortParam.format.video.nFrameWidth;
templat.height = port-sPortParam.format.video.nFrameHeight;
+ templat.level = priv-picture.h264.pps-sps-level_idc;
priv-codec = priv-pipe-create_video_codec(priv-pipe, templat);
}
@@ -239,7 +241,7 @@ static struct pipe_h264_sps
*seq_parameter_set_id(vid_dec_PrivateType *priv, str
static void seq_parameter_set(vid_dec_PrivateType *priv, struct vl_rbsp *rbsp)
{
struct pipe_h264_sps *sps;
- unsigned profile_idc;
+ unsigned profile_idc, level_idc;
unsigned i;
/* Sequence parameter set */
@@ -267,7 +269,7 @@ static void seq_parameter_set(vid_dec_PrivateType *priv,
struct vl_rbsp *rbsp)
vl_rbsp_u(rbsp, 2);
/* level_idc */
- vl_rbsp_u(rbsp, 8);
+ level_idc = vl_rbsp_u(rbsp, 8);
sps = seq_parameter_set_id(priv, rbsp);
if (!sps)
@@ -277,6 +279,8 @@ static void seq_parameter_set(vid_dec_PrivateType *priv,
struct vl_rbsp *rbsp)
memset(sps-ScalingList4x4, 16, sizeof(sps-ScalingList4x4));
memset(sps-ScalingList8x8, 16, sizeof(sps-ScalingList8x8));
+ sps-level_idc = level_idc;
+
if (profile_idc == 100 || profile_idc == 110 || profile_idc == 122 ||
profile_idc == 244 ||
profile_idc == 44 || profile_idc == 83 || profile_idc == 86 ||
profile_idc == 118 ||
profile_idc == 128 || profile_idc == 138) {
--
2.1.0
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[Mesa-dev] [PATCH 0/6] Video state tracker patches for VI
These patches were created during UVD and VCE bring-up for VI. I'm sending them in case other people want to review them. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/6] st/omx/dec: separate create_video_codec to different codecs
From: Leo Liu leo@amd.com
v2: get frame size from port info
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/state_trackers/omx/vid_dec.c| 18 --
src/gallium/state_trackers/omx/vid_dec.h| 1 +
src/gallium/state_trackers/omx/vid_dec_h264.c | 15 +++
src/gallium/state_trackers/omx/vid_dec_mpeg12.c | 14 ++
4 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/src/gallium/state_trackers/omx/vid_dec.c
b/src/gallium/state_trackers/omx/vid_dec.c
index 13f4f55..9e7e7ba 100644
--- a/src/gallium/state_trackers/omx/vid_dec.c
+++ b/src/gallium/state_trackers/omx/vid_dec.c
@@ -44,8 +44,6 @@
#include bellagio/omxcore.h
#endif
-#include bellagio/omx_base_video_port.h
-
#include pipe/p_screen.h
#include pipe/p_video_codec.h
#include util/u_memory.h
@@ -364,22 +362,6 @@ static OMX_ERRORTYPE
vid_dec_MessageHandler(OMX_COMPONENTTYPE* comp, internalReq
if (msg-messageType == OMX_CommandStateSet) {
if ((msg-messageParam == OMX_StateIdle ) (priv-state ==
OMX_StateLoaded)) {
-
- struct pipe_video_codec templat = {};
- omx_base_video_PortType *port;
-
- port = (omx_base_video_PortType
*)priv-ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
-
- templat.profile = priv-profile;
- templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
- templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
- templat.width = port-sPortParam.format.video.nFrameWidth;
- templat.height = port-sPortParam.format.video.nFrameHeight;
- templat.max_references = 2;
- templat.expect_chunked_decode = true;
-
- priv-codec = priv-pipe-create_video_codec(priv-pipe, templat);
-
if (priv-profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN)
vid_dec_mpeg12_Init(priv);
else if (priv-profile == PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH)
diff --git a/src/gallium/state_trackers/omx/vid_dec.h
b/src/gallium/state_trackers/omx/vid_dec.h
index 9acf872..1c51f9c 100644
--- a/src/gallium/state_trackers/omx/vid_dec.h
+++ b/src/gallium/state_trackers/omx/vid_dec.h
@@ -44,6 +44,7 @@
#include bellagio/st_static_component_loader.h
#include bellagio/omx_base_filter.h
+#include bellagio/omx_base_video_port.h
#include pipe/p_video_state.h
#include state_tracker/drm_driver.h
diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c
b/src/gallium/state_trackers/omx/vid_dec_h264.c
index e01e873..7c90dee 100644
--- a/src/gallium/state_trackers/omx/vid_dec_h264.c
+++ b/src/gallium/state_trackers/omx/vid_dec_h264.c
@@ -105,6 +105,21 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType
*priv)
priv-picture.h264.num_ref_frames =
priv-picture.h264.pps-sps-max_num_ref_frames;
+ if (!priv-codec) {
+ struct pipe_video_codec templat = {};
+ omx_base_video_PortType *port;
+
+ port = (omx_base_video_PortType
*)priv-ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
+ templat.profile = priv-profile;
+ templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
+ templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
+ templat.max_references = 2;
+ templat.expect_chunked_decode = true;
+ templat.width = port-sPortParam.format.video.nFrameWidth;
+ templat.height = port-sPortParam.format.video.nFrameHeight;
+
+ priv-codec = priv-pipe-create_video_codec(priv-pipe, templat);
+ }
priv-codec-begin_frame(priv-codec, priv-target, priv-picture.base);
priv-frame_started = true;
}
diff --git a/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
b/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
index de4c69a..bef83ec 100644
--- a/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
+++ b/src/gallium/state_trackers/omx/vid_dec_mpeg12.c
@@ -65,6 +65,20 @@ static struct pipe_video_buffer
*vid_dec_mpeg12_Flush(vid_dec_PrivateType *priv)
void vid_dec_mpeg12_Init(vid_dec_PrivateType *priv)
{
+ struct pipe_video_codec templat = {};
+ omx_base_video_PortType *port;
+
+ port = (omx_base_video_PortType
*)priv-ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
+ templat.profile = priv-profile;
+ templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
+ templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
+ templat.max_references = 2;
+ templat.expect_chunked_decode = true;
+ templat.width = port-sPortParam.format.video.nFrameWidth;
+ templat.height = port-sPortParam.format.video.nFrameHeight;
+
+ priv-codec = priv-pipe-create_video_codec(priv-pipe, templat);
+
priv-picture.base.profile = PIPE_VIDEO_PROFILE_MPEG2_MAIN;
priv-picture.mpeg12.intra_matrix = default_intra_matrix;
priv-picture.mpeg12.non_intra_matrix = default_non_intra_matrix;
--
2.1.0
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[Mesa-dev] [PATCH 1/6] gallium/util: get h264 level based on number of max references and resolution
From: Leo Liu leo@amd.com
v2: add commments for limitation of max references numbers,
and what the caculation is based
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
---
src/gallium/auxiliary/util/u_video.h | 36
1 file changed, 36 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_video.h
b/src/gallium/auxiliary/util/u_video.h
index 45b2d6e..b4743d1 100644
--- a/src/gallium/auxiliary/util/u_video.h
+++ b/src/gallium/auxiliary/util/u_video.h
@@ -38,6 +38,7 @@ extern C {
/* u_reduce_video_profile() needs these */
#include pipe/p_compiler.h
#include util/u_debug.h
+#include util/u_math.h
static INLINE enum pipe_video_format
u_reduce_video_profile(enum pipe_video_profile profile)
@@ -146,6 +147,41 @@ u_copy_swap422_packed(void *const *destination_data,
}
}
+static INLINE uint32_t
+u_get_h264_level(uint32_t width, uint32_t height, uint32_t *max_reference)
+{
+ uint32_t max_dpb_mbs;
+
+ width = align(width, 16);
+ height = align(height, 16);
+
+ /* Max references will be used for caculation of number of DPB buffers
+ in the UVD driver, limitation of max references is 16. Some client
+ like mpv application for VA-API, it requires references more than that,
+ so we have to set max of references to 16 here. */
+ *max_reference = MIN2(*max_reference, 16);
+ max_dpb_mbs = (width / 16) * (height / 16) * *max_reference;
+
+ /* The calculation is based on Decoded picture buffering section
+ from http://en.wikipedia.org/wiki/H.264/MPEG-4_AVC */
+ if (max_dpb_mbs = 8100)
+ return 30;
+ else if (max_dpb_mbs = 18000)
+ return 31;
+ else if (max_dpb_mbs = 20480)
+ return 32;
+ else if (max_dpb_mbs = 32768)
+ return 41;
+ else if (max_dpb_mbs = 34816)
+ return 42;
+ else if (max_dpb_mbs = 110400)
+ return 50;
+ else if (max_dpb_mbs = 184320)
+ return 51;
+ else
+ return 52;
+}
+
#ifdef __cplusplus
}
#endif
--
2.1.0
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[Mesa-dev] [PATCH 01/18] winsys/radeon: move radeon_winsys.h up one directory
From: Marek Olšák marek.ol...@amd.com --- .../auxiliary/target-helpers/inline_drm_helper.h | 6 +- src/gallium/drivers/r300/r300_chipset.c| 2 +- src/gallium/drivers/r300/r300_context.h| 1 - src/gallium/drivers/r300/r300_screen.h | 2 +- src/gallium/drivers/radeon/r600_pipe_common.h | 2 +- src/gallium/drivers/radeon/radeon_uvd.c| 1 - src/gallium/drivers/radeon/radeon_uvd.h| 2 +- src/gallium/drivers/radeon/radeon_vce.c| 1 - src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 1 - src/gallium/drivers/radeon/radeon_video.c | 1 - src/gallium/drivers/radeon/radeon_video.h | 2 +- src/gallium/drivers/radeonsi/si_pm4.h | 2 +- src/gallium/targets/pipe-loader/pipe_r300.c| 2 +- src/gallium/targets/pipe-loader/pipe_r600.c| 2 +- src/gallium/targets/pipe-loader/pipe_radeonsi.c| 2 +- src/gallium/winsys/radeon/drm/Makefile.sources | 2 +- src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 2 +- src/gallium/winsys/radeon/drm/radeon_winsys.h | 604 - src/gallium/winsys/radeon/radeon_winsys.h | 604 + 19 files changed, 618 insertions(+), 623 deletions(-) delete mode 100644 src/gallium/winsys/radeon/drm/radeon_winsys.h create mode 100644 src/gallium/winsys/radeon/radeon_winsys.h diff --git a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h index 542ad43..d3c331d 100644 --- a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h +++ b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h @@ -28,19 +28,19 @@ #endif #if GALLIUM_R300 -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include radeon/drm/radeon_drm_public.h #include r300/r300_public.h #endif #if GALLIUM_R600 -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include radeon/drm/radeon_drm_public.h #include r600/r600_public.h #endif #if GALLIUM_RADEONSI -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include radeon/drm/radeon_drm_public.h #include radeonsi/si_public.h #endif diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 7a83611..c1c7ce3 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -22,7 +22,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include r300_chipset.h -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include util/u_debug.h #include util/u_memory.h diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 4d2b153..3873c9a 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -36,7 +36,6 @@ #include r300_defines.h #include r300_screen.h #include compiler/radeon_regalloc.h -#include radeon/drm/radeon_winsys.h struct u_upload_mgr; struct r300_context; diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index f0dd3c6..7bba39b 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -25,7 +25,7 @@ #define R300_SCREEN_H #include r300_chipset.h -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include pipe/p_screen.h #include util/u_slab.h #include os/os_thread.h diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 384a9a6..b7df001 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -34,7 +34,7 @@ #include stdio.h -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include util/u_blitter.h #include util/u_double_list.h diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 9668d7d..4d4b54b 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -45,7 +45,6 @@ #include vl/vl_defines.h #include vl/vl_mpeg12_decoder.h -#include radeon/drm/radeon_winsys.h #include r600_pipe_common.h #include radeon_video.h #include radeon_uvd.h diff --git a/src/gallium/drivers/radeon/radeon_uvd.h b/src/gallium/drivers/radeon/radeon_uvd.h index 462b101..41a6fb4 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.h +++ b/src/gallium/drivers/radeon/radeon_uvd.h @@ -34,7 +34,7 @@ #ifndef RADEON_UVD_H #define RADEON_UVD_H -#include radeon/drm/radeon_winsys.h +#include radeon/radeon_winsys.h #include vl/vl_video_buffer.h /* UVD uses PM4 packet type 0 and 2 */ diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c index 6d34bd3..5f710e6 100644 --- a/src/gallium/drivers/radeon/radeon_vce.c +++ b/src/gallium/drivers/radeon/radeon_vce.c @@ -40,7 +40,6 @@
[Mesa-dev] [PATCH 03/18] winsys/amdgpu: add a new winsys for the new kernel driver
From: Marek Olšák marek.ol...@amd.com --- configure.ac | 5 + src/gallium/Makefile.am | 1 + src/gallium/drivers/r300/Automake.inc | 6 +- src/gallium/drivers/r600/Automake.inc | 6 +- src/gallium/drivers/radeonsi/Automake.inc | 6 +- src/gallium/targets/pipe-loader/Makefile.am | 12 +- src/gallium/winsys/radeon/amdgpu/Android.mk | 40 ++ src/gallium/winsys/radeon/amdgpu/Makefile.am | 12 + src/gallium/winsys/radeon/amdgpu/Makefile.sources | 8 + src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c | 643 ++ src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h | 75 +++ src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c | 578 +++ src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h | 149 + src/gallium/winsys/radeon/amdgpu/amdgpu_public.h | 14 + src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c | 491 + src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h | 80 +++ src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 8 + src/gallium/winsys/radeon/radeon_winsys.h | 4 + 18 files changed, 2129 insertions(+), 9 deletions(-) create mode 100644 src/gallium/winsys/radeon/amdgpu/Android.mk create mode 100644 src/gallium/winsys/radeon/amdgpu/Makefile.am create mode 100644 src/gallium/winsys/radeon/amdgpu/Makefile.sources create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_bo.c create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_bo.h create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_cs.c create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_cs.h create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_public.h create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.c create mode 100644 src/gallium/winsys/radeon/amdgpu/amdgpu_winsys.h diff --git a/configure.ac b/configure.ac index 095e23e..f22975f 100644 --- a/configure.ac +++ b/configure.ac @@ -68,6 +68,7 @@ AC_SUBST([OSMESA_VERSION]) dnl Versions for external dependencies LIBDRM_REQUIRED=2.4.38 LIBDRM_RADEON_REQUIRED=2.4.56 +LIBDRM_AMDGPU_REQUIRED=2.4.60 LIBDRM_INTEL_REQUIRED=2.4.60 LIBDRM_NVVIEUX_REQUIRED=2.4.33 LIBDRM_NOUVEAU_REQUIRED=2.4.33 libdrm = 2.4.41 @@ -2091,6 +2092,7 @@ if test -n $with_gallium_drivers; then xr300) HAVE_GALLIUM_R300=yes PKG_CHECK_MODULES([RADEON], [libdrm_radeon = $LIBDRM_RADEON_REQUIRED]) +PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu = $LIBDRM_AMDGPU_REQUIRED]) gallium_require_drm Gallium R300 gallium_require_drm_loader gallium_require_llvm Gallium R300 @@ -2098,6 +2100,7 @@ if test -n $with_gallium_drivers; then xr600) HAVE_GALLIUM_R600=yes PKG_CHECK_MODULES([RADEON], [libdrm_radeon = $LIBDRM_RADEON_REQUIRED]) +PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu = $LIBDRM_AMDGPU_REQUIRED]) gallium_require_drm Gallium R600 gallium_require_drm_loader if test x$enable_r600_llvm = xyes -o x$enable_opencl = xyes; then @@ -2114,6 +2117,7 @@ if test -n $with_gallium_drivers; then xradeonsi) HAVE_GALLIUM_RADEONSI=yes PKG_CHECK_MODULES([RADEON], [libdrm_radeon = $LIBDRM_RADEON_REQUIRED]) +PKG_CHECK_MODULES([AMDGPU], [libdrm_amdgpu = $LIBDRM_AMDGPU_REQUIRED]) gallium_require_drm radeonsi gallium_require_drm_loader radeon_llvm_check radeonsi @@ -2384,6 +2388,7 @@ AC_CONFIG_FILES([Makefile src/gallium/winsys/intel/drm/Makefile src/gallium/winsys/nouveau/drm/Makefile src/gallium/winsys/radeon/drm/Makefile + src/gallium/winsys/radeon/amdgpu/Makefile src/gallium/winsys/svga/drm/Makefile src/gallium/winsys/sw/dri/Makefile src/gallium/winsys/sw/kms-dri/Makefile diff --git a/src/gallium/Makefile.am b/src/gallium/Makefile.am index ede6e21..fa526d4 100644 --- a/src/gallium/Makefile.am +++ b/src/gallium/Makefile.am @@ -63,6 +63,7 @@ endif ## the radeon winsys - linked in by r300, r600 and radeonsi if NEED_RADEON_DRM_WINSYS SUBDIRS += winsys/radeon/drm +SUBDIRS += winsys/radeon/amdgpu endif ## swrast/softpipe diff --git a/src/gallium/drivers/r300/Automake.inc b/src/gallium/drivers/r300/Automake.inc index 9334973..cfcd61c 100644 --- a/src/gallium/drivers/r300/Automake.inc +++ b/src/gallium/drivers/r300/Automake.inc @@ -5,9 +5,11 @@ TARGET_CPPFLAGS += -DGALLIUM_R300 TARGET_LIB_DEPS += \ $(top_builddir)/src/gallium/drivers/r300/libr300.la \ $(RADEON_LIBS) \ - $(INTEL_LIBS) + $(LIBDRM_LIBS) \ + $(AMDGPU_LIBS) TARGET_RADEON_WINSYS = \ - $(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la + $(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la \ +
[Mesa-dev] (no subject)
Hi, This is the new amdgpu winsys and Mesa support for GCN version 3 (VI) chips. The winsys requires libdrm_amdgpu: http://cgit.freedesktop.org/~agd5f/drm/log/?h=amdgpu The 3D support should be on the same level as Sea Islands (CIK). There is also UVD and VCE support. LLVM 3.6 is required, though LLVM 3.7 is recommended for stability. We'll probably make LLVM 3.6.1 with all the fixes cherry-picked from LLVM 3.7. If some patches don't make it to the list because they are too big (e.g. the addrlib patch), you can also find them here: http://cgit.freedesktop.org/~mareko/mesa/log/?h=amdgpu Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 10/18] gallium/radeon: use VM for VCE
From: Christian König christian.koe...@amd.com
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König christian.koe...@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_vce.c| 24
src/gallium/drivers/radeon/radeon_vce.h| 15 +--
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 17 +++--
3 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index e220f40..d1495a2 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -353,6 +353,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
if (!enc)
return NULL;
+ if (rscreen-info.drm_major == 3)
+ enc-use_vm = true;
if ((rscreen-info.drm_major 2) || (rscreen-info.drm_minor = 42))
enc-use_vui = true;
@@ -428,3 +430,25 @@ bool rvce_is_fw_version_supported(struct
r600_common_screen *rscreen)
{
return rscreen-info.vce_fw_version == ((40 24) | (2 16) | (2
8));
}
+
+/**
+ * Add the buffer as relocation to the current command submission
+ */
+void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle
*buf,
+ enum radeon_bo_usage usage, enum radeon_bo_domain domain,
+ uint32_t offset)
+{
+ int reloc_idx;
+
+ reloc_idx = enc-ws-cs_add_reloc(enc-cs, buf, usage, domain,
RADEON_PRIO_MIN);
+ if (enc-use_vm) {
+ uint64_t addr;
+ addr = enc-ws-buffer_get_virtual_address(buf);
+ addr = addr + offset;
+ RVCE_CS(addr 32);
+ RVCE_CS(addr);
+ } else {
+ RVCE_CS(reloc_idx * 4);
+ RVCE_CS(offset);
+ }
+}
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 5c6317a..67ba333 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -36,13 +36,11 @@
#include util/u_double_list.h
-#define RVCE_RELOC(buf, usage, domain) (enc-ws-cs_add_reloc(enc-cs, (buf),
(usage), domain, RADEON_PRIO_MIN))
-
#define RVCE_CS(value) (enc-cs-buf[enc-cs-cdw++] = (value))
#define RVCE_BEGIN(cmd) { uint32_t *begin = enc-cs-buf[enc-cs-cdw++];
RVCE_CS(cmd)
-#define RVCE_READ(buf, domain) RVCE_CS(RVCE_RELOC(buf, RADEON_USAGE_READ,
domain) * 4)
-#define RVCE_WRITE(buf, domain) RVCE_CS(RVCE_RELOC(buf, RADEON_USAGE_WRITE,
domain) * 4)
-#define RVCE_READWRITE(buf, domain) RVCE_CS(RVCE_RELOC(buf,
RADEON_USAGE_READWRITE, domain) * 4)
+#define RVCE_READ(buf, domain, off) rvce_add_buffer(enc, (buf),
RADEON_USAGE_READ, (domain), (off))
+#define RVCE_WRITE(buf, domain, off) rvce_add_buffer(enc, (buf),
RADEON_USAGE_WRITE, (domain), (off))
+#define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf),
RADEON_USAGE_READWRITE, (domain), (off))
#define RVCE_END() *begin = (enc-cs-buf[enc-cs-cdw] - begin) * 4; }
struct r600_common_screen;
@@ -101,7 +99,8 @@ struct rvce_encoder {
struct rvid_buffer *fb;
struct rvid_buffer cpb;
struct pipe_h264_enc_picture_desc pic;
- bool use_vui;
+ booluse_vm;
+ booluse_vui;
};
struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
@@ -111,6 +110,10 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen);
+void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle
*buf,
+enum radeon_bo_usage usage, enum radeon_bo_domain domain,
+uint32_t offset);
+
/* init vce fw 40.2.2 specific callbacks */
void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 0902957..1e7f278 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -94,8 +94,7 @@ static void task_info(struct rvce_encoder *enc, uint32_t
taskOperation)
static void feedback(struct rvce_encoder *enc)
{
RVCE_BEGIN(0x0505); // feedback buffer
- RVCE_WRITE(enc-fb-res-cs_buf, enc-fb-res-domains); //
feedbackRingAddressHi
- RVCE_CS(0x); // feedbackRingAddressLo
+ RVCE_WRITE(enc-fb-res-cs_buf, enc-fb-res-domains, 0x0); //
feedbackRingAddressHi/Lo
RVCE_CS(0x0001); // feedbackRingSize
RVCE_END();
}
@@ -306,13 +305,11 @@ static void encode(struct rvce_encoder *enc)
task_info(enc, 0x0003);
[Mesa-dev] [PATCH 07/18] radeonsi: add VI hardware support
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 6
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeonsi/si_descriptors.c | 15 +++--
src/gallium/drivers/radeonsi/si_pipe.c | 5 ++-
src/gallium/drivers/radeonsi/si_shader.c| 24 +++--
src/gallium/drivers/radeonsi/si_state.c | 45 +
src/gallium/drivers/radeonsi/si_state_draw.c| 41 --
src/gallium/drivers/radeonsi/si_state_shaders.c | 8 -
8 files changed, 121 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 3b26dea..80a32ca 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -379,6 +379,9 @@ static const char* r600_get_name(struct pipe_screen*
pscreen)
case CHIP_KABINI: return AMD KABINI;
case CHIP_HAWAII: return AMD HAWAII;
case CHIP_MULLINS: return AMD MULLINS;
+ case CHIP_TONGA: return AMD TONGA;
+ case CHIP_ICELAND: return AMD ICELAND;
+ case CHIP_CARRIZO: return AMD CARRIZO;
default: return AMD unknown;
}
}
@@ -496,6 +499,9 @@ const char *r600_get_llvm_processor_name(enum radeon_family
family)
#else
return kabini;
#endif
+ case CHIP_TONGA: return tonga;
+ case CHIP_ICELAND: return iceland;
+ case CHIP_CARRIZO: return carrizo;
default: return ;
}
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index bdb4541..8944059 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -232,6 +232,7 @@ struct r600_surface {
unsigned cb_color_pitch;/* EG and later */
unsigned cb_color_slice;/* EG and later */
unsigned cb_color_attrib; /* EG and later */
+ unsigned cb_dcc_control;/* VI and later */
unsigned cb_color_fmask;/* CB_COLORn_FMASK (EG and later) or
CB_COLORn_FRAG (r600) */
unsigned cb_color_fmask_slice; /* EG and later */
unsigned cb_color_cmask;/* CB_COLORn_TILE (r600 only) */
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index bbfd36d..88a507d 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -675,7 +675,8 @@ void si_update_vertex_buffers(struct si_context *sctx)
desc[0] = va 0x;
desc[1] = S_008F04_BASE_ADDRESS_HI(va 32) |
S_008F04_STRIDE(vb-stride);
- if (vb-stride)
+
+ if (sctx-b.chip_class = CIK vb-stride)
/* Round up by rounding down and adding 1 */
desc[2] = (vb-buffer-width0 - offset -
sctx-vertex_elements-format_size[i]) /
@@ -839,6 +840,9 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint
shader, uint slot,
break;
}
+ if (sctx-b.chip_class = VI stride)
+ num_records *= stride;
+
/* Set the descriptor. */
uint32_t *desc = buffers-desc_data[slot];
desc[0] = va;
@@ -929,7 +933,11 @@ static void si_set_streamout_targets(struct pipe_context
*ctx,
struct pipe_resource *buffer = targets[i]-buffer;
uint64_t va = r600_resource(buffer)-gpu_address;
- /* Set the descriptor. */
+ /* Set the descriptor.
+*
+* On VI, the format must be non-INVALID, otherwise
+* the buffer will be considered not bound and store
+* instructions will be no-ops. */
uint32_t *desc = buffers-desc_data[bufidx];
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va 32);
@@ -937,7 +945,8 @@ static void si_set_streamout_targets(struct pipe_context
*ctx,
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
/* Set the resource. */
pipe_resource_reference(buffers-buffers[bufidx],
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 91b4d6f..0bb7a35 100644
[Mesa-dev] [PATCH 08/18] radeonsi: add a temporary workaround for a shader bug
From: Marek Olšák marek.ol...@amd.com
This will be reverted after the corresponding LLVM fix is cherry-picked and
released as part of LLVM 3.6.
---
src/gallium/drivers/radeonsi/si_state_shaders.c | 47 -
1 file changed, 31 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 09ca792..5833ee1 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -33,7 +33,19 @@
#include util/u_memory.h
#include util/u_simple_shaders.h
-static void si_shader_es(struct si_shader *shader)
+/* TODO: the compiler has a better workaround, remove this */
+static unsigned si_adjust_num_sgprs(struct si_screen *sscreen, unsigned
num_sgprs)
+{
+ assert(num_sgprs = 104);
+
+ if (sscreen-b.family == CHIP_TONGA ||
+ sscreen-b.family == CHIP_ICELAND)
+ num_sgprs = 104;
+
+ return num_sgprs;
+}
+
+static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
unsigned num_sgprs, num_user_sgprs;
@@ -57,7 +69,7 @@ static void si_shader_es(struct si_shader *shader)
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs = num_user_sgprs + 1 + 2;
}
- assert(num_sgprs = 104);
+ num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va 8);
si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va 40);
@@ -71,7 +83,7 @@ static void si_shader_es(struct si_shader *shader)
S_00B32C_SCRATCH_EN(shader-scratch_bytes_per_wave 0));
}
-static void si_shader_gs(struct si_shader *shader)
+static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
{
unsigned gs_vert_itemsize = shader-selector-info.num_outputs * (16
2);
unsigned gs_max_vert_out = shader-selector-gs_max_out_vertices;
@@ -130,7 +142,7 @@ static void si_shader_gs(struct si_shader *shader)
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs = num_user_sgprs + 2 + 2;
}
- assert(num_sgprs = 104);
+ num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader-num_vgprs - 1) / 4) |
@@ -141,7 +153,7 @@ static void si_shader_gs(struct si_shader *shader)
S_00B22C_SCRATCH_EN(shader-scratch_bytes_per_wave 0));
}
-static void si_shader_vs(struct si_shader *shader)
+static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader)
{
struct tgsi_shader_info *info = shader-selector-info;
struct si_pm4_state *pm4;
@@ -173,7 +185,7 @@ static void si_shader_vs(struct si_shader *shader)
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs = num_user_sgprs + 2;
}
- assert(num_sgprs = 104);
+ num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
/* Certain attributes (position, psize, etc.) don't count as params.
* VS is required to export at least one param and
r600_shader_from_tgsi()
@@ -233,7 +245,7 @@ static void si_shader_vs(struct si_shader *shader)
S_028818_VPORT_Z_SCALE_ENA(1) |
S_028818_VPORT_Z_OFFSET_ENA(1));
}
-static void si_shader_ps(struct si_shader *shader)
+static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
{
struct tgsi_shader_info *info = shader-selector-info;
struct si_pm4_state *pm4;
@@ -308,7 +320,7 @@ static void si_shader_ps(struct si_shader *shader)
/* Last 2 reserved SGPRs are used for VCC */
num_sgprs = num_user_sgprs + 1 + 2;
}
- assert(num_sgprs = 104);
+ num_sgprs = si_adjust_num_sgprs(sscreen, num_sgprs);
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
S_00B028_VGPRS((shader-num_vgprs - 1) / 4) |
@@ -320,7 +332,8 @@ static void si_shader_ps(struct si_shader *shader)
S_00B32C_SCRATCH_EN(shader-scratch_bytes_per_wave 0));
}
-static void si_shader_init_pm4_state(struct si_shader *shader)
+static void si_shader_init_pm4_state(struct si_screen *sscreen,
+struct si_shader *shader)
{
if (shader-pm4)
@@ -329,16 +342,16 @@ static void si_shader_init_pm4_state(struct si_shader
*shader)
switch (shader-selector-type) {
case PIPE_SHADER_VERTEX:
if (shader-key.vs.as_es)
- si_shader_es(shader);
+ si_shader_es(sscreen, shader);
else
- si_shader_vs(shader);
+ si_shader_vs(sscreen, shader);
break;
case PIPE_SHADER_GEOMETRY:
-
[Mesa-dev] [PATCH 09/18] gallium/radeon: use VM for UVD
From: Christian König christian.koe...@amd.com
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König christian.koe...@amd.com
Signed-off-by: Leo Liu leo@amd.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/radeon/radeon_uvd.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index be58d0b..ac850a2 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -82,6 +82,7 @@ struct ruvd_decoder {
unsignedbs_size;
struct rvid_buffer dpb;
+ booluse_legacy;
};
/* flush IB to the hardware */
@@ -107,8 +108,16 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned
cmd,
reloc_idx = dec-ws-cs_add_reloc(dec-cs, cs_buf, usage, domain,
RADEON_PRIO_MIN);
- set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
- set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
+ if (!dec-use_legacy) {
+ uint64_t addr;
+ addr = dec-ws-buffer_get_virtual_address(cs_buf);
+ addr = addr + off;
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr 32);
+ } else {
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
+ set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
+ }
set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd 1);
}
@@ -791,6 +800,9 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
if (!dec)
return NULL;
+ if (info.drm_major 3)
+ dec-use_legacy = TRUE;
+
dec-base = *templ;
dec-base.context = context;
dec-base.width = width;
--
2.1.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/18] winsys/radeon: add a private interface for radeon_surface
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/evergreen_state.c | 6 +-
src/gallium/drivers/r600/r600_uvd.c| 2 +-
src/gallium/drivers/radeon/r600_pipe_common.h | 2 +-
src/gallium/drivers/radeon/r600_texture.c | 12 +-
src/gallium/drivers/radeon/radeon_uvd.c| 6 +-
src/gallium/drivers/radeon/radeon_uvd.h| 4 +-
src/gallium/drivers/radeon/radeon_vce.c| 2 +-
src/gallium/drivers/radeon/radeon_vce.h| 6 +-
src/gallium/drivers/radeon/radeon_video.c | 2 +-
src/gallium/drivers/radeon/radeon_video.h | 2 +-
src/gallium/drivers/radeonsi/si_state.c| 4 +-
src/gallium/drivers/radeonsi/si_uvd.c | 4 +-
src/gallium/winsys/radeon/drm/Makefile.sources | 1 +
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 180 +
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 +--
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1 +
src/gallium/winsys/radeon/radeon_winsys.h | 79 -
17 files changed, 286 insertions(+), 47 deletions(-)
create mode 100644 src/gallium/winsys/radeon/drm/radeon_drm_surface.c
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index edd886b..8951ab0 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -664,7 +664,7 @@ evergreen_create_sampler_view_custom(struct pipe_context
*ctx,
unsigned height, depth, width;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
enum pipe_format pipe_format = state-format;
- struct radeon_surface_level *surflevel;
+ struct radeon_surf_level *surflevel;
unsigned base_level, first_level, last_level;
uint64_t va;
@@ -918,7 +918,7 @@ static void evergreen_emit_scissor_state(struct
r600_context *rctx, struct r600_
/**
* This function intializes the CB* register values for RATs. It is meant
* to be used for 1D aligned buffers that do not have an associated
- * radeon_surface.
+ * radeon_surf.
*/
void evergreen_init_color_surface_rat(struct r600_context *rctx,
struct r600_surface *surf)
@@ -1163,7 +1163,7 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
struct r600_screen *rscreen = rctx-screen;
struct r600_texture *rtex = (struct r600_texture*)surf-base.texture;
unsigned level = surf-base.u.tex.level;
- struct radeon_surface_level *levelinfo = rtex-surface.level[level];
+ struct radeon_surf_level *levelinfo = rtex-surface.level[level];
uint64_t offset;
unsigned format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
diff --git a/src/gallium/drivers/r600/r600_uvd.c
b/src/gallium/drivers/r600/r600_uvd.c
index ee5288f..357e901 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -57,7 +57,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct
pipe_context *pipe,
{
struct r600_context *ctx = (struct r600_context *)pipe;
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
- struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {};
+ struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
const enum pipe_format *resource_formats;
struct pipe_video_buffer template;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index b7df001..bdb4541 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -195,7 +195,7 @@ struct r600_texture {
unsigneddirty_level_mask; /* each bit says if
that mipmap is compressed */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
- struct radeon_surface surface;
+ struct radeon_surf surface;
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ab8ce7b..dc510c9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -119,7 +119,7 @@ static unsigned r600_texture_get_offset(struct r600_texture
*rtex, unsigned leve
}
static int r600_init_surface(struct r600_common_screen *rscreen,
-struct radeon_surface *surface,
+struct radeon_surf *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
bool is_flushed_depth)
@@ -234,7 +234,7 @@ static boolean
[Mesa-dev] [PATCH 05/18] radeonsi: fix DRM version checks for amdgpu DRM 3.0.0
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_buffer_common.c | 6 --
src/gallium/drivers/radeon/r600_pipe_common.c | 4 +++-
src/gallium/drivers/radeon/r600_texture.c | 8 +---
src/gallium/drivers/radeonsi/si_pipe.c | 4 +++-
src/gallium/drivers/radeonsi/si_state.c | 8
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index fc5f6c2..ac395fa 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
- if (rscreen-info.drm_minor 40) {
+ if (rscreen-info.drm_major == 2
+ rscreen-info.drm_minor 40) {
res-domains = RADEON_DOMAIN_GTT;
flags |= RADEON_FLAG_GTT_WC;
break;
@@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
* Write-combined CPU mappings are fine, the kernel ensures all
CPU
* writes finish before the GPU executes a command stream.
*/
- if (rscreen-info.drm_minor 40)
+ if (rscreen-info.drm_major == 2
+ rscreen-info.drm_minor 40)
res-domains = RADEON_DOMAIN_GTT;
else if (res-domains RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_CPU_ACCESS;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index c6d7918..3b26dea 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -864,7 +864,9 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
util_format_s3tc_init();
pipe_mutex_init(rscreen-aux_context_lock);
- if (rscreen-info.drm_minor = 28 (rscreen-debug_flags
DBG_TRACE_CS)) {
+ if (((rscreen-info.drm_major == 2 rscreen-info.drm_minor = 28) ||
+rscreen-info.drm_major == 3)
+ (rscreen-debug_flags DBG_TRACE_CS)) {
rscreen-trace_bo = (struct
r600_resource*)pipe_buffer_create(rscreen-b,
PIPE_BIND_CUSTOM,
PIPE_USAGE_STAGING,
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index dc510c9..1b64507 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -489,7 +489,7 @@ static unsigned r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
unsigned num_pipes = rscreen-tiling_info.num_channels;
if (rscreen-chip_class = EVERGREEN
- rscreen-info.drm_minor 26)
+ rscreen-info.drm_major == 2 rscreen-info.drm_minor 26)
return 0;
/* HW bug on R6xx. */
@@ -501,7 +501,7 @@ static unsigned r600_texture_get_htile_size(struct
r600_common_screen *rscreen,
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen-chip_class = CIK
rtex-surface.level[0].mode == RADEON_SURF_MODE_1D
- rscreen-info.drm_minor 38)
+ rscreen-info.drm_major == 2 rscreen-info.drm_minor 38)
return 0;
switch (num_pipes) {
@@ -1262,7 +1262,9 @@ void evergreen_do_fast_color_clear(struct
r600_common_context *rctx,
/* fast color clear with 1D tiling doesn't work on old kernels
and CIK */
if (tex-surface.level[0].mode == RADEON_SURF_MODE_1D
- rctx-chip_class = CIK rctx-screen-info.drm_minor
38) {
+ rctx-chip_class = CIK
+ rctx-screen-info.drm_major == 2
+ rctx-screen-info.drm_minor 38) {
continue;
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index e68c30e..91b4d6f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -259,7 +259,9 @@ static int si_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_TEXTURE_MULTISAMPLE:
/* 2D tiling on CIK is supported since DRM 2.35.0 */
return sscreen-b.chip_class CIK ||
- sscreen-b.info.drm_minor = 35;
+ (sscreen-b.info.drm_major == 2
+ sscreen-b.info.drm_minor = 35) ||
+ sscreen-b.info.drm_major == 3;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
[Mesa-dev] [PATCH 00/18] AMDGPU winsys and VI hardware support
Hi, This is the new amdgpu winsys and Mesa support for GCN version 3 (VI) chips. The winsys requires libdrm_amdgpu: http://cgit.freedesktop.org/~agd5f/drm/log/?h=amdgpu The 3D support should be on the same level as Sea Islands (CIK). There is also UVD and VCE support. LLVM 3.6 is required, though LLVM 3.7 is recommended for stability. We'll probably make LLVM 3.6.1 with all the fixes cherry-picked from LLVM 3.7. If some patches don't make it to the list because they are too big (e.g. the addrlib patch), you can also find them here: http://cgit.freedesktop.org/~mareko/mesa/log/?h=amdgpu Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] glsl: add fallthrough comment on switch
On Mon, Apr 20, 2015 at 10:27 PM, Tapani Pälli tapani.pa...@intel.com wrote: Signed-off-by: Tapani Pälli tapani.pa...@intel.com --- src/glsl/linker.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index b6baa5d..08b4137 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -2571,6 +2571,7 @@ add_interface_variables(struct gl_shader_program *shProg, var-data.location != SYSTEM_VALUE_VERTEX_ID_ZERO_BASE var-data.location != SYSTEM_VALUE_INSTANCE_ID) continue; The continue should be indented. + /* FALLTHROUGH */ case ir_var_shader_in: if (programInterface != GL_PROGRAM_INPUT) continue; -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 03/24] mesa/glsl: build list of program resources during linking
On Wed, Apr 1, 2015 at 5:14 AM, Tapani Pälli tapani.pa...@intel.com wrote:
Patch adds ProgramResourceList to gl_shader_program structure.
List contains references to active program resources and is
constructed during linking phase.
This list will be used by follow-up patches to implement hooks
for GL_ARB_program_interface_query. It can be also used to
implement any of the older shader program query APIs.
v2: code cleanups + note for SSBO and subroutines (Ilia Mirkin)
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/linker.cpp | 179
++
src/mesa/main/mtypes.h| 14
src/mesa/main/shaderobj.c | 6 ++
3 files changed, 199 insertions(+)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 73432b2..a757425 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -2492,6 +2492,181 @@ check_explicit_uniform_locations(struct gl_context
*ctx,
delete uniform_map;
}
+static bool
+add_program_resource(struct gl_shader_program *prog, GLenum type,
+ const void *data, uint8_t stages)
+{
+ assert(data);
+
+ /* If resource already exists, do not add it again. */
+ for (unsigned i = 0; i prog-NumProgramResourceList; i++)
+ if (prog-ProgramResourceList[i].Data == data)
+ return true;
+
+ prog-ProgramResourceList =
+ reralloc(prog,
+ prog-ProgramResourceList,
+ gl_program_resource,
+ prog-NumProgramResourceList + 1);
+
+ if (!prog-ProgramResourceList) {
+ linker_error(prog, Out of memory during linking.\n);
+ return false;
+ }
+
+ struct gl_program_resource *res =
+ prog-ProgramResourceList[prog-NumProgramResourceList];
+
+ res-Type = type;
+ res-Data = data;
+ res-StageReferences = stages;
+
+ prog-NumProgramResourceList++;
+
+ return true;
+}
+
+/**
+ * Function builds a stage reference bitmask from variable name.
+ */
+static uint8_t
+build_stageref(struct gl_shader_program *shProg, const char *name)
+{
+ uint8_t stages = 0;
+ for (unsigned i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+ if (!sh)
+ continue;
+ ir_variable *var = sh-symbols-get_variable(name);
+ if (var)
+ stages |= (1 i);
+ }
+ return stages;
+}
+
+/**
+ * Builds up a list of program resources that point to existing
+ * resource data.
+ */
+static void
+build_program_resource_list(struct gl_context *ctx,
+struct gl_shader_program *shProg)
+{
+ /* Rebuild resource list. */
+ if (shProg-ProgramResourceList) {
+ ralloc_free(shProg-ProgramResourceList);
+ shProg-ProgramResourceList = NULL;
+ shProg-NumProgramResourceList = 0;
+ }
+
+ int input_stage = MESA_SHADER_STAGES, output_stage = 0;
+
+ /* Determine first input and final output stage. These are used to
+* detect which variables should be enumerated in the resource list
+* for GL_PROGRAM_INPUT and GL_PROGRAM_OUTPUT.
+*/
+ for (unsigned i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+ if (!sh)
+ continue;
+ if (input_stage == MESA_SHADER_STAGES)
+ input_stage = i;
+ output_stage = i;
+ }
+
+ for (int i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+
+ if (!sh || (i != input_stage i != output_stage))
+ continue;
+
+ /* Add inputs and outputs to the resource list. */
+ foreach_in_list(ir_instruction, node, sh-ir) {
+ ir_variable *var = node-as_variable();
+ GLenum iface;
+
+ if (!var)
+continue;
+
+ switch (var-data.mode) {
+ /* From GL 4.3 core spec, section 11.1.1 (Vertex Attributes):
+ * For GetActiveAttrib, all active vertex shader input variables
+ * are enumerated, including the special built-in inputs gl_VertexID
+ * and gl_InstanceID.
+ */
+ case ir_var_system_value:
+if (var-data.location != SYSTEM_VALUE_VERTEX_ID
+var-data.location != SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
+var-data.location != SYSTEM_VALUE_INSTANCE_ID)
+continue;
Coverity is warning about this... and rightly so.
Either the indentation on the continue statement is wrong and it's
missing a /* fallthrough */ comment, or something more serious is
wrong.
+ case ir_var_shader_in:
+if (i != input_stage)
+ continue;
+iface = GL_PROGRAM_INPUT;
+break;
+ case ir_var_shader_out:
+if (i != output_stage)
+ continue;
+iface = GL_PROGRAM_OUTPUT;
+break;
+ default:
+continue;
+ };
+
+ if
Re: [Mesa-dev] [PATCH v2 03/24] mesa/glsl: build list of program resources during linking
On 04/21/2015 04:49 AM, Matt Turner wrote:
On Wed, Apr 1, 2015 at 5:14 AM, Tapani Pälli tapani.pa...@intel.com wrote:
Patch adds ProgramResourceList to gl_shader_program structure.
List contains references to active program resources and is
constructed during linking phase.
This list will be used by follow-up patches to implement hooks
for GL_ARB_program_interface_query. It can be also used to
implement any of the older shader program query APIs.
v2: code cleanups + note for SSBO and subroutines (Ilia Mirkin)
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/linker.cpp | 179 ++
src/mesa/main/mtypes.h| 14
src/mesa/main/shaderobj.c | 6 ++
3 files changed, 199 insertions(+)
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 73432b2..a757425 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -2492,6 +2492,181 @@ check_explicit_uniform_locations(struct gl_context *ctx,
delete uniform_map;
}
+static bool
+add_program_resource(struct gl_shader_program *prog, GLenum type,
+ const void *data, uint8_t stages)
+{
+ assert(data);
+
+ /* If resource already exists, do not add it again. */
+ for (unsigned i = 0; i prog-NumProgramResourceList; i++)
+ if (prog-ProgramResourceList[i].Data == data)
+ return true;
+
+ prog-ProgramResourceList =
+ reralloc(prog,
+ prog-ProgramResourceList,
+ gl_program_resource,
+ prog-NumProgramResourceList + 1);
+
+ if (!prog-ProgramResourceList) {
+ linker_error(prog, Out of memory during linking.\n);
+ return false;
+ }
+
+ struct gl_program_resource *res =
+ prog-ProgramResourceList[prog-NumProgramResourceList];
+
+ res-Type = type;
+ res-Data = data;
+ res-StageReferences = stages;
+
+ prog-NumProgramResourceList++;
+
+ return true;
+}
+
+/**
+ * Function builds a stage reference bitmask from variable name.
+ */
+static uint8_t
+build_stageref(struct gl_shader_program *shProg, const char *name)
+{
+ uint8_t stages = 0;
+ for (unsigned i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+ if (!sh)
+ continue;
+ ir_variable *var = sh-symbols-get_variable(name);
+ if (var)
+ stages |= (1 i);
+ }
+ return stages;
+}
+
+/**
+ * Builds up a list of program resources that point to existing
+ * resource data.
+ */
+static void
+build_program_resource_list(struct gl_context *ctx,
+struct gl_shader_program *shProg)
+{
+ /* Rebuild resource list. */
+ if (shProg-ProgramResourceList) {
+ ralloc_free(shProg-ProgramResourceList);
+ shProg-ProgramResourceList = NULL;
+ shProg-NumProgramResourceList = 0;
+ }
+
+ int input_stage = MESA_SHADER_STAGES, output_stage = 0;
+
+ /* Determine first input and final output stage. These are used to
+* detect which variables should be enumerated in the resource list
+* for GL_PROGRAM_INPUT and GL_PROGRAM_OUTPUT.
+*/
+ for (unsigned i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+ if (!sh)
+ continue;
+ if (input_stage == MESA_SHADER_STAGES)
+ input_stage = i;
+ output_stage = i;
+ }
+
+ for (int i = 0; i MESA_SHADER_STAGES; i++) {
+ struct gl_shader *sh = shProg-_LinkedShaders[i];
+
+ if (!sh || (i != input_stage i != output_stage))
+ continue;
+
+ /* Add inputs and outputs to the resource list. */
+ foreach_in_list(ir_instruction, node, sh-ir) {
+ ir_variable *var = node-as_variable();
+ GLenum iface;
+
+ if (!var)
+continue;
+
+ switch (var-data.mode) {
+ /* From GL 4.3 core spec, section 11.1.1 (Vertex Attributes):
+ * For GetActiveAttrib, all active vertex shader input variables
+ * are enumerated, including the special built-in inputs gl_VertexID
+ * and gl_InstanceID.
+ */
+ case ir_var_system_value:
+if (var-data.location != SYSTEM_VALUE_VERTEX_ID
+var-data.location != SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
+var-data.location != SYSTEM_VALUE_INSTANCE_ID)
+continue;
Coverity is warning about this... and rightly so.
Either the indentation on the continue statement is wrong and it's
missing a /* fallthrough */ comment, or something more serious is
wrong.
It is missing a /* fallthrough */ comment. I'll send a patch that adds
comments for both of the fallthrough cases you found.
// Tapani
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Re: [Mesa-dev] [PATCH v2 06/24] mesa: glGetProgramResourceName
On Wed, Apr 1, 2015 at 5:14 AM, Tapani Pälli tapani.pa...@intel.com wrote:
Patch adds required helper functions to shaderapi.h and
the actual implementation.
Name generation copied from '_mesa_get_uniform_name' which can
be removed later by refactoring functions to use resource list.
The added functionality can be tested by tests for following
functions that are refactored by later patches:
GetActiveUniformName
GetActiveUniformBlockName
v2: no index for geometry shader inputs (Ilia Mirkin)
add bufSize 0 check and error out
validate enum
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/mesa/main/program_resource.c | 23 +
src/mesa/main/shader_query.cpp | 106
+++
src/mesa/main/shaderapi.h| 10
3 files changed, 139 insertions(+)
diff --git a/src/mesa/main/program_resource.c
b/src/mesa/main/program_resource.c
index 72cc558..638f5f2 100644
--- a/src/mesa/main/program_resource.c
+++ b/src/mesa/main/program_resource.c
@@ -245,6 +245,29 @@ _mesa_GetProgramResourceName(GLuint program, GLenum
programInterface,
GLuint index, GLsizei bufSize, GLsizei *length,
GLchar *name)
{
+ GET_CURRENT_CONTEXT(ctx);
+ struct gl_shader_program *shProg =
+ _mesa_lookup_shader_program_err(ctx, program,
+ glGetProgramResourceName);
+
+ /* Set user friendly return values in case of errors. */
+ if (name)
+ *name = '\0';
+ if (length)
+ *length = 0;
+
+ if (!shProg || !name)
+ return;
+
+ if (programInterface == GL_ATOMIC_COUNTER_BUFFER ||
+ !supported_interface_enum(programInterface)) {
+ _mesa_error(ctx, GL_INVALID_ENUM, glGetProgramResourceName(%s),
+ _mesa_lookup_enum_by_nr(programInterface));
+ return;
+ }
+
+ _mesa_get_program_resource_name(shProg, programInterface, index, bufSize,
+ length, name, glGetProgramResourceName);
}
void GLAPIENTRY
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 61eec68..ab61be9 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -648,3 +648,109 @@ _mesa_program_resource_index(struct gl_shader_program
*shProg,
return calc_resource_index(shProg, res);
}
}
+
+/* Find a program resource with specific index in given interface.
+ */
+struct gl_program_resource *
+_mesa_program_resource_find_index(struct gl_shader_program *shProg,
+ GLenum interface, GLuint index)
+{
+ struct gl_program_resource *res = shProg-ProgramResourceList;
+ int idx = -1;
+
+ for (unsigned i = 0; i shProg-NumProgramResourceList; i++, res++) {
+ if (res-Type != interface)
+ continue;
+
+ switch (res-Type) {
+ case GL_UNIFORM_BLOCK:
+ case GL_ATOMIC_COUNTER_BUFFER:
+ if (_mesa_program_resource_index(shProg, res) == index)
+return res;
+
Coverity warns about this fallthrough. Please mark it with /*
fallthrough */ if it's indeed intended.
+ case GL_TRANSFORM_FEEDBACK_VARYING:
+ case GL_PROGRAM_INPUT:
+ case GL_PROGRAM_OUTPUT:
+ case GL_UNIFORM:
+ if (++idx == (int) index)
+return res;
+ break;
+ default:
+ assert(!not implemented for given interface);
+ }
+ }
+ return NULL;
+}
+
+/* Get full name of a program resource.
+ */
+bool
+_mesa_get_program_resource_name(struct gl_shader_program *shProg,
+GLenum interface, GLuint index,
+GLsizei bufSize, GLsizei *length,
+GLchar *name, const char *caller)
+{
+ GET_CURRENT_CONTEXT(ctx);
+
+ /* Find resource with given interface and index. */
+ struct gl_program_resource *res =
+ _mesa_program_resource_find_index(shProg, interface, index);
+
+ /* The error INVALID_VALUE is generated if index is greater than
+ * or equal to the number of entries in the active resource list for
+ * programInterface.
+ */
+ if (!res) {
+ _mesa_error(ctx, GL_INVALID_VALUE, %s(index %u), caller, index);
+ return false;
+ }
+
+ if (bufSize 0) {
+ _mesa_error(ctx, GL_INVALID_VALUE, %s(bufSize %d), caller, bufSize);
+ return false;
+ }
+
+ GLsizei localLength;
+
+ if (length == NULL)
+ length = localLength;
+
+ _mesa_copy_string(name, bufSize, length,
_mesa_program_resource_name(res));
+
+ /* Page 61 (page 73 of the PDF) in section 2.11 of the OpenGL ES 3.0
+* spec says:
+*
+* If the active uniform is an array, the uniform name returned in
+* name will always be the name of the uniform array appended with
+* [0].
+*
+* The same text also appears in the OpenGL
Re: [Mesa-dev] [PATCH 1/5] winsys/radeon: make radeon_bo_vtbl static
On 21.04.2015 06:59, Marek Olšák wrote: From: Marek Olšák marek.ol...@amd.com This series is Reviewed-by: Michel Dänzer michel.daen...@amd.com -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] glsl: add fallthrough comment on switch
Signed-off-by: Tapani Pälli tapani.pa...@intel.com --- src/glsl/linker.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index b6baa5d..08b4137 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -2571,6 +2571,7 @@ add_interface_variables(struct gl_shader_program *shProg, var-data.location != SYSTEM_VALUE_VERTEX_ID_ZERO_BASE var-data.location != SYSTEM_VALUE_INSTANCE_ID) continue; + /* FALLTHROUGH */ case ir_var_shader_in: if (programInterface != GL_PROGRAM_INPUT) continue; -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] mesa: add missing break in switch statement
Signed-off-by: Tapani Pälli tapani.pa...@intel.com --- src/mesa/main/shader_query.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp index 1428058..336598d 100644 --- a/src/mesa/main/shader_query.cpp +++ b/src/mesa/main/shader_query.cpp @@ -634,7 +634,7 @@ _mesa_program_resource_find_index(struct gl_shader_program *shProg, case GL_ATOMIC_COUNTER_BUFFER: if (_mesa_program_resource_index(shProg, res) == index) return res; - + break; case GL_TRANSFORM_FEEDBACK_VARYING: case GL_PROGRAM_INPUT: case GL_PROGRAM_OUTPUT: -- 2.1.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] mesa: fix UBO queries for active uniforms
Commit 34df5eb introduced regression to GetActiveUniformBlockiv
when querying one of the following properties:
GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS
GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES
Implementation counted all uniforms in ubo directly while query should
check first if the uniform in quersion is _active_.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109
---
src/mesa/main/shader_query.cpp | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index b5f1d08..1428058 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -860,13 +860,23 @@ get_buffer_property(struct gl_shader_program *shProg,
*val = RESOURCE_UBO(res)-UniformBufferSize;
return 1;
case GL_NUM_ACTIVE_VARIABLES:
- *val = RESOURCE_UBO(res)-NumUniforms;
+ *val = 0;
+ for (unsigned i = 0; i RESOURCE_UBO(res)-NumUniforms; i++) {
+const char *iname = RESOURCE_UBO(res)-Uniforms[i].IndexName;
+struct gl_program_resource *uni =
+ _mesa_program_resource_find_name(shProg, GL_UNIFORM, iname);
+if (!uni)
+ continue;
+(*val)++;
+ }
return 1;
case GL_ACTIVE_VARIABLES:
for (unsigned i = 0; i RESOURCE_UBO(res)-NumUniforms; i++) {
const char *iname = RESOURCE_UBO(res)-Uniforms[i].IndexName;
struct gl_program_resource *uni =
_mesa_program_resource_find_name(shProg, GL_UNIFORM, iname);
+if (!uni)
+ continue;
*val++ =
_mesa_program_resource_index(shProg, uni);
}
--
2.1.0
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Re: [Mesa-dev] [PATCH 2/2] clover: remove pre llvm 3.5.0 compatibility code
On Sun, Apr 19, 2015 at 10:50:19AM +0200, EdB wrote:
---
Reviewed-by: Tom Stellard thomas.stell...@amd.com
.../state_trackers/clover/llvm/invocation.cpp | 23
++
1 file changed, 2 insertions(+), 21 deletions(-)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index 4da62b9..e07d95b 100644
--- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
+++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
@@ -29,21 +29,14 @@
#include clang/Basic/TargetInfo.h
#include llvm/Bitcode/BitstreamWriter.h
#include llvm/Bitcode/ReaderWriter.h
-#if HAVE_LLVM 0x0305
-#include llvm/Linker.h
-#else
#include llvm/Linker/Linker.h
#include llvm/IR/DiagnosticInfo.h
#include llvm/IR/DiagnosticPrinter.h
-#endif
#include llvm/IR/DerivedTypes.h
#include llvm/IR/LLVMContext.h
#include llvm/IR/Module.h
#include llvm/Support/SourceMgr.h
#include llvm/IRReader/IRReader.h
-#if HAVE_LLVM 0x0305
-#include llvm/ADT/OwningPtr.h
-#endif
#if HAVE_LLVM = 0x0307
#include llvm/IR/LegacyPassManager.h
#else
@@ -328,9 +321,7 @@ namespace {
llvm::Function *kernel = *I;
export_list.push_back(kernel-getName().data());
}
-#if HAVE_LLVM 0x0305
- PM.add(new llvm::DataLayout(mod));
-#elif HAVE_LLVM 0x0306
+#if HAVE_LLVM 0x0306
PM.add(new llvm::DataLayoutPass(mod));
#elif HAVE_LLVM 0x0307
PM.add(new llvm::DataLayoutPass());
@@ -356,11 +347,7 @@ namespace {
compat::vectormodule::argument args;
llvm::Function *kernel_func = mod-getFunction(kernel_name);
-#if HAVE_LLVM 0x0305
- llvm::DataLayout TD(kernel_func-getParent()-getDataLayout());
-#else
- llvm::DataLayout TD(mod);
-#endif
+ llvm::DataLayout TD(mod);
for (llvm::Function::const_arg_iterator I = kernel_func-arg_begin(),
E = kernel_func-arg_end(); I != E;
++I) {
@@ -651,8 +638,6 @@ namespace {
return m;
}
-#if HAVE_LLVM = 0x0305
-
void
diagnostic_handler(const llvm::DiagnosticInfo di, void *data) {
if (di.getSeverity() == llvm::DS_Error) {
@@ -667,8 +652,6 @@ namespace {
}
}
-#endif
-
void
init_targets() {
static bool targets_initialized = false;
@@ -721,9 +704,7 @@ clover::compile_program_llvm(const compat::string source,
llvm::LLVMContext llvm_ctx;
unsigned optimization_level;
-#if HAVE_LLVM = 0x0305
llvm_ctx.setDiagnosticHandler(diagnostic_handler, r_log);
-#endif
if (get_debug_flags() DBG_CLC)
debug_log(source, .cl);
--
2.3.5
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Re: [Mesa-dev] [PATCH 1/2] clover: make llvm = 3.5.0 and c++11 mandatory
On Sun, Apr 19, 2015 at 10:50:18AM +0200, EdB wrote:
Clover not longer compile with llvm = 3.5.0 since e1d363b3
e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it
No one seems to have noticed it. It's now official.
Thanks for working on this.
---
configure.ac | 32
---
src/gallium/state_trackers/clover/Makefile.am | 6 ++---
2 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/configure.ac b/configure.ac
index 325b936..ff4eef3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1865,6 +1865,13 @@ strip_unwanted_llvm_flags() {
-e 's/-fstack-protector-strong\//g'
}
+llvm_check_for() {
+if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt
${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}${LLVM_REQUIRED_VERSION_PATCH};
then
+AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR.$LLVM_REQUIRED_VERSION_PATCH
or newer is required for $1])
+fi
+}
+
+
if test -z $with_gallium_drivers; then
enable_gallium_llvm=no
@@ -1919,22 +1926,13 @@ if test x$enable_gallium_llvm = xyes; then
fi
if test x$enable_opencl = xyes; then
+LLVM_REQUIRED_VERSION_MAJOR=3
+LLVM_REQUIRED_VERSION_MINOR=5
+LLVM_REQUIRED_VERSION_PATCH=0
Can we make these function arguments rather than global variables?
+llvm_check_for opencl
+
LLVM_COMPONENTS=${LLVM_COMPONENTS} all-targets ipo linker
instrumentation
-# LLVM 3.3 = 177971 requires IRReader
-if $LLVM_CONFIG --components | grep -qw 'irreader'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader
-fi
-# LLVM 3.4 requires Option
-if $LLVM_CONFIG --components | grep -qw 'option'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} option
-fi
-# Current OpenCL/Clover and LLVM 3.5 require ObjCARCOpts and
ProfileData
-if $LLVM_CONFIG --components | grep -qw 'objcarcopts'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} objcarcopts
-fi
-if $LLVM_CONFIG --components | grep -qw 'profiledata'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} profiledata
-fi
+LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader option objcarcopts
profiledata
fi
DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
-DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH
MESA_LLVM=1
@@ -2061,9 +2059,7 @@ radeon_llvm_check() {
LLVM_REQUIRED_VERSION_MAJOR=3
LLVM_REQUIRED_VERSION_MINOR=4
LLVM_REQUIRED_VERSION_PATCH=2
-if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt
${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}${LLVM_REQUIRED_VERSION_PATCH};
then
-AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR.$LLVM_REQUIRED_VERSION_PATCH
or newer is required for $1])
-fi
+llvm_check_for $1
if test true $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
sources with the --enable-experimental-targets=R600
diff --git a/src/gallium/state_trackers/clover/Makefile.am
b/src/gallium/state_trackers/clover/Makefile.am
index 62c13fa..3a45b9c 100644
--- a/src/gallium/state_trackers/clover/Makefile.am
+++ b/src/gallium/state_trackers/clover/Makefile.am
@@ -3,6 +3,7 @@ AUTOMAKE_OPTIONS = subdir-objects
include Makefile.sources
AM_CPPFLAGS = \
+-std=c++11 \
$(GALLIUM_PIPE_LOADER_DEFINES) \
-DPIPE_SEARCH_DIR=\$(libdir)/gallium-pipe\ \
-I$(top_srcdir)/include \
@@ -35,7 +36,6 @@ endif
noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la
libcltgsi_la_CXXFLAGS = \
- -std=c++0x \
$(VISIBILITY_CXXFLAGS)
libcltgsi_la_SOURCES = $(TGSI_SOURCES)
@@ -48,10 +48,10 @@ libclllvm_la_CXXFLAGS = \
-DLIBCLC_LIBEXECDIR=\$(LIBCLC_LIBEXECDIR)/\ \
-DCLANG_RESOURCE_DIR=\$(CLANG_RESOURCE_DIR)\
-libclllvm_la_SOURCES = $(LLVM_SOURCES)
+libclllvm_la_SOURCES = \
+$(LLVM_SOURCES)
libclover_la_CXXFLAGS = \
- -std=c++11 \
$(VISIBILITY_CXXFLAGS)
libclover_la_LIBADD = \
--
2.3.5
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[Mesa-dev] [Bug 84805] DEF files missing for GLES1/GLES2
https://bugs.freedesktop.org/show_bug.cgi?id=84805 --- Comment #6 from Charles Huber genpfa...@gmail.com --- Still working as of cb154bb22116910c462f7a83f4401bd01e15c34d -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 84805] DEF files missing for GLES1/GLES2
https://bugs.freedesktop.org/show_bug.cgi?id=84805 --- Comment #7 from José Fonseca jfons...@vmware.com --- (In reply to Charles Huber from comment #6) Still working as of cb154bb22116910c462f7a83f4401bd01e15c34d That's 10.4 branch. I think this has been broken apart in master: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5564c361b5cc1f5ec4be3622d7f9be601e3c268a There were two EGL implementations: a DRI Linux-specific one, and a cross-platform one, but nobody was interested in maintaining the later one. I wonder if you truly need EGL on Windows, or WGL_EXT_create_context_es_profile could meet your needs. Even if you truly need EGL on Windows, I'm afraid that unless somebody is willing to maintain it, it's not going to come back to life... In short, the patch you proposed only makes sense in the 10.4 branch. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 1/2] clover: make llvm = 3.5.0 and c++11 mandatory
Clover not longer compile with llvm = 3.5.0 since e1d363b3.
e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it.
No one seems to have noticed it, it's now official.
---
configure.ac | 32 +++-
1 file changed, 11 insertions(+), 21 deletions(-)
diff --git a/configure.ac b/configure.ac
index 325b936..095e23e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1865,6 +1865,13 @@ strip_unwanted_llvm_flags() {
-e 's/-fstack-protector-strong\//g'
}
+llvm_check_version_for() {
+if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt ${1}0${2}${3};
then
+AC_MSG_ERROR([LLVM $1.$2.$3 or newer is required for $4])
+fi
+}
+
+
if test -z $with_gallium_drivers; then
enable_gallium_llvm=no
@@ -1919,22 +1926,10 @@ if test x$enable_gallium_llvm = xyes; then
fi
if test x$enable_opencl = xyes; then
+llvm_check_version_for 3 5 0 opencl
+
LLVM_COMPONENTS=${LLVM_COMPONENTS} all-targets ipo linker
instrumentation
-# LLVM 3.3 = 177971 requires IRReader
-if $LLVM_CONFIG --components | grep -qw 'irreader'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader
-fi
-# LLVM 3.4 requires Option
-if $LLVM_CONFIG --components | grep -qw 'option'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} option
-fi
-# Current OpenCL/Clover and LLVM 3.5 require ObjCARCOpts and
ProfileData
-if $LLVM_CONFIG --components | grep -qw 'objcarcopts'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} objcarcopts
-fi
-if $LLVM_CONFIG --components | grep -qw 'profiledata'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} profiledata
-fi
+LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader option objcarcopts
profiledata
fi
DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
-DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH
MESA_LLVM=1
@@ -2058,12 +2053,7 @@ radeon_llvm_check() {
if test x$enable_gallium_llvm != xyes; then
AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
fi
-LLVM_REQUIRED_VERSION_MAJOR=3
-LLVM_REQUIRED_VERSION_MINOR=4
-LLVM_REQUIRED_VERSION_PATCH=2
-if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt
${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}${LLVM_REQUIRED_VERSION_PATCH};
then
-AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR.$LLVM_REQUIRED_VERSION_PATCH
or newer is required for $1])
-fi
+llvm_check_version_for 3 4 2 $1
if test true $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
sources with the --enable-experimental-targets=R600
--
2.1.0
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Re: [Mesa-dev] [PATCH v2 1/2] clover: make llvm = 3.5.0 and c++11 mandatory
EdB edb+m...@sigluy.net writes:
Clover not longer compile with llvm = 3.5.0 since e1d363b3.
e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it.
No one seems to have noticed it, it's now official.
---
I haven't carefully reviewed the series, but I'm fine with dropping
support for LLVM 3.5. For the series:
Acked-by: Francisco Jerez curroje...@riseup.net
configure.ac | 32 +++-
1 file changed, 11 insertions(+), 21 deletions(-)
diff --git a/configure.ac b/configure.ac
index 325b936..095e23e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1865,6 +1865,13 @@ strip_unwanted_llvm_flags() {
-e 's/-fstack-protector-strong\//g'
}
+llvm_check_version_for() {
+if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt ${1}0${2}${3};
then
+AC_MSG_ERROR([LLVM $1.$2.$3 or newer is required for $4])
+fi
+}
+
+
if test -z $with_gallium_drivers; then
enable_gallium_llvm=no
@@ -1919,22 +1926,10 @@ if test x$enable_gallium_llvm = xyes; then
fi
if test x$enable_opencl = xyes; then
+llvm_check_version_for 3 5 0 opencl
+
LLVM_COMPONENTS=${LLVM_COMPONENTS} all-targets ipo linker
instrumentation
-# LLVM 3.3 = 177971 requires IRReader
-if $LLVM_CONFIG --components | grep -qw 'irreader'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader
-fi
-# LLVM 3.4 requires Option
-if $LLVM_CONFIG --components | grep -qw 'option'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} option
-fi
-# Current OpenCL/Clover and LLVM 3.5 require ObjCARCOpts and
ProfileData
-if $LLVM_CONFIG --components | grep -qw 'objcarcopts'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} objcarcopts
-fi
-if $LLVM_CONFIG --components | grep -qw 'profiledata'; then
-LLVM_COMPONENTS=${LLVM_COMPONENTS} profiledata
-fi
+LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader option objcarcopts
profiledata
fi
DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
-DLLVM_VERSION_PATCH=$LLVM_VERSION_PATCH
MESA_LLVM=1
@@ -2058,12 +2053,7 @@ radeon_llvm_check() {
if test x$enable_gallium_llvm != xyes; then
AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
fi
-LLVM_REQUIRED_VERSION_MAJOR=3
-LLVM_REQUIRED_VERSION_MINOR=4
-LLVM_REQUIRED_VERSION_PATCH=2
-if test ${LLVM_VERSION_INT}${LLVM_VERSION_PATCH} -lt
${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}${LLVM_REQUIRED_VERSION_PATCH};
then
-AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR.$LLVM_REQUIRED_VERSION_PATCH
or newer is required for $1])
-fi
+llvm_check_version_for 3 4 2 $1
if test true $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
sources with the --enable-experimental-targets=R600
--
2.1.0
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Re: [Mesa-dev] [PATCH] gallivm: Fix build against LLVM 3.7 SVN r235265
On 20.04.2015 12:51, Nick Sarnie wrote: LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used v2: Be consistent with the LLVM version check (Aaron Watry) Pushed, thanks. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
