Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Lucio De Re
On 9/6/18, Bakul Shah wrote: > > But if all you want to do is just run plan9 why even bother? > But that is disingenuous, isn't it? What one wants is Plan 9 as a model for what may be a family of hardware APIs. It makes sense to promote massive parallelism, but the API to it should be

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Bakul Shah
On Wed, 05 Sep 2018 07:42:52 -0400 Chris McGee wrote: > > It could be, but after having looked briefly at the size of the design for > RISC-V Rocket and especially BOOM I wonder if it's all overly complicated. > They even built their own high level hardware language (Chisel) that > generates

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Chris McGee
> Take a look at greenarraychips.com and how Chuck Moore tries to > simplify the whole instead of software or hardware. > Thanks, that is a very interesting read on the topic of asynchronous and highly parallel computing. I'm not sure if the designs for these are very simple though.

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Iruatã Souza
On Wed, Sep 5, 2018 at 4:45 AM Chris McGee wrote: > > >> Wasn't that the whole point of RISC? > > > It could be, but after having looked briefly at the size of the design for > RISC-V Rocket and especially BOOM I wonder if it's all overly complicated. > They even built their own high level

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Ethan Gardener
On Wed, Sep 5, 2018, at 12:42 PM, Chris McGee wrote: > > They even built their own high level hardware language (Chisel) that > generates Verilog using Scala. Yuck. >From what I've heard of Verilog and VHDL, this is the sane approach. I only >have second hand knowledge of these languages, my

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Chris McGee
> Wasn't that the whole point of RISC? > It could be, but after having looked briefly at the size of the design for RISC-V Rocket and especially BOOM I wonder if it's all overly complicated. They even built their own high level hardware language (Chisel) that generates Verilog using Scala. Yuck.

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Dave MacFarlane
On Tue, Sep 4, 2018, 22:31 Chris McGee, wrote: > > I believe that the core of the problem with the C language is that is >> based upon abstracting the PDP-11 instruction set. CPUs, such as Intel/AMD >> x64 are vastly more complex so "optimising" C compilers are trying to make >> something

Re: [9fans] Is Plan 9 C "Less Dangerous?"

2018-09-05 Thread Ethan Gardener
On Wed, Sep 5, 2018, at 4:25 AM, Ori Bernstein wrote: > > > CPUs, such as Intel/AMD x64 > > are vastly more complex so "optimising" C compilers are trying to make > > something simple take advantage of something far more complex. > > Ironically, because of the complexity in the CPUs, many of the