c void detect_fsb_freq(struct drm_i915_private *i915)
> {
> if (GRAPHICS_VER(i915) == 5)
> i915->fsb_freq = ilk_fsb_freq(i915);
> - else if (IS_PINEVIEW(i915))
> - i915->fsb_freq = pnv_fsb_freq(i915);
> + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
> + i915->fsb_freq = i9xx_fsb_freq(i915);
>
> if (i915->fsb_freq)
> drm_dbg(>drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
> --
> 2.39.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
g in 666 to 667.
>
> Signed-off-by: Jani Nikula
Would it be worth adding a "_khz" suffix to the structure fields to help
clarify the units?
Either way,
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
> drivers/gpu/drm/i915/gt/intel_rps.c
On Tue, May 28, 2024 at 05:24:54PM +0300, Jani Nikula wrote:
> Follow the same style in mem freq init as in fsb freq init, returning
> the value instead of assigning in multiple places.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/soc
On Tue, May 28, 2024 at 05:24:53PM +0300, Jani Nikula wrote:
> Split out the PNV DDR3 detection to a distinct step instead of
> conflating it with mem freq detection.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/soc/intel_dram.c | 12
On Tue, May 28, 2024 at 05:24:52PM +0300, Jani Nikula wrote:
> To simplify further changes, add separate functions for reading the fsb
> frequency.
>
> This ends up reading CLKCFG register twice, but it's not a big deal.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> - "disabling CxSR\n",
> - (dev_priv->is_ddr3 == 1) ? "3" : "2",
> - dev_priv->fsb_freq, dev_priv->mem_freq);
> + drm_info(_priv->drm, "Unknown FSB/MEM, disabling
> CxSR\n");
> /* Disable CxSR and never update its watermark again */
> intel_set_memory_cxsr(dev_priv, false);
> dev_priv->display.funcs.wm = _funcs;
> --
> 2.39.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Tue, May 28, 2024 at 05:24:50PM +0300, Jani Nikula wrote:
> Clarify that the function is specific to PNV, making subsequent changes
> slightly easier to grasp.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c |
IP_VER(20, 0), STEP_B0,
> STEP_FOREVER))
> intel_de_rmw(dev_priv,
> TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder),
>0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
> }
> --
> 2.43.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
t;= MAKE_GUC_VER(70, 21, 1)) &&
> + (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> + IS_MEDIA_GT_IP_RANGE(gt, IP_VER(13, 0), IP_VER(13, 0)) ||
> + IS_DG2(gt->i915)))
> + guc_waklv_enable_simple(guc,
> +
> GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED,
> + , );
>
> size = guc_ads_waklv_size(guc) - remain;
> if (!size)
> --
> 2.43.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
t;= MAKE_GUC_VER(70, 21, 1)) &&
> + (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> + IS_MEDIA_GT_IP_RANGE(gt, IP_VER(13, 0), IP_VER(13, 0)) ||
> + IS_DG2(gt->i915)))
> + guc_waklv_enable_simple(guc,
> +
> GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED,
> + , );
>
> size = guc_ads_waklv_size(guc) - remain;
> if (!size)
> --
> 2.43.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
e explain the reason why this workaround is
> needed here and put it in a comment?
>
> > > Besides, in MTL we have the media GT where the MOD_CTRL family
> > > has address 0x38cf34. Should this be checked and included, as
> > > well?
> >
> > The gt pointer passed into xelpmp_gt_workarounds_init() is always the
> > media GT. And the GSI offset of 0x38 gets added into the register
> > offset automatically so you don't need to worry about doing so manually.
>
> Correct, thanks!
>
> Andi
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
et of 0x38 gets added into the register
offset automatically so you don't need to worry about doing so manually.
Matt
>
> Thanks,
> Andi
>
> > /* Wa_22016670082 */
> > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> >
> > --
> > 2.34.1
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
e the batches submitted in parallel are nearly identical and
expected to run the same amount of time, right? Do we have any
userspace (or potential future userspace) that might submit
heterogeneous batches in parallel, which would make this inaccurate?
I'm not very familiar with the use cases of par
_initial.c | 1 +
> include/uapi/drm/drm_fourcc.h | 12
> 5 files changed, 27 insertions(+), 1 deletion(-)
>
> --
> 2.43.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
.platform == XE_ALDERLAKE_P))
>
> And wrong paths being taken on the display side.
>
> Signed-off-by: Lucas De Marchi
ADL-N uses exactly the same display IP as ADL-P (unlike on the GT side
where they differ), so
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/xe/compa
On Mon, Apr 15, 2024 at 10:07:32AM -0700, Matt Roper wrote:
> On Mon, Apr 15, 2024 at 01:44:22PM +0530, Balasubramani Vivekanandan wrote:
> > From: Matthew Auld
> >
> > Perform manual transient cache flush prior to flip and at the end of
> > frontbuffer_flush. This
Anyway, the changes here look good to me,
Reviewed-by: Matt Roper
> Signed-off-by: Matthew Auld
> Signed-off-by: Balasubramani Vivekanandan
>
> Acked-by: Nirmoy Das
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> .../gpu/drm/i915/display/intel_fron
sh at the start of flip sequence to
> ensure all transient data in L3 cache is flushed to memory. Add a
> routine for this which we can then call from the display code.
>
> CC: Matt Roper
> Signed-off-by: Nirmoy Das
> Co-developed-by: Matthew Auld
> Signed-off-by: Matthew
On Mon, Apr 15, 2024 at 01:44:16PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL
> register. Restrict the programming only to Xe_LPD+.
>
> BSpec: 49213
> CC: Ma
On Mon, Apr 15, 2024 at 01:44:13PM +0530, Balasubramani Vivekanandan wrote:
> From: Lucas De Marchi
>
> Add initial display info for xe2hpd. It is similar to xelpdp, but with no
> PORT_B.
>
> v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES
>
> Bspec
or each modifier above would take care of it.
>
> CC: Juha-Pekka Heikkilä
> CC: Matt Roper
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 16 +---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> di
to apply on all versions starting from
> 14
> * Improved the print log
>
> Bspec: 50110
> CC: Suraj Kandpal
> CC: Matt Roper
> CC: Jani Nikula
> Signed-off-by: Mitul Golani
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display
lasubramani Vivekanandan
>
Reviewed-by: Matt Roper
Does this commit need a Fixes: too?
Matt
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_c
ICKENBIT_REG3, 0,
> > CHICKEN3_SPARE18);
> > > +
> > > /* Enable audio presence detect */
> > > intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
> > > 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
> > > diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> > > index 616e7b1275c4..6f8d33299ecd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> > > @@ -148,4 +148,7 @@
> > > #define HBLANK_START_COUNT_964
> > > #define HBLANK_START_COUNT_128 5
> > >
> > > +#define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C)
> > > +#define CHICKEN3_SPARE18REG_BIT(18)
> > > +
> > > #endif /* __INTEL_AUDIO_REGS_H__ */
> > > --
> > > 2.42.0
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Thu, Apr 11, 2024 at 03:36:37PM -0700, Matt Roper wrote:
> On Wed, Apr 10, 2024 at 07:20:46PM +0530, Uma Shankar wrote:
> > WA_14020863754: Corner case with Min Hblank Fix can cause
> > audio hang
> >
> > Issue: Previously a fix was made to avoid issues with extremel
pu/drm/i915/display/intel_audio_regs.h
> @@ -148,4 +148,7 @@
> #define HBLANK_START_COUNT_964
> #define HBLANK_START_COUNT_128 5
>
> +#define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C)
> +#define CHICKEN3_SPARE18REG_BIT(18)
> +
> #endif /* __INTEL_AUDIO_REGS_H__ */
> --
> 2.42.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
crtc->pipe,
>
> new_dbuf_state->active_pipes))
> pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
@ static const struct {
> const struct intel_display_device_info *display;
> } gmdid_display_map[] = {
> { 14, 0, _lpdp_display },
> + { 14, 1, _hpd_display },
> { 20, 0, _lpd_display },
> };
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
here is misleading since "missing" makes it sound like
we overlooked something previously, whereas in reality this is just a
new required step on Xe2_HPD. A title like "Configure CHICKEN_MISC_2
before enabling planes" would probably be more accurate.
With updated wordi
br3,
> + _c20_dp_uhbr10,
> + _c20_dp_uhbr13_5,
> + _c20_dp_uhbr20,
According to bspec 67066, I don't think we need the UHBR20 table for
Xe2_HPD (even though there are data values given on page 74165).
Otherwise,
Reviewed-by: Matt Roper
Matt
> + NULL,
> +};
&
e more accurate?
Otherwise the tables below match the current spec, so
Reviewed-by: Matt Roper
>
> CC: Clint Taylor
> Signed-off-by: Balasubramani Vivekanandan
>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++-
> 1 file changed, 146 in
On Wed, Apr 03, 2024 at 04:52:37PM +0530, Balasubramani Vivekanandan wrote:
> From: José Roberto de Souza
>
> Xe2_HPD has a different value to power down port A.
>
> BSpec: 65450
> CC: Matt Roper
> Signed-off-by: José Roberto de Souza
> Signed-off-by: Balasubramani Vi
in DG2. Extend this to future discrete products.
>
> Signed-off-by: Radhakrishna Sripada
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
&g
in Bspec:20124.
>
> Signed-off-by: Ankit Nautiyal
> Signed-off-by: Balasubramani Vivekanandan
>
Matches our experimental findings, so
Reviewed-by: Matt Roper
I've pinged the internal ticket to try to get the documentation for this
clarified.
BTW, if you send another version of thi
On Wed, Apr 03, 2024 at 04:52:34PM +0530, Balasubramani Vivekanandan wrote:
> From: Clint Taylor
>
> Add Xe2_HPD specific CDCLK table and use MTL Funcs.
>
> Bspec: 65243
> Cc: Matt Roper
> CC: Lucas De Marchi
> Signed-off-by: Clint Taylor
> Signed-off-by:
ux CCS and the Flat CCS is enabled via PAT
> + */
> + if ((DISPLAY_VER(i915) >= 20) || IS_BATTLEMAGE(i915))
> + return false;
> +
> + if (HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
> + retur
imply
that i915 had Battlemage support previously.
Otherwise,
Reviewed-by: Matt Roper
Matt
> building i915 code. We should make sure the macro parameter is used in
> the always-false expression so that we don't run into "unused variable"
> warnings from i915
On Wed, Apr 03, 2024 at 04:52:31PM +0530, Balasubramani Vivekanandan wrote:
> Common display code requires IS_BATTLEMAGE macro. Defined the macro.
>
> Signed-off-by: Balasubramani Vivekanandan
>
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/xe/compat-i915-headers/i91
c)
> +#define GEN8_DE_RM_TIMEOUT REG_BIT(29)
Given that this was first introduced in Xe_LPD+, the "GEN8" prefix here
is inappropriate.
Matt
> #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> #define GEN8_DE_MISC_GSEREG_BIT(27)
> #define GEN8_DE_EDP_PSR REG_BIT(19)
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
nd the first.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> Acked-by: Michal Mrozek
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c |
nd the first.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> Acked-by: Michal Mrozek
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c |
3]: https://gitlab.freedesktop.org/drm/intel/issues/8293
> [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
>
>
> Build changes
> -
>
> * Linux: CI_DRM_14489 -> Patchwork_131625v1
>
> CI-20190529: 20190529
> CI_DRM_14489: f9c56f1a03b5c35488671e4ffe61e28b12ffe163 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7785: 7785
> Patchwork_131625v1: f9c56f1a03b5c35488671e4ffe61e28b12ffe163 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> a50860ce8e96 drm/i915: Add new PCI IDs to DG2 platform in driver
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131625v1/index.html
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Tue, Mar 26, 2024 at 07:42:34PM +0100, Andi Shyti wrote:
> Hi Matt,
>
> On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> > On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > > + /*
> > > + * Do not cr
On Tue, Mar 26, 2024 at 07:42:34PM +0100, Andi Shyti wrote:
> Hi Matt,
>
> On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> > On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > > + /*
> > > + * Do not cr
On Tue, Mar 26, 2024 at 04:02:41PM +0530, Ravi Kumar Vodapalli wrote:
> New PCI IDs are added in Bspec for DG2 platform, add them in driver
>
> Bspec: 44477
> Signed-off-by: Ravi Kumar Vodapalli
Reviewed-by: Matt Roper
> ---
> include/drm/i915_pciids.h | 4 +++-
&g
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
Reviewed-
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
Reviewed-
nd the first.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20
nd the first.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20
On Mon, Mar 18, 2024 at 02:00:25PM -0700, Radhakrishna Sripada wrote:
> Disable clockgating for TDL SVHS fub.
>
> v2: Implement in general render/compute wa's(MattR)
>
> Bspec: 46045
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
Reviewed-by: Matt Roper
> ---
On Mon, Mar 18, 2024 at 12:35:58PM -0700, Radhakrishna Sripada wrote:
> Disable clockgating for TDL SVHS fub.
>
> Bspec: 46045
> Cc: Matt Roper
> Signed-off-by: Radhakrishna Sripada
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt
On Tue, Mar 12, 2024 at 04:43:06PM -0700, John Harrison wrote:
> On 3/12/2024 09:24, Matt Roper wrote:
> > On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > An existing workaround has been
On Tue, Mar 12, 2024 at 04:43:06PM -0700, John Harrison wrote:
> On 3/12/2024 09:24, Matt Roper wrote:
> > On Thu, Mar 07, 2024 at 06:01:29PM -0800, john.c.harri...@intel.com wrote:
> > > From: John Harrison
> > >
> > > An existing workaround has been
> engine->instance)
> engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
Given that we expect all i915 platforms to have a render engine now, we
could simplify this down to just
if (engine->class == RENDER)
engine->flags |= I915_ENGINE_FIRST
ersions from the _FEATURES macros. Since that was the
> only use for XE_HPM_FEATURES, remove it completely.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_pci.c | 12
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
&g
On Tue, Mar 12, 2024 at 04:51:41PM -0700, Lucas De Marchi wrote:
> Now that DG2 is the only user of this forcewake table, remove the macro
> and use FORCEWAKE_RENDER explicitly for range 0xd800 - 0xd87f.
>
> Suggested-by: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed
ryushin
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++---
> drivers/gpu/drm/i915/intel_clock_gating.c | 4 ++--
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/driv
ryushin
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++---
> drivers/gpu/drm/i915/intel_clock_gating.c | 4 ++--
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/driv
n12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */
> \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
>
n12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */
> \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
>
load-balancing disable hasn't landed in i915 yet (although it
probably will soon). Assuming we wait for that to happen first before
applying this,
Reviewed-by: Matt Roper
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
> drivers/gpu/drm/i915/gt/uc/
load-balancing disable hasn't landed in i915 yet (although it
probably will soon). Assuming we wait for that to happen first before
applying this,
Reviewed-by: Matt Roper
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-
> drivers/gpu/drm/i915/gt/uc/
_UABI_CLASS)
> + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
> continue;
>
> + GEM_BUG_ON(uabi_class >=
> +ARRAY_SIZE(i915->engine_uabi_class_count));
> + i915->engine_uabi_class_count[uabi_class]++;
> +
> rb_link_node(>uabi_node, prev, p);
> rb_insert_color(>uabi_node, >uabi_engines);
>
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
_UABI_CLASS)
> + if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
> continue;
>
> + GEM_BUG_ON(uabi_class >=
> +ARRAY_SIZE(i915->engine_uabi_class_count));
> + i915->engine_uabi_class_count[uabi_class]++;
> +
> rb_link_node(>uabi_node, prev, p);
> rb_insert_color(>uabi_node, >uabi_engines);
>
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++--
> 2 files changed, 22 insertions(
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++--
> 2 files changed, 22 insertions(
is already done, but the logic will need
> >to know the ratio to properly update the registers.
> >
> >v2:
> > - Make first sentence of commit message more intelligible. (Matt)
> >
> >Reviewed-by: Matt Roper
> >Signed-off-by: Gustavo Sousa
> >---
here since that's where we find out that Xe2
and beyond should always use the CDCLK PLL as the MDCLK source (rather
than the CD2X which would still be the register field's default value if
we didn't touch it).
Reviewed-by: Matt Roper
> Cc: Matt Roper
> Signed-off-by: Gustavo Sousa
> ---
>
> + guc_waklv_enable_simple(guc, , ,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
> + guc_waklv_enable_simple(guc, , ,
> +
> GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
> }
>
> size = guc_ads_waklv_size(guc) - remain;
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
> + guc_waklv_enable_simple(guc, , ,
> + GUC_WORKAROUND_KLV_SERIALIZED_RA_MODE);
> + guc_waklv_enable_simple(guc, , ,
> +
> GUC_WORKAROUND_KLV_AVOID_GFX_CLEAR_WHILE_ACTIVE);
> }
>
> size = guc_ads_waklv_size(guc) - remain;
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Requires: 97aba5e46038 ("drm/i915/gt: Refactor uabi engine class/instance
> list creation")
> Signed-off-by: Andi Shyti
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Requires: 97aba5e46038 ("drm/i915/gt: Refactor uabi engine class/instance
> list creation")
> Signed-off-by: Andi Shyti
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> 2 files changed, 6 insertions(+)
>
>
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
> 2 files changed, 6 insertions(+)
>
>
ction.
> + */
> + if (!(engine->gt->info.engine_mask &
> + BIT(_CCS(engine->uabi_instance
> + continue;
> +
> GEM_BUG_ON(uabi_class >=
> ARRAY_SIZE(i915-&g
ction.
> + */
> + if (!(engine->gt->info.engine_mask &
> + BIT(_CCS(engine->uabi_instance
> + continue;
> +
> GEM_BUG_ON(uabi_class >=
> ARRAY_SIZE(i915-&g
On Mon, Mar 04, 2024 at 03:30:24PM -0300, Gustavo Sousa wrote:
> CDCLK programming Xe2LPD always selects the CDCLK PLL as source for the
I think something got a bit muddled while rewriting this sentence.
Maybe the first two words were supposed to be dropped?
Otherwise,
Reviewed-by: Matt Ro
ratio, extract the
> function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic
> and call it using 2 as hardcoded ratio. Upcoming changes will use that
> function for updates in the ratio due to CDCLK changes.
>
> Bspec: 50057, 69445, 49213, 68868
> Signed-off-by: Gustavo So
could also move the 'u32 waveform' declaration from the top of the
function inside the block too to help prevent any future mistakes of
using it unitialized.
Either way,
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++--
> 1 file changed, 3 in
#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
> #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> #define BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> #define BXT_CDCLK_CD2X_DIV_SEL_1_5
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> --
> 2.44.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Mon, Mar 04, 2024 at 03:30:20PM -0300, Gustavo Sousa wrote:
> The CDCLK table is tied to Xe2LPD display and not to the platform. Let's
> rename lnl_cdclk_table to xe2lpd_cdclk_table in order to reflect that.
>
> Signed-off-by: Gustavo Sousa
Reviewed-by: Matt Roper
> ---
>
On Thu, Feb 22, 2024 at 05:23:47AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/cdclk: Document CDCLK components (rev2)
> URL : https://patchwork.freedesktop.org/series/130016/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_14311_full ->
On Mon, Feb 19, 2024 at 08:30:00PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/cdclk: Rename intel_cdclk_needs_modeset to
> intel_cdclk_clock_changed (rev2)
> URL : https://patchwork.freedesktop.org/series/129908/
> State : failure
>
> == Summary ==
>
> CI Bug Log -
from media team thus not applying
> WA on media engines. We will revisit if any issues reported
> from media team.
>
> V2(Matt):
> - Use correct WA number
>
> Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641")
> Signed-off-by: Tejas Upadhyay
R
On Thu, Feb 22, 2024 at 11:03:27PM +0100, Andi Shyti wrote:
> Hi Matt,
>
> first of all thanks a lot for the observations you are raising.
>
> On Wed, Feb 21, 2024 at 12:51:04PM -0800, Matt Roper wrote:
> > On Wed, Feb 21, 2024 at 01:12:18AM +0100, Andi Shyti wrote:
>
On Thu, Feb 22, 2024 at 11:03:27PM +0100, Andi Shyti wrote:
> Hi Matt,
>
> first of all thanks a lot for the observations you are raising.
>
> On Wed, Feb 21, 2024 at 12:51:04PM -0800, Matt Roper wrote:
> > On Wed, Feb 21, 2024 at 01:12:18AM +0100, Andi Shyti wrote:
>
l)
> {
> - /* Wa_14018575942 / Wa_18018781329 */
> + /* Wa_14018575942 / Wa_14018778641 / Wa_18018781329 */
> + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> /* Wa_22016670082 */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Wed, Feb 21, 2024 at 01:12:18AM +0100, Andi Shyti wrote:
> Hi Matt,
>
> thanks a lot for looking into this.
>
> On Tue, Feb 20, 2024 at 03:39:18PM -0800, Matt Roper wrote:
> > On Tue, Feb 20, 2024 at 03:35:26PM +0100, Andi Shyti wrote:
>
> [...]
>
> > &g
On Wed, Feb 21, 2024 at 01:12:18AM +0100, Andi Shyti wrote:
> Hi Matt,
>
> thanks a lot for looking into this.
>
> On Tue, Feb 20, 2024 at 03:39:18PM -0800, Matt Roper wrote:
> > On Tue, Feb 20, 2024 at 03:35:26PM +0100, Andi Shyti wrote:
>
> [...]
>
> > &g
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/
irst
> instance.
>
> This change can be tested with igt i915_query.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> 2 files changed, 7 insertions(+)
>
>
t;)
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++
> 2 files changed, 7 insertions(+)
>
>
series.
Matt
> platforms.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_
series.
Matt
> platforms.
>
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matt Roper
> Cc: # v6.2+
> ---
> drivers/gpu/drm/i915/gt/intel_
), \
> > - INTEL_VGA_DEVICE(0x46D2, info)
> > + INTEL_VGA_DEVICE(0x46D2, info), \
> > + INTEL_VGA_DEVICE(0x46D3, info), \
> > + INTEL_VGA_DEVICE(0x46D4, info)
> >
> > /* RPL-S */
> > #define INTEL_RPLS_IDS(info) \
> > --
> > 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
On Wed, Feb 14, 2024 at 10:50:20AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: update pll values in sync with Bspec for MTL (rev2)
> URL : https://patchwork.freedesktop.org/series/129878/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
_max_link_rate_reserved:5; /* 216+ */
> + u8 efp_index; /* 256+ */
> } __packed;
>
> struct bdb_general_definitions {
> --
> 2.39.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
DMA_RESV_USAGE_BOOKKEEP);
>
> - if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm)
> - dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence,
> + if (!xe_vma_has_no_bo(vma) && !bo->vm)
> +
as those bits are not meant to be
> modified outside of the port initialization. Rather propagate the
> additional bit in DDI_BUF_CTL to be set when that register is
> written again after D2D is enabled.
>
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
Reviewed-b
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