Hi Nilan,
You'd need to look at the interface firmware to see exactly how the clock
is generated on the FPGA, but essentially, yes, the 240 mhz clock is
derived by dividing down the clock the ADC chip passes to the FPGA (which
may or may not be equal to the sampling rate, depending on the exact
With regards to the demux option, for the system you describe you want -d 2
(I.e. demux by = run the FPGA at half the sample rate, and process two
samples in parallel on every FPGA clock cycle). Basically, provided you
have the up to date ruby package, all you need to do is run adc16_init.rb
with
Hi Vishwa,
I am not at my computer right now, so this is from memory, but I think you want
to specify an IP clock rate of 240 MHz and supply a 480 MHz clock to the ADC
card(s). The IP clock rate is sometimes called the fabric clock rate. It is the
rate at which the FPGA logic elements (aka
Hi David/Jack,
We are working on a beam former and we use the 'ADC16x250-8 coax rev 2' to
sample RF signals using ROACH2-Rev 2. The operating BW is 240MHz. Thus, we
need to sample the signals at 480 MSamples/s. We have few queries regarding
the adc16 yellow block and how to setup the input clock.
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