Re: [casper] state of the art single bit correlators

Hi Neil, Dan, That would be the thesis of the brilliant Curtis Mead, downloadable here: https://dash.harvard.edu/handle/1/11158246 Jono > On Nov 13, 2023, at 8:56 AM, Dan Werthimer wrote: > > > hi neil, > > paul horowitz, at harvard, had a PhD student who characterized and used FPGA >

[casper] save the Holmdel CMB Horn

Dear CASPERites, Is this the first request to sign a petition sent to this exploder? It’s relevant to what we do: Please, CASPERites, consider signing, and forward to others. There is a great short video explaining the horn’s historical relevance, featuring a very enthusiastic founding

Re: [casper] Ethernet speed interoperability

Thanks also for this information, Greg, also helps and I very much appreciate it. Best wishes, Jonathan > On Nov 30, 2022, at 7:16 PM, Greg Lindahl wrote: > > Jono, > > The secret is that none of this autonegotiates. You have to set the > link speed and the link width explicitly on the

Re: [casper] Ethernet speed interoperability

Hi Jack, Thanks for weighing in. Actually your answer doesn’t read as the same one that Mitch gave. Further clarification: > On Nov 30, 2022, at 3:08 PM, Jack Hickish wrote: > > Yes, I think that's probably right. There are old standards which probably > allow you to passively convert a

Re: [casper] Ethernet speed interoperability

route if interested? But it is old technology and > probably hard to come by? > > Best, > > Mitch > >> On Nov 30, 2022, at 9:09 AM, 'Jonathan Weintroub' via >> casper@lists.berkeley.edu wrote: >> >> Hi CASPERites, >> >> I believe that 40 G

[casper] Ethernet speed interoperability interoperability

Hi CASPERites, I believe that 40 Gbps Ethernet interoperates rather transparently with 10 Gbps. Because the 40 Gbps is arranged as four x 10 G lanes, so its possibly to break a 40 QSFP port into four 10 SFP+ with a suitable breakout cable. Or with proper packet addressing via a network

Re: [casper] RA Instruments using CASPER hardware and tools

Ciao Morag, It is not a full CASPER instrument, so maybe a marginal case: the ALMA Phasing System (APS) is a retrofit of a VLBI beam forming capability to the non-VLBI capable ALMA Correlator,

Re: [casper] viability of VCU128 eval board as production CASPER instrument

e put the HiTech Global HTG940 and HTG9200 boards into the CASPER >> library if either of those was useful. >> >> I would definitely recommend looking at Alpha Data as well - I've had good >> experiences with them so far, and I've recently put the ADA-SDEV-3 into &g

[casper] viability of VCU128 eval board as production CASPER instrument

Hi CASPERites, At SAO we’ve been developing high performance instruments based on the Xilinx VCU128 evaluation board and the Adsantec ASNT7123A 16 GS/s 4-bit direct flash ADC.

[casper] truly spectacular!

https://arxiv.org/pdf/2201.10541.pdf https://www.nytimes.com/2022/01/31/science/milky-way.html?auth=login-email=email Well done SARAO and CASPER and all involved.