[casper] capser_xps Cannot find any compiled XSG netlist

2013-07-08 Thread Haoxuan Zheng
Hi Casper, I started getting this strange casper_xps fail yesterday: XSG generation complete. # ## Copying base system ## # source_dir = /mnt/data0/omniscope/programs/mlib_devel/xps_base/XPS_ROACH2_base Copying base package from:

Re: [casper] capser_xps Cannot find any compiled XSG netlist

2013-07-08 Thread Haoxuan Zheng
Thanks a lot Ryan! It was precisely the capitalized letter in my file name that caused the problems! Jeff From: Ryan Monroe [ryan.m.mon...@gmail.com] Sent: Monday, July 08, 2013 2:09 PM To: Haoxuan Zheng Cc: casper@lists.berkeley.edu; Jonathan L Losh; Nevada J

[casper] How to avoid design placement/implementation in casper_xps command

2013-07-01 Thread Haoxuan Zheng
Hi Casper, [Question]: Is there a way to ask casper_xps to finish synthesized design and stop there (meaning not to attempt placement), and I take over in PlanAhead? This will save me a few hours each run. I checked the casper wiki for casper_xps but I'm not sure which step corresponds to

Re: [casper] Python katcp cannot connect FPGA

2013-05-21 Thread Haoxuan Zheng
. Thanks a lot! Jeff From: David MacMahon [dav...@berkeley.edu] on behalf of David MacMahon [dav...@astro.berkeley.edu] Sent: Tuesday, May 21, 2013 4:56 PM To: Haoxuan Zheng Cc: casper@lists.berkeley.edu Subject: Re: [casper] Python katcp cannot connect FPGA

Re: [casper] Python katcp cannot connect FPGA

2013-05-21 Thread Haoxuan Zheng
Hi Andy, Here are the tidied up versions. Thank you so much! Jeff From: aml...@gmail.com [aml...@gmail.com] on behalf of Andrew Lutomirski [l...@mit.edu] Sent: Tuesday, May 21, 2013 5:54 PM To: Haoxuan Zheng Cc: David MacMahon; casper@lists.berkeley.edu

Re: [casper] Python katcp cannot connect FPGA

2013-05-21 Thread Haoxuan Zheng
From: casper-boun...@lists.berkeley.edu [casper-boun...@lists.berkeley.edu] on behalf of Haoxuan Zheng [jef...@mit.edu] Sent: Monday, May 20, 2013 12:01 PM To: casper@lists.berkeley.edu Subject: [casper] Python katcp cannot connect FPGA Hi CASPER, Sorry for the spam

[casper] Python katcp cannot connect FPGA

2013-05-20 Thread Haoxuan Zheng
Hi CASPER, Sorry for the spam, but since my original message was sent at the worst hour of the week (Friday evening), I would like to give it another try: Our lab just got a new server which will be our data taking computer, and it has trouble connecting to our ROACH 2 through python katcp.

[casper] Python katcp cannot connect FPGA

2013-05-18 Thread Haoxuan Zheng
Hi CASPER, Our lab just got a new server which will be our data taking computer, and it has trouble connecting to our ROACH 2 through python katcp. Whenever I do fpga = corr.katcp_wrapper.FpgaClient('10.0.0.200', 7147, timeout = 60), fpga.is_connected() always say False. Here's some clues: 1)

[casper] PlanAhead 14.2 help

2013-04-30 Thread Haoxuan Zheng
Hi CASPER, We would like to use PlanAhead to help achieve timing closure in our latest design where the failed route has 80% routing time. However the PlanAhead software we have is version 14.2, which looks significantly different from the example on CASPERwiki,

Re: [casper] ERROR:Xflow - map: application received signal 9

2013-04-01 Thread Haoxuan Zheng
system.make bits. Error using gen_xps_files (line 640) XPS failed. Thank you so much for any inputs! Jeff From: casper-boun...@lists.berkeley.edu [casper-boun...@lists.berkeley.edu] on behalf of Haoxuan Zheng [jef...@mit.edu] Sent: Sunday, March 31, 2013 11:45 PM

Re: [casper] ERROR:Xflow - map: application received signal 9

2013-04-01 Thread Haoxuan Zheng
From: Ross Williamson [rwilliam...@astro.caltech.edu] Sent: Monday, April 01, 2013 3:28 AM To: Haoxuan Zheng Cc: casper@lists.berkeley.edu; Jonathan L Losh; sanchez.nev...@gmail.com Subject: Re: [casper] ERROR:Xflow - map: application received signal 9 Sig 9 can

[casper] ERROR:Xflow - map: application received signal 9

2013-03-31 Thread Haoxuan Zheng
Hi Casper, I have been getting the following error when running casper_xps compilation (see bold part towards the end). I am running Xilinx ISE 14.2 on Matlab 2012a on Ubuntu 11.10. Any thoughts or suggestions would be greatly appreciated! #--# #

Re: [casper] debugging communication with one_GbE from roach-2 's fpga

2013-01-21 Thread Haoxuan Zheng
Hi Casper group, We managed to take the FPGA 1GBE on ROACH2 fully under control, great thanks to John, Marc, Danny, Jack, and Jason! Wireshark was extremely helpful, as it can see packets as long as the receiver's IP is set correctly. For python grabbing to work, it turned out that we simply