Re: [casper] Help with packing data

2021-11-26 Thread Andrew van der Byl
Hi Heystek, You can pre-compute the sinusoid values and only write the 1st quarter to BRAM. To 'lookup' values simply read out the BRAM linearly. You could use a counter as an address generator. Keep in mind that the address space of the BRAM (and counter) represents only 1/4 of the waveform so

Re: [casper] Help with packing data

2021-11-26 Thread Heystek Grobler
Hey Andrew Yes, you read correctly, it is 602 million data points. I perhaps thought that I might had to shorten the amount of data points. I played around and the bram can comfortably handle 6020 data points and that still gives me a decent sine wave if I plot it. I would I implement a

Re: [casper] Help with packing data

2021-11-26 Thread Andrew Martens
Hey Heystek I would recommend trying to figure out how to do your tests without needing so many data points. Cheers On Fri, Nov 26, 2021 at 3:49 PM Heystek Grobler wrote: > Hey Andrew > > Thank you so much for the explanation. > > Is there a way to get around it by using a similar kind of

Re: [casper] Help with packing data

2021-11-26 Thread Andrew van der Byl
Hi Heystek, It's a Friday afternoon so perhaps my eyes are deceiving me, but it looks like you are wanting to store 602 million data points in BRAM? don't think you are going to have too much luck with that. You could generate a relatively fine grained cosine wave and only store the first 1/4

Re: [casper] Help with packing data

2021-11-26 Thread Heystek Grobler
Hey Andrew Thank you so much for the explanation. Is there a way to get around it by using a similar kind of block? Or should I rethink the sine wave that I generated that makes use of 602 000 000 data points? Thanks for the help! Heystek > On 26 Nov 2021, at 15:46, Andrew Martens

Re: [casper] Help with packing data

2021-11-26 Thread Andrew Martens
Hi Heystek Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit address size would equate to 4G addresses, which is far larger than the amount of BRAM available in the FPGA. Regards Andrew On Fri, Nov 26, 2021 at 3:40 PM Heystek Grobler wrote: > Hey everyone. > > I have

Re: [casper] Help with packing data

2021-11-26 Thread Heystek Grobler
Hey everyone. I have one last question regarding the BRAM. For my application I need an address width of 32, but I get the error that the maximum allowable address width is 16. Is there away around this problem or a way to get the BRAM to use an address width of 32? Thanks for the help!

Re: [casper] Help with packing data

2021-11-25 Thread Morag Brown
Hi Heystek, You would need to increase the BRAM depth to one that can store all your data - currently, because the address width is 10, it can only store 2^10 (1024) points and you're trying to write 6020. So you would need to increase the address width to an appropriate size. Morag On Thu, Nov

Re: [casper] Help with packing data

2021-11-25 Thread Heystek Grobler
Hey Morag The BRAM has an address width 10 and a data width of 32. Should I increase it? Heystek > On 25 Nov 2021, at 19:52, Morag Brown wrote: > > Hi Heystek, > > How big is the BRAM in your design? Does it have enough space to accommodate > the amount of data you're trying to write to