Hello,
After trying to reconfigure the flash memory on the Virtex7 FPGA with a new
image, I am no longer able to connect to the SKARAB through casperfpga
using the 1GigE port. When I enter the command fpga =
casperfpga.SkarabFpga('169.254.128.213'), the following is output.
Hi Mark,
Firstly, welcome to the CASPER community.
The SKARAB has multiple images stored in Flash. These are meant only used
for the initial FPGA image at start up and a fall back image. This is a
Xilinx standard method of configuration. You should be using the
upload_to_ram_and_program
Hi Mark,
I assume you were loading the latest BSP images to your SKARAB? Further to
what Wesley said, please can you also indicate the following:
1) Did you reprogramme both the multiboot and golden flash images?
2) Did you use the *.hex or *.bin file that was in the repo?
3) Is it possible
Hi Wes and other SKARAB experts,
To my understanding our SKARAB is now "bricked" and no longer responds on
Ethernet at all. We now need a way to bring it back to life from a straight
off the factory floor state. We surmise this involves JTAG and while there
is a tantalizing mention of this
Hi Jonathan and Mark,
Yes, JTAG is the way. Okay, I have done this before. This is what needs to
be done and I am going via memory here - will confirm when I am in the
office tomorrow:
1) Remove the SKARAB lid
2) This is TBC, but you will need to short the jumper on P9 (schematic page
42),
Hi Adam,
Ok thanks. I found a Xilinx Platform USB pod in anticipation of this need
before leaving the office. I still need to locate the fly lead cables.
For this reason alone this needs to wait till tomorrow. It's also very
late for you so I feel badly keeping you up.
The package of
Hi Jonathan and Mark,
Thanks for the feedback. The documentation is a work in progress, so
feedback is important.
I will certainly add a How To on configuring the SKARAB via the JTAG and we
are/will be working on a user manual for casperfpga.
The schematics are part of the "Peralex
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