Hi Laura
I had a look at the xco coregen file for TX Fifo when the Enable Large Tx
Frames option is used (8K Packets). The size of the FIFO seems to be only
64 deep!?
I will investigate further...
HK
On Wed, May 30, 2012 at 1:45 AM, Laura Vertatschitsch verta...@gmail.comwrote:
Hey guys,
Yes, you've got the right definition. And Laura's correct in that some ROACHes
shipped with old versions. I've appended the original email to the mailing list
below for your reference.
All the software is available on SKA-SA's github account, so you can get it
even when CASPER's server is
Hi Bill,
Not quite yet, but we are working on a board that could do 2.2 GSPS
non-interleaved. It is called the adc1x2200-10 which indicates 1 channel,
10 bits, 2200 MSPS. It is based on the e2v AT84AS008 part with associated
DMUX and the status is that we have a PCB design, PCB's and components
Hi Bill,
Can you clarify: when you say you need an ADC clocked at 2048 MHz do you mean
a sampling rate of 4096 MS/s or 2048 MS/s? (The ADC sample rate for some parts
is twice the clock rate.) I'm a bit confused as to what you are after, looking
back at your original framing of your problem,
hi bill,
you asked about adc's with more than 8 bits:
beside the upcoming 10 bit adc from south africa,
discussed in earlier emails today, there's are
dual input 12 bit 550 Msps ADC board
dual input 14 bit 400 Msps ADC board
six input 12 bit 1000 Msps ADC board
the six input Gsps adc
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