[casper] seeking Roach 1 boards

Dear Casperites, My colleague Anton Tremsin (cc'ed), from the Berkeley's Experimental Astrophysics group at Space Sciences Laboratory, still uses Roach 1 boards with CX4 connectors in their detectors and would be very thankful if someone can donate/sell them decommissioned Roach 1 boards. Anton

Re: [casper] Red Pitaya Wide(-ish)band Spectrometer Tutorial

Hi Adam, Yes, I built the slx files and generated the fpg files for the first two tutorials. For the third tutorial, I first opened the slx file in Simulink and compiled it but got an error when I tried to upload and program. Then I tried updating the model as described under "Updating an

Re: [casper] Red Pitaya Wide(-ish)band Spectrometer Tutorial

Hi Paul, Thanks for your email. It looks like your mlib_devel and casperfpga version are fairly recent and contain the BRAM 32 bit fixes that we made. It seems I committed this particular fpg file 9 months ago, so it might not of contained all these fixes then. I am quite certain it was working

Re: [casper] Help with timing constraint

Hi Heystek Output reports and their location change over versions, between ISE and Vivado etc. I think the output reports for ISE are located in the 'implementation' folder. I think the timing related ones have 'timing' in the name... A quick Google search of the error will help. Note that there

Re: [casper] Help with timing constraint

Hi Heystek, It's possible that you then have another issue that causes the build process to exit prior to generating that file. You'll need to debug that first. Regards, Andrew On Wed, Aug 26, 2020 at 10:40 AM Heystek Grobler wrote: > Hey Andrew > > It is strange, I cant seem to locate

Re: [casper] Help with timing constraint

Hey Andrew It is strange, I cant seem to locate top_timing_summary_routed.rpt I am running Matlab 2012B with ISE 14.7 > On 26 Aug 2020, at 10:27, Andrew van der Byl wrote: > > Hi Heystek, > > 1) Navigate to your project folder > 2) Then go to and open: >

Re: [casper] Help with timing constraint

Hi Heystek, 1) Navigate to your project folder 2) Then go to and open: /myproj/myproj.runs/impl_1/ top_timing_summary_routed.rpt Just a note - this file is usually fairly large as text files go ~20MB. Regards, Andrew On Wed, Aug 26, 2020 at 10:22 AM Heystek Grobler wrote: > Hey James and

Re: [casper] Help with timing constraint

Hey James and Andrew Thank you so much for the advice! @Andrew, this might be a stupid question, but where do I locate the top_timing_summary_routed.rpt file? Heystek > On 26 Aug 2020, at 10:17, Andrew van der Byl wrote: > > Hi Heystek, > > Have a look in top_timing_summary_routed.rpt

Re: [casper] Help with timing constraint

Hi Heystek, Have a look in top_timing_summary_routed.rpt and search for 'VIOLATED' - this usually shows up which paths are hurting your design. Then, as James said, start pipeling your design. Hope this helps. Regards, Andrew On Wed, Aug 26, 2020 at 10:13 AM James Smith wrote: > Hello

Re: [casper] Help with timing constraint

Hello Heystek, You will have to go through the timing reports and see which signal path is failing timing, and by how much. Once you have an idea, you will need to sprinkle delay blocks and / or adjust latencies in your logic to get to a point where the place-and-route can find a layout that

[casper] Help with timing constraint

Good day everyone I am running a design but ran into this problem: xflow done! touch __xps/system_routed xilperl /opt/Xilinx_ISE/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par Analyzing implementation/system.par