Re: [casper] Compiling design

Hey Jack and Andrew You were right. I literarily had one “Gateway In” block. I removed it and now my design compiles. Thank you for your help! I really appreciate it. Heystek > On 11 Aug 2020, at 16:51, Jack Hickish wrote: > > Hi Heystek, > > Somewhere in your design -- presumably

Re: [casper] Compiling design

Hi Heystek I notice that you are using Xilinx Output Gateways leading to scopes, I would guess that there are Input Gateway/s as well. These will be linked to physical pins, or software interfaces, on the FPGA when compiled. If you want to access inputs linked to FPGA pins or software interfaces,

Re: [casper] Compiling design

Hi Heystek, Somewhere in your design -- presumably outside the screenshot you just sent or inside one of your blocks -- you have a "Gateway In" block. This isn't allowed (when you compile the design, the toolflow doesn't know what to drive it with). If you find and delete this block, I think

Re: [casper] Compiling design

Hey James Below is a snipped: > On 11 Aug 2020, at 15:24, James Smith wrote: > > Send a screen snip of what you've got, Heystek? > > On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler > wrote: > Hey James and Mugundhan > > Thank you for your emails. > >

Re: [casper] Compiling design

Send a screen snip of what you've got, Heystek? On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler wrote: > Hey James and Mugundhan > > Thank you for your emails. > > Yes, I have a Shared BRAM block in my design. The BRAM block is from the > casper blockset. So I should rather use something else

Re: [casper] Compiling design

Hey James and Mugundhan Thank you for your emails. Yes, I have a Shared BRAM block in my design. The BRAM block is from the casper blockset. So I should rather use something else for the design? > On 11 Aug 2020, at 15:03, James Smith wrote: > > Hello Heystek, > > Somewhere in your design,

Re: [casper] Compiling design

Hi Heystek, This is (probably) because the yellow blocks, when you look under the mask, already have gateway ins and outs. In conventional system generator, the gateways are ports for the design. Here, the tool flow takes care of this. Sincerely, Mugundhan On Tue, 11 Aug, 2020, 6:24 PM Heystek

Re: [casper] Compiling design

Hello Heystek, Somewhere in your design, you are trying to use a Xilinx block as an input. Replace it with one of the yellow blocks from the Casper tools, and you should be okay. (Usually this will be a software register or a BRAM block.) Regards, James On Tue, Aug 11, 2020 at 12:54 PM Heystek

[casper] Compiling design

Good day everyone I am compiling a design for Roach2. I can into this error when running casper_xps: "xilinx input gateways cannot be used in a design. Only gpio blocks” How can I solve this or am I doing something stupid? Thanks for the help Heystek -- You received this message because