Re: [casper] Clock signal question

I assume you're trying to clock an ADC, which will in turn clock the FPGA? Most CASPER ADCs and DACs need a 0dBm signal for the clock, but can usually accommodate a few dB around that figure. See for example: https://casper.berkeley.edu/wiki/ADC2x1000-8

[casper] Clock signal question

Hi everyone Does anyone know what is the best clock signal for a ROACH1 and ROACH2 board and will a sign wave do and at what level? Thanks for all the help Heystek -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe

Re: [casper] Help with PlanAhead

I actually didn't know that tool existed! I am trying to meet timing constraints, and I'm actually very close to do so, so I'm definitely gonna try smartxplorer. Thanks for the advise! Franco On 25/05/17 15:24, Michael D'Cruze wrote: Hi Franco, Just curious, but have you considered using

Re: [casper] Help with PlanAhead

Thanks for the feedback Jack! On 25/05/17 13:46, Jack Hickish wrote: Hi Franco, 1) Yes, this is an optimization the tools have performed. If you dig into the Xilinx manuals you can probably find some options / UCF entries to turn off this type of optimization, or at least make it less

Re: [casper] Clock signal question

Hello Heystek, On Thu, May 25, 2017 at 2:50 PM, Heystek Grobler wrote: > How does the gain work when pulling a spectrum out of the BRAMS? You're going to need to be a bit more specific. I'm not too sure what you're trying to do here. Regards, James -- You received

Re: [casper] Help with PlanAhead

Hi Franco, 1) Yes, this is an optimization the tools have performed. If you dig into the Xilinx manuals you can probably find some options / UCF entries to turn off this type of optimization, or at least make it less aggressive. I don't use these enough to know exactly which ones you want, but

Re: [casper] Clock signal question

We have used oscillators from EMResearch such as the SLFS series http://www.emresearch.com/product/slfs-series/ We've used 1400 MHz on ROACH1 (KATADC) and 2500 MHz on ROACH2 (ADC5G). John On Thu, May 25, 2017 at 6:00 AM, James Smith wrote: > Hello Heystek, > > On Thu, May

RE: [casper] Help with PlanAhead

Hi Franco, Just curious, but have you considered using SmartXplorer to assist in getting your design to meet timing, if this is the eventual goal? Usually I find that with a medium or large design, if I can adjust the latencies in Simulink to get within a timing score of, say, 1, then