[casper] Roach 10 GbE - Core configuration issue

Dear CASPERites, I'm running the 10GbE tutorial and am not getting any data transfered over the ethernet link. The python script successfully programs the FPGA and executes, but on running the script with the -a flag it would appear that the 10GbE cores aren't being configured. I am using the

[casper] 10.1 designs on BEE2

Hi all, I'm trying to retire an old 7.1 virtual machine to the digital grave that it deserves. I ported a BEE2 design to 10.1, and successfully compiled the relevant bof files for the BEE. Unfortunately, when I run the boffile, the BEE hangs. If I run the process in the background, I can see the

[casper] 64xADC

Hi CASPERites, I'm looking to cram as many input signals as possible into a ROACH, and notice that there is a link on the website for a 64 input ADC card. Unfortunately, this link doesn't go anywhere, and the sampling rate of the board is quoted as either 50 or 64 Msps depending on where you

[casper] Black Boxes with input buses over 32 bits wide

Hi all, I'm experimenting with some black boxed state machines to simplify some of the control logic in my designs. I thought I had it sussed, until I tried a black box with a 64 bit wide input bus. The HDL seems unable to see the top 32 bits of the input, and simulink refuses to recognise any of

Re: [casper] Black Boxes with input buses over 32 bits wide

and black boxing that also seemed to solve the problem. All mighty suspicious, but semi-solved, at least. Cheers, Jack On Mon, Apr 26, 2010 at 8:20 PM, Jack Hickish jackhick...@googlemail.comwrote: Hi all, I'm experimenting with some black boxed state machines to simplify some of the control logic

[casper] Correlator Loopback

And that folks, did not go to plan. :-(

Re: [casper] Multi-Clock domain design using CASPER

Regarding multirate support from the toolflow - the system generator token seems to have various options for multirate implementation (the default of which is clock enables). On reading the system generator help file, my take is that the hybrid DCM-CE mode will instantiate a DCM that can drive up

[casper] GPIO input/output select on ROACH

Hi all, I've been playing around with the GPIO on a ROACH, and just to ease my curiosity, can anyone tell me what the pins that are driven by the gpiox_oe_n blocks actually *do*? Anyone with an answer will surely save me many sleepless nights of idle wondering... Cheers, Jack

Re: [casper] GPIO input/output select on ROACH

are spread across different I/O banks, so they are all at different voltages. To make them all a uniform 3.3V, they go through unidirectional level translators; the gpiox_oe_n signals control the drive directions of these translators. Cheers, Henry On 8/27/2010 5:50 PM, Jack Hickish wrote: Hi

Re: [casper] Optimum PFB / FFT settings to meet timing

Hi, After a compile fails, it's worth checking the timing report in the compile directory /XPS_ROACH_BASE/implementation/system.twr Whilst a little bit cryptic, the report should at least give you some idea of which bits of the design are causing timing failure. It becomes reasonably clear if

Re: [casper] Simulink Problem

Hi, Have you tried the old 'set the clock pin location to d7' trick? See here: http://casper.berkeley.edu/astrobaki/index.php/CasperTutorial01 -- Section 2.1 Cheers, Jack On 3 September 2010 18:34, r...@physics.ucsb.edu wrote: I am sorry I didn't provide more detail. I have Matlab

Re: [casper] 10Gbe yellow block outside of subnet?

Hi Dave, I remember an issue with borph hanging on read/writes, which the mail archive suggests you may have solved. Could you just confirm -- does the current version of 10.1 in the git repo successfully create bof files that work with the BEE2? Cheers, Jack On 14 October 2010 12:09, David

Re: [casper] X-engine resource requirements

Hi Glenn, I noticed the same thing as you re. DSP use in the X-engine, and went about making a new complex multiply block which performs two 4x4 bit multiplies per DSP slice by concatenating inputs together, and therefore uses 2 DSPs per Cmult. This was pretty simple, though I suspect the adders

Re: [casper] Starting tut1

Hi Miguel, I think the General ROACH Instructions that you're reading were written specifically for the CASPER workshop in Harvard last year, where there were some servers / ROACHs already set up. If you're trying to run your design on a ROACH in your own setup, a few of the details may be

Re: [casper] Fwd: trouble compiling tutorial 1

Hi Louis, The error you describe sounds similar to that encountered when trying to compile on Ubuntu -- see here: http://www.mail-archive.com/casper@lists.berkeley.edu/msg01224.html Are you using Centos/RHEL/one of the supported OSs? Cheers, Jack On 13 July 2011 23:10, Louis Dartez

Re: [casper] Black Boxes with input buses over 32 bits wide

Hi All, Just a quick update on this issue which I discovered about a year ago. It would seem that black-boxed verilog inputs over 32 bits wide work fine in System Generator 13.2. I hope this brings some others as much joy as it brings me. Cheers, Jack On 28 April 2010 16:57, Jack Hickish

Re: [casper] Question regarding Roach SMA

Hi Nimish, Is there a chance that your toolflow is not set up with the new pin mapping, mentioned in the bottom of the GPIO page. If you're on the old mapping then I guess the SMAs will map to GPIOs 4 and 5. Might be worth checking to see if your pulse which should be on 7 is coming out on 4. I

Re: [casper] Regarding 64ADCx64-12 yellow block

Hi Srikanth, You can find it in the xps_library at: http://www-astro.physics.ox.ac.uk/~FosterG/casper/oxford_devel.git which is the Oxford repo (and includes relatively recent pulls from all the public mlib_devel branches at various institutions. I'll try and get the block included in the github

Re: [casper] how to compile for '-2' chips?

Hey Ricardo, Can't say I've tried, but it looks like changing (or adding a new case) to mlib_devel/xps_library/xps_xsg_conf_mask.m should achieve what you want. The sx95t speed grade looks to be set on line 93. Cheers, Jack On 12 April 2012 23:49, Ricardo Finger rfing...@gmail.com wrote:

Re: [casper] Matlab crashes with tutorial 3

Hi all, After a fair bit of tutorial related pain on the mailist recently, I've just forked the tutorial-devel repo to https://github.com/jack-h/tutorials_devel and recompiled tutorials 1-3 with Sysgen 11.5 and the libraries in the main casper github repo. The tutorials in the 2011 directory

Re: [casper] Matlab crashes with tutorial 3

into this. Best Regards Gopal On 05/09/2012 03:58 PM, Jack Hickish wrote: Hi all, After a fair bit of tutorial related pain on the mailist recently, I've just forked the tutorial-devel repo to https://github.com/jack-h/tutorials_devel and recompiled tutorials 1-3 with Sysgen 11.5

Re: [casper] Matlab crashes with tutorial 3

On 11 May 2012 03:07, Gopal Narayanan go...@astro.umass.edu wrote: Hi Jack, All is well now. I indeed had placed the pcore files in the wrong directory, one above the required pcores subdirectory. Now it compiles all the way through. My mistake! Thanks a lot for your help. Best Regards,

Re: [casper] Treating SMA clock inputs as inputs

Hi Devon, You should be able to (at least in the latest casper libs) access aux0_clk and aux1_clk with the GPIO yellow block, though I can't say I've actually ever used this functionality. No reason to expect it won't just do what it says on the tin, though :-) Cheers, Jack On 15 June 2012

Re: [casper] Question about code from CASPER tutorial 4

Hi Alexander, On 20 July 2012 00:21, Alexander Mouschovias a...@caltech.edu wrote: Hi guys, I'm working with tutorial 4 from the 2011 workshop (available at https://github.com/jack-h/tutorials_devel). In the get_data function from poco_plot_cross.py, it seems to me that a_0r=b_0r,

Re: [casper] writing/reading qdr

Hi Matt, Looking at your model, you have write enable pulses coinciding with every second address location. Even though a write enable pulse writes two 36 bit values, each address location addresses a full 72 bit data burst, so if you want to write the entire qdr you need to increment the address

Re: [casper] Problem with Tutorial 3

Hi All, On 17 September 2012 09:34, Jason Manley jman...@ska.ac.za wrote: It does seem odd that this happens every X accumulations. That almost sounds like a problem with the readout software. There's nothing I can think of in the design that changes on those timescales, unless there is a

Re: [casper] Problem with Tutorial 3

I've just pushed a fix (and boffile) to the tutorials-devel git repo On 17 September 2012 13:03, Jason Manley jman...@ska.ac.za wrote: On 17 Sep 2012, at 11:45, Jack Hickish wrote: 2^27 isn't a valid sync period for tut3, which has an FFT ending in a 10th order reorder (https

Re: [casper] Problem with Tutorial 3

I'll dive into this and try to figure out what's going on, but extra eyes are appreciated. Thanks, Jason Castro NRAO On 9/17/2012 8:03 AM, Jason Manley wrote: On 17 Sep 2012, at 11:45, Jack Hickish wrote: 2^27 isn't a valid sync period for tut3, which has an FFT ending

Re: [casper] error sync_delay_en

Hi Katty, It seems there's a block not linking properly to your casper libraries. I'd suggest the first thing to try is just to delete the FFT blocks from your model and drop fresh ones back in from the CASPER library. Cheers, Jack On 9 November 2012 20:54, katherine viviana cortes urbina

Re: [casper] making a variant on an existing yellow block

I believe an initialization failure amounts to an error whilst running the block mask script. If you run the mask script manually on your new yellow block from the matlab command line, if it fails, it should at least tell you something useful. On 14 November 2012 09:59, Alex Zahn

Re: [casper] making a variant on an existing yellow block

trigger/XPS_ROACH_base/system.mhs line 279 - cannot find MPD for the pcore Any ideas? -Alex On Wed, Nov 14, 2012 at 3:54 AM, Jack Hickish jackhick...@gmail.comwrote: I believe an initialization failure amounts to an error whilst running the block mask script. If you run the mask script

Re: [casper] Get Python running on ROACH-2?

Hey Jeff, Ioana Probably worth mentioning that that python script mainly existed because the ROACH 1 didn't have access to a 100mb Ethernet connection except via the powerPC. ROACH 2 has a dedicated fpga-side 1000(?)mb/s interface. Depending on your application, you might consider using this for

Re: [casper] debugging communication with one_GbE from roach-2 's fpga

Hi Ioana, I'm attaching a model and python script that Guy Kenfack and I knocked together worked on at the Green Bank workshop. We sent a counter and saw the data at the right IP/port in wireshark. A question to anyone in the know: is there a runtime way to configure the source IP/mac settings

Re: [casper] debugging communication with one_GbE from roach-2 's fpga

Excellent. Thanks for the info. Jack On Jan 22, 2013 5:01 AM, Henno Kriel he...@ska.ac.za wrote: Hi The 1GbE core is configured to work in the same way as the 10GbE core with regards to tgtap. Regards Henno On Mon, Jan 21, 2013 at 3:52 PM, Marc Welz m...@ska.ac.za wrote: Hello A

Re: [casper] ROACH2 qdr3 and sfp conflict in core_info.tab

repository. I've left the full 64KB mapped for now. On 31 January 2013 17:24, David MacMahon dav...@astro.berkeley.edu wrote: Hi, Jack, Thanks for your helpful reply! On Jan 31, 2013, at 2:01 AM, Jack Hickish wrote: However, digging through the library, calibration flags (cal_fail and phy_ready

[casper] ROACH1 QDR size

Hi All, Is someone able to confirm that the size of the QDR chips on ROACH 1 boards depends solely on the board version? If this is indeed the case, does anyone know the QDR specs for the different board iterations? Cheers, Jack

Re: [casper] ROACH1 QDR size

, 2013, at 12:27 AM, Jack Hickish wrote: Hi All, Is someone able to confirm that the size of the QDR chips on ROACH 1 boards depends solely on the board version? If this is indeed the case, does anyone know the QDR specs for the different board iterations? Cheers, Jack

[casper] INFIERI Summer School, Oxford, July 10-16 2013

Hi All, In case it is of interest to any of you (or those you know), this July Oxford University will be hosting the first of a series of annual summer schools covering the complete signal processing chains found in 21st century scientific instrumentation. The series aims to be cross

[casper] DSP research position at Cambridge University

Hi all, Sorry to spam, but I thought this may be of interest to some of those on the maillist. Cambridge University are looking for a research associate in astronomical DSP. See the link below for details. http://www.mrao.cam.ac.uk/jobs/research-associate-in-digital-signal-processing/ Cheers,

Re: [casper] Simulation of tutorial3

Hi Ross, Have you looked upstream at, eg, the FFT output, to check there is a single spike coming out of that? Might also be worth making sure that you are simulating a sync pulse, and waiting long enough for data after the sync to propagate all the way through the design. Cheers, Jack On 15

Re: [casper] Fwd:connecting with .py this is register cnt_rst not found

Hey Katty, Laura If you produced this bof file from a Simulink model, you can look in the model to find the correct register. Alternatively, you can log into your roach and run your .bof file as an executable. When you see the process id, you can actually navigate to a folder that will

Re: [casper] QDR problems

Hullo, So first of all -- That appears to be my commit, so sorry. I'll fix it in the vanilla fork of the oxford github repo when i get into work this morning. FWIW, I believe core_info.tab on ROACH2 also has control addresses which are wrong. Or rather, are out of date now the ROACH2 QDR module

Re: [casper] QDR problems

blocks. FWIW, the qdrX_ctrl addresses were already updated a few months ago (there was an email thread about it iirc) but never propagated to casper-astro. Cheers, Jack On 4 June 2013 09:40, Jack Hickish jackhick...@gmail.com wrote: Hullo, So first of all -- That appears to be my commit, so sorry

Re: [casper] 64ADCx64-12 on a roach2

Hey David, The verilog for the yellow block is available but (as far as i know) untested on ROACH 2. The code / block is all available in https://github.com/oxfork/mlib_devel/ Feel free to improve it :-) Cheers, Jack On 5 June 2013 17:39, David Saroff dsar...@nrao.edu wrote: Does anyone

Re: [casper] 38 PFB's on a virtex-6?

On 10 June 2013 17:07, David Saroff dsar...@nrao.edu wrote: Short of compiling a design, can the resource usage of a PFB yellow block be seen? If the data rate is some submultiple of the FPGA clock, say 50 MSPS and 200 MHz is there a natural way to share resources? The question's context:

Re: [casper] building tutorial 3

Hey David, What libraries and tool versions are you using, and what error do you get? Cheers, Jack On 4 July 2013 21:00, David Saroff dsar...@nrao.edu wrote: Casper folks, A fresh copy of tut3.mdl from the wiki does not build, in the matlab/simulink/casper_xps setup given to me by our

Re: [casper] (no subject)

Hey Jeff, Quick and easy check -- have you the clock speed by looking at the DCM instantiation in system.mhs If you're using arb_clk to make 202MHz then the tools will find an integer multiplier and divisor to match close to your target speed. I don't know what the criteria for this selection is

Re: [casper] Possible CASPER workshop lecture topic

On 22 Jul 2013 18:00, John Ford jf...@nrao.edu wrote: Hi Rich, In hoping to get a yellow block tutorial up and running (there is a tutorial Dave George wrote a few years ago which I'll use as a starting point), probably based around a bidirectional gpio block. But if you (or anyone

Re: [casper] 64ADC64-12 on a roach1

Hi David, Just duplicating the email I sent you off list on the offchance it's useful to someone on the maillist in the future. My versions for the ADC64x64-12 (64 inputs, 64 MSa/s, 12 bits) are (https://casper.berkeley.edu/wiki/64ADCx64-12) (https://casper.berkeley.edu/wiki/X64_adc) MATLAB --

Re: [casper] casper libraries

Hi Tim, The ska-sa repo is *much* more up-to-date than the casper-astro repo, which still uses the old file naming conventions / directory structures. With the casper conference coming up in a couple of weeks, the tutorials are being updated to work with the ska-sa master branch. The official

Re: [casper] Matlab components for toolflow

, Jack Hickish jackhick...@gmail.comwrote: If you're really desperate, presumably someone on this list with a license can precompile the fft block for you, which you could then black box? Or generate the block, disable the init script, and send it to you? Not necessarily suggesting

Re: [casper] system.twx missing

Hey Andrea, I think (http://www.xilinx.com/support/answers/23165.html) the ngc file is all you're going to get, unless you run the compile again with the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. Your error is some specific component that has impossible timing constraints -- it's not just

[casper] ROACH2 XAUI

Hi all, I'm considering an application for ROACH2 which would require a load of point-to-point 10Gb/s connections. Has anyone got XAUI running on ROACH2 with either of the available mezzanine cards? If not, are there likely to be any major obstacles to getting this working? Cheers, Jack

Re: [casper] ROACH2 XAUI

Thanks, all, Food for thought... (I'm trying to weigh up the pros and cons of using a cheaper switchless correlator but having to make more custom firmware vs just using a switch and participating in mass IP theft from various CASPER github repos) Cheers, Jack On 6 November 2013 13:45, Andrew

[casper] Automated Floor Planning

Howdy, I've seen a few old documents (eg. https://casper.berkeley.edu/wiki/images/3/30/3ghz_spec_library_design.pdf) which suggest that somewhere there might exist an automated floor planner for some version of the CASPER FFT. Does such a marvellous thing actually exist in (partially?) working

Re: [casper] adc5g block run at 2500MHz

Hi all, Like Weiwei, I'm trying to use the ADC5g at 5 Gsps. I've played with a simple ADC to snap model, and (as Rurik warned) getting reliable data capturing is difficult at this speed. I've tried per-bit calibration of input data streams via IODELAYs in conjunction with phase-shifting of the

Re: [casper] adc5g block run at 2500MHz

, Jack Hickish jackhick...@gmail.com wrote: Hi all, Like Weiwei, I'm trying to use the ADC5g at 5 Gsps. I've played with a simple ADC to snap model, and (as Rurik warned) getting reliable data capturing is difficult at this speed. I've tried per-bit calibration of input data streams via IODELAYs

Re: [casper] adc5g block run at 2500MHz

, YMMV :) Cheers, Jack Thanks! Rurik On Wed, Jan 15, 2014 at 7:51 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Ross, Thanks for the info -- I've actually got a 5 Gsps ROACH2 (demux 1:1) pocket correlator compiled, and the final piece of the puzzle was getting the ADCs running properly

Re: [casper] adc5g block run at 2500MHz

for my project. Thanks! Best, Weiwei On Wed, Jan 15, 2014 at 9:53 AM, Jack Hickish jackhick...@gmail.com wrote: On 15 January 2014 16:28, Primiani, Rurik rprimi...@cfa.harvard.edu wrote: Hi Jack, Great work! The oversample mode is not something I realized existed! Me neither -- I

[casper] Simulink Log Comments prompt

Hi all, I expect many of you know about and may be using this feature, but every time you save a model, Simulink can be configured to prompt you to enter a changelog comment. See http://www.mathworks.co.uk/help/simulink/ug/managing-model-versions.html#f4-140406 for details On the off chance

Re: [casper] Timing errors and subsystems

I'm not sure what, if any, difference a subsystem will make to the mapped design (I thought none), but I believe it's the case that changing module names etc. can affect the place and route algorithm's start seed. I seem to remember seeing this mentioned in a Xilinx doc under the heading I've

Re: [casper] Timing errors and subsystems

for your help, Paul On 01/29/2014 06:07 PM, Jack Hickish wrote: I'm not sure what, if any, difference a subsystem will make to the mapped design (I thought none), but I believe it's the case that changing module names etc. can affect the place and route algorithm's start seed. I seem to remember

Re: [casper] Timing errors and subsystems

changing this seed and compiling again? Thanks for your help, Paul On 01/29/2014 06:07 PM, Jack Hickish wrote: I'm not sure what, if any, difference a subsystem will make to the mapped design (I thought none), but I believe it's the case that changing module names etc. can affect

Re: [casper] adc5g glitch

there is some code out there (I believe written by Jack Hickish) that adjusts the IODELAYs on each data bit to correct for capture errors. Just to say, this code is in a fork of the sma repo, at https://github.com/jack-h/adc_tests But you won't need to calibrate per-bit unless you're running

Re: [casper] ROACH-2 and the x64 ADC Block Compatibility Problem

Hi Richard, I made a ROACH2 version of this block at the last CASPER workshop, and somewhere between then and now it seems to have disappeared into the digital aether. I'll try and dig it out this weekend. But in general, the modification procedure is: 1) Copy the relevant pcores in

Re: [casper] ROACH-2 and the x64 ADC Block Compatibility Problem

Richard, I've just added all the code you need to compile the x64 ADC on ROACH2 to my repo at https://github.com/jack-h/mlib_devel/ I think (since you seem to already have the adc yellow block for ROACH1) that you should just be able to cherry pick the last commit -- it should have everything

Re: [casper] Xeng auto_tap block error

Might also be worth saying that you can also pass arguments to the underlying search function, for example, to update all software registers (which is particularly useful of late): update_casper_blocks(bdroot, 'Tag', 'sw_reg') Awesome! On 3 February 2014 19:22, David MacMahon

Re: [casper] MUX

Hi Katty, I think the root of your problems might be that you are using simulink's multiplexer blocks on your ADC outputs rather than Xilinx's. Then you end up with multidimensional signals, which the Xilinx blocks don't like. The Xilinx time division multiplexing block is in the Xilinx Basic

Re: [casper] ROACH-2 USB Communication Dead?

Hi Richard, There are two USB connectors on the board -- the USB B one is the one which will show up to a PC as a serial device. The USB A one for adding slave devices to the power pc (eg booting a file system from usb) -- are you connecting to the right one? Cheers, Jack On 12 February 2014

Re: [casper] ROACH-2 USB Communication Dead?

be happening? Thanks all, Richard On Wed, Feb 12, 2014 at 1:37 PM, Jack Hickish jackhick...@gmail.com wrote: Yeah, it's not great naming. host and slave or something like that would probably have been better. I'm pretty sure FTDI is just the brand name for the chip which provides USB

Re: [casper] 1.25 GHz spectrometer

On 21 February 2014 04:40, Shobhit Jain jshobhit...@gmail.com wrote: Hello all, I am designing a 1.25 GHz bandwidth 4096 channel spectrum analyzer using Roach-2 (Rev-2) and ASIAA Sinica 5GSPS ADC kit. My design is based on tut-3 and I am using ADC 5g yellow block in my design (1:1 demux, AC

Re: [casper] How to set the sys_rev, sys_rev_rcs, and sys_scratchpad registers?

Hi Paul, None of these registers is directly configurable from within simulink. They live in the sys_block pcore -- see the relevant base package .../xps_base/XPS_ROACHx_base/system.mhs, for where their values are set. The sys_rev and sys_rev_rcs are determined by the hardware. E.g., roach has

Re: [casper] How to set the sys_rev, sys_rev_rcs, and sys_scratchpad registers?

checkouts. Failing that, it will use timestamps. This is handled automatically with the get_rcs function in corr. Jason On 26 Feb 2014, at 17:07, Jack Hickish jackhick...@gmail.com wrote: Hi Paul, None of these registers is directly configurable from within simulink. They live

Re: [casper] Reset Jumper Cable for 64ADCx64-12 and ROACH-2

Hi Richard, The yellow block should use the roach 2 gpios in the same way as roach 1, so the reset signal should control pin 0 of the gpio bank (though the choice of banks a and b won't make any difference on roach 2, since there's only one). Cheers, Jack On 11 Mar 2014 21:44, Richard Black

[casper] 10GbE throughput

Hi all, I have an application that generates 40 Gb/s of data and I'd like to output it over 4 x 10GbE links (i.e. one roach2 mezzanine card). I'm going to have to throw some data away to make room for packetising overhead, and right now I'm trying to work out how much, to see whether I should

Re: [casper] 10GbE throughput

On 14 March 2014 10:02, Jason Manley jman...@ska.ac.za wrote: I'm not sure... I didn't investigate much further once I figured out it'd work fine for our application. Can't argue with that :) Sounds like some benchmarking is in order... Jason On 14 Mar 2014, at 11:55, Jack Hickish

Re: [casper] Bidirection GPIO

Hey Alex, There's a tutorial on making such a block on the wiki (including the files you need to add it to the toolflow). I wrote it whilst at the workshop last year, so its only tested to the extent that I could communicate from one gpio to another and then back again. Note that the roach gpios

Re: [casper] One GB Ethernet block

Hey Tim, Unfortunately, the one Gb Ethernet block is exclusively for ROACH2. The ROACH-1 board only has 10GbE outputs (or XAUI) directly from the FPGA via the CX4 connectors. The only way to get data out on a slower connection is via the PowerPC on 100mb Ethernet, using either the katcp interface

[casper] CASPER Workshop 2014 -- Registration now open!

Dear Casperites, Just a quick email to say that the CASPER wiki has been updated with some new details about the upcoming workshop. Check it out at https://casper.berkeley.edu/wiki/Workshop_2014 The important details -- Where: University of California, Berkeley Registration Closes: April 29,

Re: [casper] ADC64X yellowblock

Hi Rick, The ROACH version seems to have made it into the xps_library at repo at https://github.com/ska-sa/mlib_devel There's both the ROACH and ROACH2 versions at https://github.com/jack-h/mlib_devel (though the latter is untested) Block documentation at

Re: [casper] FFT compute time

Hi Tim, Also, if we supply ONE and only ONE sync pulse, should the fft block compute indefinately? My simulink seems to require a series of sync pulses to get the FFt to work more than once. That's right, one and only one sync pulse is sufficient to keep the FFT operating indefinitely on

Re: [casper] casper Digest, Vol 78, Issue 2

Hi Tim, On 2 May 2014 14:16, Madden, Timothy J. tmad...@aps.anl.gov wrote: Aaron I thought they were streaming until I tried using simulink. If I give the FFTs ONE and only ONE pulse, they compute ONE FFT and stop. So I have to give a series of pulses. So then I must figure out what sync

[casper] Workshop Participant List Schedule

Hi all, The 2014 workshop participant list and preliminary schedule are now on the wiki. Participant List: https://casper.berkeley.edu/wiki/Workshop_2014_Participant_List Schedule: https://casper.berkeley.edu/wiki/Workshop_2014_Schedule If you see any errors or omissions, please let me know. If

Re: [casper] ISE 14.7 in ubuntu 12.04

Hey Rolando, Have you followed these instructions: https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b ? Jack On 12 May 2014 18:55, Rolando Paz flx...@gmail.com wrote: Hi everyone. Someone managed to install ISE 14.7 in ubuntu 12.04? Best Regards Rolando Paz

Re: [casper] ISE 14.7 in ubuntu 12.04

you have any idea about how to install ISE 14.7 on Linux? Best Regards Rolando Paz 2014-05-12 20:55 GMT-06:00 Jack Hickish jackhick...@gmail.com: Hey Rolando, Have you followed these instructions: https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b ? Jack

Re: [casper] PIC32 controlling ROACH in a radio telescope.

Out of interest, what are you wanting to use katcp on the PIC for? Jack On 15 May 2014 17:10, John Ford jf...@nrao.edu wrote: Hi, I want to implement KATCP protocol on a PIC32 micro controller. I'm trying to compile the KATCP C library over a TCP/IP stack freeware provided by Microchip (the

[casper] Workshop 2014 Schedule

Hi All, The 2014 CASPER Workshop Schedule is now complete, and is online at https://casper.berkeley.edu/wiki/Workshop_2014_Schedule The talks are loosely grouped into themed sessions, and then heavily perturbed by participants individual availabilities. Where I know that individual participants

[casper] ROACH2 max LVDS rate ADC5g

Howdy, The wiki says the ADC5g can run at maximum rate (1.25 Gb/s) on ROACH2, but the LVDS maximum input rate (for a standard speed-grade ROACH2) appears to be 1.1 Gb/s -- Table 41, http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf Am I missing something or looking at the wrong

Re: [casper] Trouble with ROACH external clocking

? -Alex On Thu, Jun 5, 2014 at 10:30 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Alex, Lots of questions for you! -- Which

Re: [casper] I did it!!!!!! POCO Software IBOB

Hi Rolando, I don't know too much about the pocket correlator software you're running, but I expect you can open and plot the .uv data files with the plot_corr.py script, which is a part of the aipy python package (run with the -h flag to get information about the options) -- see

[casper] Deprecated pcores

Good Morning, It was very kind of some (surely independent, non-casper) soul to share some deprecated cores necessary for casper compiles with recent versions of Xilinx tools. It would be nice if whomever is doing this sharing could update the opb core mpd file to support virtex 6 for roach2,

Re: [casper] total power sampler

Hi Ramesh, When the data gets to your simulink design it will be multiplexed with 4 adc channels per adc yellow block output, so you'll have to demux yourself or deal with the mulitplexing in your code somehow. I don't think there's a casper block to demultiplex this for you, though there is a

Re: [casper] total power sampler

. Cheers, Ramesh On 24 Jun 2014, at 10:52, Jack Hickish jackhick...@gmail.com wrote: Hi Ramesh, When the data gets to your simulink design it will be multiplexed with 4 adc channels per adc yellow block output, so you'll have to demux yourself or deal with the mulitplexing in your code

Re: [casper] Trouble Compiling

Hi Tom, Are there any error messages (other than the last one) in your model's compile directory/XPS_ROACH_base/platgen.log or system.log? Cheers, Jack On 26 June 2014 21:38, Geelen, T.F.G. t.f.g.gee...@student.tue.nl wrote: Hello, I'm trying to compile a simple model on my laptop after I

Re: [casper] Trouble simulating ADC board

Hi Tom, If you look under the adc block at test/adc083000x2/test_adc083000x2_adc0_user_outofrange what's that gateway block being driven by? Is it something fishy-looking? Cheers, Jack On 2 July 2014 12:53, Geelen, T.F.G. t.f.g.gee...@student.tue.nl wrote: Hi, I am trying to simulate a

Re: [casper] ADC 5GS error in ROACH2

Hi, Just a thought - Is it possible that the zdok you've selected for the ADC doesn't match the clock selected in the mssge block? I.e., if you're ADC is on zdok0, are you clocking off adc0 and not adc1? Cheers, Jack On 4 Jul 2014 09:46, Geelen, T.F.G. t.f.g.gee...@student.tue.nl wrote: Hi,

[casper] ROACH2 10GbE implementation parameters

Hi all, I'm testing a switch for a ROACH2-based packetized FX correlator. I currently have a single ROACH with 8 SFP-ports connected, 4 on a 2m QSFP-4xSFP cable, and 4 on 3m QSFP-4xSFP cable. Both are passive copper (30 AWG). The switch is a Mellanox SX1012, which might be the root of the problem

Re: [casper] ROACH2 10GbE implementation parameters

by the switch and dropped by the roach vs not being received by the switch in the first place? Can you change any transmission parameters on the switch? FWIW, I think you can set preemph and other such params on the ROACH at runtime via software. Dave On Jul 22, 2014, at 11:27 AM, Jack

Re: [casper] ROACH2 10GbE implementation parameters

Thanks for the info, I will certainly try and get my hands on some new Mellanox firmware before fighting with the vitesse. Cheers, Jack On 23 July 2014 01:04, Jason Manley jman...@ska.ac.za wrote: though I think these only affect the short link between the FPGA and the vitesse tranceiver

Re: [casper] Problem running tutorial 2

Hi Tom, This is a library version issue. I've been useless and haven't yet pushed the up-to-date library to the casper-astro repository. I shall do this now (though it might take a few minutes for me to download and push the correct stuff to github). Jack On 11 August 2014 10:57, Geelen, T.F.G.

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