[casper] DDR Size on Roach2 rev2

Hi All, Has anyone tried a 16GB DDR stick on the ROACH2? Thanks, --Adam Adam Schoenwald - Electrical Engineer Code 564/Instrument Electronics Development Branch NASA Goddard Space Flight Center

[casper] Netboot for ROACH2 in 2017

Hi All, The point: I'm looking for a new snapshot, or instructions on how to make one, for netbooting a roach2. Can anyone either update the git, namely the snapshot file, at https://github.com/ska-sa/roach2_nfs_uboot or give instructions on how to properly merge recent changes into the nfs

[casper] DRAM errors on readout

Hi All, I've been trying to get the DRAM to work on the ROACH2 and It looks like my data is getting jumbled when read out. I have a few questions I'm hoping people may have answers to. 1) If the roach2 clock, coming from adc0, is set to 200MHZ, do I need to set the DRAM data path clock

[casper] QDR Help / Timing Diagram

Hi All, I've abandoned my attempt to use the DRAM for now and moved on to QDR. I'm somewhat confused by the wiki at https://casper.berkeley.edu/wiki/Qdr . The "issuing commands section" says that one type of command cannot be issued in two consecutive cycles. The "bursting" section says that

RE: [casper] QDR Help / Timing Diagram

Jack Hickish <jackhick...@gmail.com> Cc: Schoenwald, Adam J. (GSFC-5640) <adam.schoenw...@nasa.gov>; Casper Lists <casper@lists.berkeley.edu> Subject: Re: [casper] QDR Help / Timing Diagram There's also a testbench for our ROACH2 VACC that's currently in service on MeerKAT, whic

RE: [casper] OPB Address Space Overlap when using DRAM

k as long as the addresses in these two files are consistent, you could change them. Does the dram interface actually work, when you can get the design to compile? If so I'd be interested to know what libraries you're using. Cheers Jack On Mon, 26 Jun 2017 at 12:13 Schoenwald, Adam J. (GSFC-5640)

[casper] OPB Address Space Overlap when using DRAM

Hi All, I am trying to compile a design with using DRAM, an ADC16x250, 1x 10Gbe, and a good number of software registers. I also have a 128x2^11 snapshot. I don't want an interface from the DRAM to the CPU (and have checked the box saying so) if that is relavent. I saw a recent commit by Jack H