Re: [casper] QDR Help / Timing Diagram

2017-07-05 Thread Jack Hickish 
On Wed, 5 Jul 2017 at 11:01 Schoenwald, Adam J. (GSFC-5640) <
adam.schoenw...@nasa.gov> wrote:

> Thanks Jack, Jason,
> I think I have the QDR Timing down now, at least in simulation.
>
> Do I need to do anything special to use the ECC bits? If I want to
> calibrate QDR, does that mean I must include the CPU interface? Is this
> related to how I set the be flag ?
>

The CPU interface is needed, as you surmise. Depending on what version of
mlib_devel you're using, the CPU interface yellow block option parameter
should be overridden by the toolflow in the case of ROACH2, but there's no
harm in manually enabling the interface..

The ECC bits are made available to simulink (i.e., the data bus is a
multiple of 9 bits, not 8 bits) but (someone can correct me if I'm wrong)
you have to implement the correction code yourself, the controller doesn't
do anything smart with the extra bits, it just makes them available for
user storage.

Cheers
Jack

PS -- please come to the CASPER workshop!




>
> Thanks,
> --Adam
>
> 
> Adam Schoenwald - Electrical Engineer
> Office: 301.286.4175  | Cell & Text: 631-241-0003
> 
>
>
> -Original Message-
> From: Jason Manley [mailto:jman...@ska.ac.za]
> Sent: Wednesday, July 5, 2017 10:55 AM
> To: Jack Hickish <jackhick...@gmail.com>
> Cc: Schoenwald, Adam J. (GSFC-5640) <adam.schoenw...@nasa.gov>; Casper
> Lists <casper@lists.berkeley.edu>
> Subject: Re: [casper] QDR Help / Timing Diagram
>
> There's also a testbench for our ROACH2 VACC that's currently in service
> on MeerKAT, which may help you:
> https://github.com/ska-sa/cbf_fpga_testbenches/blob/master/test_qdr_vacc5.slx
>
> Note that there are calibration problems with QDR on ROACH2, so you'll
> likely encounter bit errors. If this matters to you, I highly recommend you
> leverage the ECC bits...
>
> Jason Manley
> CBF Manager
> SKA-SA
>
> Cell: +27 82 662 7726 <+27%2082%20662%207726>
> Work: +27 21 506 7300 <+27%2021%20506%207300>
>
> On 05 Jul 2017, at 16:49, Jack Hickish <jackhick...@gmail.com> wrote:
>
> >
> >
> > On Wed, Jul 5, 2017, 6:56 AM Schoenwald, Adam J. (GSFC-5640) <
> adam.schoenw...@nasa.gov> wrote:
> > Hi All,
> >
> > I've abandoned my attempt to use the DRAM for now and moved on to QDR.
> >
> > I'm somewhat confused by the wiki  at
> https://casper.berkeley.edu/wiki/Qdr .
> >
> >
> >
> > The "issuing commands section" says that one type of command cannot be
> issued in two consecutive cycles.
> >
> > The "bursting" section says that data for both read and write is
> presented for two cycles, and that data_in and be must be set for both of
> those cycles.
> >
> >
> >
> > Does this mean that a "write event" lasts for two clock cycles?
> >
> > If so, can data_in change from the first clock cycle to the second,
> storing a total of 144 bits over two cycles?
> >
> >
> > Correct. I believe there is a qdr transpose block in the library which
> may be a useful reference design.
> >
> > Cheers
> > Jack
> >
> >
> >
> > Thanks,
> >
> > --Adam
> >
> >
> >
> > 
> >
> > Adam Schoenwald - Electrical Engineer
> >
> > 
> >
> >
> >
> >
> > --
> > You received this message because you are subscribed to the Google
> Groups "casper@lists.berkeley.edu" group.
> > To unsubscribe from this group and stop receiving emails from it, send
> an email to casper+unsubscr...@lists.berkeley.edu.
> > To post to this group, send email to casper@lists.berkeley.edu.
> >
> > --
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>

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RE: [casper] QDR Help / Timing Diagram

2017-07-05 Thread Schoenwald, Adam J. (GSFC-5640) 
Thanks Jack, Jason,
I think I have the QDR Timing down now, at least in simulation.

Do I need to do anything special to use the ECC bits? If I want to calibrate 
QDR, does that mean I must include the CPU interface? Is this related to how I 
set the be flag ? 

Thanks,
--Adam


Adam Schoenwald - Electrical Engineer 
Office: 301.286.4175  | Cell & Text: 631-241-0003



-Original Message-
From: Jason Manley [mailto:jman...@ska.ac.za] 
Sent: Wednesday, July 5, 2017 10:55 AM
To: Jack Hickish <jackhick...@gmail.com>
Cc: Schoenwald, Adam J. (GSFC-5640) <adam.schoenw...@nasa.gov>; Casper Lists 
<casper@lists.berkeley.edu>
Subject: Re: [casper] QDR Help / Timing Diagram

There's also a testbench for our ROACH2 VACC that's currently in service on 
MeerKAT, which may help you: 
https://github.com/ska-sa/cbf_fpga_testbenches/blob/master/test_qdr_vacc5.slx

Note that there are calibration problems with QDR on ROACH2, so you'll likely 
encounter bit errors. If this matters to you, I highly recommend you leverage 
the ECC bits...

Jason Manley
CBF Manager
SKA-SA

Cell: +27 82 662 7726
Work: +27 21 506 7300

On 05 Jul 2017, at 16:49, Jack Hickish <jackhick...@gmail.com> wrote:

> 
> 
> On Wed, Jul 5, 2017, 6:56 AM Schoenwald, Adam J. (GSFC-5640) 
> <adam.schoenw...@nasa.gov> wrote:
> Hi All,
> 
> I've abandoned my attempt to use the DRAM for now and moved on to QDR.
> 
> I'm somewhat confused by the wiki  at https://casper.berkeley.edu/wiki/Qdr .
> 
>  
> 
> The "issuing commands section" says that one type of command cannot be issued 
> in two consecutive cycles.
> 
> The "bursting" section says that data for both read and write is presented 
> for two cycles, and that data_in and be must be set for both of those cycles.
> 
>  
> 
> Does this mean that a "write event" lasts for two clock cycles?
> 
> If so, can data_in change from the first clock cycle to the second, storing a 
> total of 144 bits over two cycles?
> 
> 
> Correct. I believe there is a qdr transpose block in the library which may be 
> a useful reference design.
> 
> Cheers
> Jack
> 
>  
> 
> Thanks,
> 
> --Adam
> 
>  
> 
> 
> 
> Adam Schoenwald - Electrical Engineer
> 
> 
> 
>  
> 
> 
> -- 
> You received this message because you are subscribed to the Google Groups 
> "casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
> 
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> To unsubscribe from this group and stop receiving emails from it, send an 
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> To post to this group, send email to casper@lists.berkeley.edu.

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Re: [casper] QDR Help / Timing Diagram

2017-07-05 Thread Jason Manley 
There's also a testbench for our ROACH2 VACC that's currently in service on 
MeerKAT, which may help you: 
https://github.com/ska-sa/cbf_fpga_testbenches/blob/master/test_qdr_vacc5.slx

Note that there are calibration problems with QDR on ROACH2, so you'll likely 
encounter bit errors. If this matters to you, I highly recommend you leverage 
the ECC bits...

Jason Manley
CBF Manager
SKA-SA

Cell: +27 82 662 7726
Work: +27 21 506 7300

On 05 Jul 2017, at 16:49, Jack Hickish  wrote:

> 
> 
> On Wed, Jul 5, 2017, 6:56 AM Schoenwald, Adam J. (GSFC-5640) 
>  wrote:
> Hi All,
> 
> I’ve abandoned my attempt to use the DRAM for now and moved on to QDR.
> 
> I’m somewhat confused by the wiki  at https://casper.berkeley.edu/wiki/Qdr .
> 
>  
> 
> The “issuing commands section” says that one type of command cannot be issued 
> in two consecutive cycles.
> 
> The “bursting” section says that data for both read and write is presented 
> for two cycles, and that data_in and be must be set for both of those cycles.
> 
>  
> 
> Does this mean that a “write event” lasts for two clock cycles?
> 
> If so, can data_in change from the first clock cycle to the second, storing a 
> total of 144 bits over two cycles?
> 
> 
> Correct. I believe there is a qdr transpose block in the library which may be 
> a useful reference design.
> 
> Cheers
> Jack
> 
>  
> 
> Thanks,
> 
> --Adam
> 
>  
> 
> 
> 
> Adam Schoenwald - Electrical Engineer
> 
> 
> 
>  
> 
> 
> -- 
> You received this message because you are subscribed to the Google Groups 
> "casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
> 
> -- 
> You received this message because you are subscribed to the Google Groups 
> "casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an 
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.

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Re: [casper] QDR Help / Timing Diagram

2017-07-05 Thread Jack Hickish 
On Wed, Jul 5, 2017, 6:56 AM Schoenwald, Adam J. (GSFC-5640) <
adam.schoenw...@nasa.gov> wrote:

> Hi All,
>
> I’ve abandoned my attempt to use the DRAM for now and moved on to QDR.
>
> I’m somewhat confused by the wiki  at https://casper.berkeley.edu/wiki/Qdr
> .
>
>
>
> The “issuing commands section” says that one type of command cannot be
> issued in two consecutive cycles.
>
> The “bursting” section says that data for both read and write is presented
> for two cycles, and that data_in and be must be set for both of those
> cycles.
>
>
>
> Does this mean that a “write event” lasts for two clock cycles?
>
> If so, can data_in change from the first clock cycle to the second,
> storing a total of 144 bits over two cycles?
>

Correct. I believe there is a qdr transpose block in the library which may
be a useful reference design.

Cheers
Jack

>
>
> Thanks,
>
> --Adam
>
>
>
> 
>
> Adam Schoenwald - Electrical Engineer
>
> 
>
>
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To post to this group, send email to casper@lists.berkeley.edu.
>

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