this. And even then, I probably won't have time to focus on
hardware I don't own.
I'm thankful for your engagement and I fully understand you. Now, it
will be better if you focus on your final exams :) Good luck!
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list
0xF2F100FF_56960004
I think you are correct. This looks like the memory init is not able
to get correct information from the SPD. If that is the problem, you
should check that the SMBus controller setup is correct.
Ok, I'm going to check it.
--
Piotr Piwko
http://www.embedded-engineering.pl
2010/2/24 Peter Stuge pe...@stuge.se:
Piotr Piwko wrote:
I'm afraid that I will have to write my own part of code which will
be responsible to execute a boostrap. At this moment I use the old
version of coreboot project (practically LinuxBIOS 2.0.0), because
only in this release my target
Hello,
Does coreboot support executing of boostrap which is contained in MBR?
Maybe you have any hints about writing payload which can do that?
Thanks in advance,
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org
for your interest.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
in advance for your engagement.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
that msrtool doesn't have suitable
definitions in its database.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
2010/1/13 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net:
On 13.01.2010 15:45, Piotr Piwko wrote:
I had removed the the 'wbinvd' cache invalidation function, and then a
boot process moved on. Now it hangs on 'FATAL: NO VSA found!' error'.
Hm. I know the that piece of v3 code rather
2010/1/14 Peter Stuge pe...@stuge.se:
Piotr Piwko wrote:
Anyway, could you provide my any better solution to include the VSA
to coreboot image?
I believe you're doing it the correct way already.
I hope so too :)
There is a similar function ram_check() in lib/ramtest.c.
Yes, but I don't
.bin:blob/vsa
After that, the boot process hangs on 'Done printk() buffer move'. It
seems like the VSA is not placed in a proper place in the whole bios
image. Do you know any other possibilities to include the VSA in
coreboot image?
Thanks in advance for interest.
--
Piotr Piwko
http://www.embedded
2010/1/12 Piotr Piwko piotr.pi...@gmail.com:
Did you already try the v3 support for adl/msm800sev?
No I didn't. I am just going to try it. Of course, I will report my
progress here :)
So, here we go :)
I attached the first log of coreboot-v3 booting process for
adl/msm800sev board. As we can
2010/1/12 Piotr Piwko piotr.pi...@gmail.com:
I attached the first log of coreboot-v3 booting process for
adl/msm800sev board. As we can see there are the same errors with SMB.
I suppose they are related as previously with the references to DIMM1
which are not present in this board.
OK, I
/msm800sev/initram.c file ... (please, see attached log).
PS. Let me know if I am too verbose in this thread. I just want to
help future users.
--
Piotr Piwko
http://www.embedded-engineering.pl/
coreboot-3.0.1177 Tue Jan 12 12:24:18 CET 2010 starting... (console_loglevel=8)
Choosing normal boot.
LAR
hint.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
don't know exactly where I need to begin make changes ...
Thanks for your interest.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
should
set a proper memory address for stack. As we can see the default
address (0x400) is wrong but which one is correct? Can you give my
any hints?
Thanks in advance
--
Piotr Piwko
http://www.embedded-engineering.pl/
coreboot-2.0.0-r4949M.0Fallback pi�ą, 8 sty 2010, 13:26:09 CET starting
-entry;
// entry = ntohl((u32) stage-entry);
return (void *) entry;
}
// ...
---
On Monday I will test the cbfs_find_file function. I hope I will found
something.
Have a good weekend!
--
Piotr Piwko
http://www.embedded
--
Piotr Piwko
http://www.embedded-engineering.pl/
coreboot-2.0.0-r4949M.0Fallback czw, 7 sty 2010, 12:55:27 CET starting...
_MSR GLCP_SYS_RSTPLL (4c14) value is: 0392:180c
Configuring PLL
coreboot-2.0.0-r4949M.0Fallback czw, 7 sty 2010, 12:55:27 CET starting...
_MSR GLCP_SYS_RSTPLL
from vendor BIOS and compare they
with coreboot values. I hope it will point me.
But first, I will check this coreboot BIOS on MSM800SEV board. It
should work correctly, isn't it?
Thank you all for your engagement. I will inform about progress in this case.
Have a nice day!
--
Piotr Piwko
http
provide my an estimated time.
Thank you in advance for engagement.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
include it in order to have 1MB coreboot image?
Thanks in advance for your help and engagement.
--
Piotr Piwko
http://www.embedded-engineering.pl/
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
21 matches
Mail list logo
