,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com/
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this an effective, non-tearing solution, you'll need
triple buffering. The latency does go up, but using DMA to transfer from
previewer memory output buffers to the VPBE bufs is the ideal solution
(~3ms for a D1 frame)
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746
is not in 'sync' with the VPBE, you'll
definitely get tearing at the VPBE output.
What is driving this requirement for single buffer access? Is it memory
usage? Latency?
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
)
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
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option than to curl up your sleeves and just dive into the
audio driver code. I had to for at least a few weeks before I could get
some headway into this.
Thanks,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http
(when I was
getting stalls) was to check the EDMA Missed event register, and to make
sure that that got cleared properly.
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
to be configured for SW_ECC for this to work
properly.
Hope it helps,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
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in this is appreciated!
Thank you,
Jerry
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
From: Karicheri, Muralidharan [mailto:m-kariche...@ti.com]
Sent: Thursday
would be appreciated,
Thank you,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
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,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
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that u-boot writes in shows that it is drastically different.
Does this amount to just different ECC values? (U-boot is doing Soft
ECC, while Kernel is HW ECC)
Or is it the OOB Layout?
Any help would be appreciated!
Thank you,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
volume chunks significantly boosted by speeds
I usually write in 8K chunks, but you should experiement with other
sizes as well.
Thanks,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
calls are not guaranteed to return in constant time.
Note that this is a slight bit of work, but its extremely useful in the
end if you'd like variable frame rate delivery, or if you'd like to do
some kind of Audio-Video synchronization
Hope it helps,
Jerry Johns
Design Engineer
inline ASM code a few months back for the
DaVinci in this manner.
http://www.ethernut.de/en/documents/arm-inline-asm.html
Hope it helps,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
not setting
any other PINMUX registers, or other control oriented regs as well.
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 221
www.nuvation.com http://www.nuvation.com
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note that the DVEVM comes with VCXOs that are controlled by PWM
signals that allow you to control drift using a proportional controller.
By varying the PWM signals, you can speed up and slow down the audio
clock to keep it sync.
Hope it helps,
Jerry Johns
Design Engineer
Nuvation Research
interplay between audio/video bus usage scenarios that might be
causing this? Thread priority inversion could also be a problem.
However, I feel the solution might be simpler than that
Thanks for the help,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 225
be pre-empting every other
thread in the system. This stuttery display reduces somewhat if audio
in/out is disabled, but is still slightly present. There is also tearing
on the screen as well.
If I run the decode demo, I do not get any problems.
Any clues?
Thanks a ton,
Jerry Johns
Hello all, Currently, the FifoUtil object allows for creation of
a pipe using the pipe() call, and then subsequent reads() and writes() allow
for inter-thread communication - I would like to know if there is a
convenient function call to purge the contents of an existing pipe? E.g, a
-intfc.c and davinci-audio.c files)
Thanks a ton,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 225
www.nuvation.com http://www.nuvation.com
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Hey all,
I'm using the DM355 chip mated with an FPGA that produces an
I2S compliant bit stream - I did not have to modify the davinci audio
drivers since the FPGA produces an exact bitstream as the TLV320AIC33
chip does (16 bit samples, L and R on a I2S line); On the application
side,
Could you give more details into your problem? What do you define as two
channels? Does that mean two stereo inputs? i.e Left and Right 1, and
Left and Right 2. Or is it Left and Right for 1 stereo input?
Also, please clearly define the exact symptoms you are getting - is the
read call
Hey all,
I've searched through these forums extensively for this
widespread audio lockup/stall problem when doing full-duplex mode on the
OSS Davinci sound driver, and was wondering if it has been resolved? Has
there been a proposed solution that definitely works? Or could someone
The davinci-audio-aic33.c is the audio codec specific to the DM6446 -
you cannot use the aic32 version as that is not the chip on the board
I think the TLV chip can be configured for Mono operation (it has mixers
in it and filter coefficients that can be programmed to do simple left
channel
DM6467 Block Diagrams - focus.ti.com.cn/cn/lit/ml/sprv065/sprv065.pdf
DM6467 Press Release
-focus.ti.com/pr/docs/preldetail.tsp?sectionId=594prelId=sc07173
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 225
www.nuvation.com
-Original Message
,
Jerry Johns
Design Engineer
Nuvation Research Corp - Canada
Tel: (519) 746-2304 ext. 225
www.nuvation.com http://www.nuvation.com
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What you need to do is resize 720P to D1, encode/decode, then resize
D1
Erm, I think that sorta defeats the purpose of 720P encoding wouldn't
it? The descaling at the first stage would result in a net loss of
information which cannot be recovered;
However, if you just want a effective SD
You cannot use 10-bit mode in the DM6446 (even though its mentioned as
being possible) - we've tried many different combinations, and finally
isolated the problem to a faulty YCbCr data output (the colors were
terribly skewed); follow up with TI confirmed that the 10-bit mode is
not functional and
Actually sorry, I gave you erroneous information just now - it has been
a while since I played around with the CCDC register settings;
10-bit BT.656 does work - the only problem is that it generates 16-bit
pixel output (not 8-bit output as we normally get currently); the data
going to RAM will
Hello all,
Recently we manufactured our own custom boards with NAND
chips, and we'r noticing that during ftl_format of the chip, it doesn't skip
over bad blocks in NAND - can someone verify is skipping bad blocks is
already supported in the montavista kernel for davinci?
I've
Hey yoni,
To rebuild the nandwriter, u need to get source from TI by
asking their reps - that's how we did it for our 128MB custom board; the
source is unsupported by them, but they will still be able to give it to
you; u just have to modify it to ensure that it doesn't load in the
Hey,
This might sound silly, but do you have video input connected on your
board (either through S-video -x option or through RCA)
Without the video, the ISR will not trigger since no EAV,SAV codes are
transmitted
Also, if you have changed the kernel code for the VPFE, then that might
Hello all,
I'm having some difficulty getting BT.656 video to work with the
VPFE; I'm modifying the current vpfe driver, including removing support for
the TVP driver. What are the required registers to be setup and what values
should they have for BT.656 to work? Here's some info on
Hi Zhou,
Don't know if this is useful, but in sprued6 (Guide to creating
algorithms), I remember reading this...
In Codec Engine, memory shared by the GPP and DSP is not cached on
the GPP, but is cached on the DSP. The skeleton must manage the
cache by invalidating the cache area
Hello,
Might seem like a dumb question, but I was wondering how do I access
memory mapped registers from the user space?
I've used *(volatile int*)IO_ADDRESS(x), inl(x), *(volatile int*)(x), where
x is 0x
Do I have to mmap it before I can do anything?
Thanks
Jerry
SangJae,
The DVEVM 1.10 is currently not set up right now to work with nand flash; if
you search the archives, youll find others in a similar dilemma (including me J)
Thats why you get the traceutil error; only
NOR works for the moment being
From: Davor Magdic [mailto:[EMAIL
]
Sent: Wednesday, October 18, 2006
1:56 PM
To: Jerry Johns;
davinci-linux-open-source@linux.davincidsp.com
Subject: RE: DSP Stack Memory Map
The copy codec
packages(e.g. codecs.videnc_copy) include libraries - and even
sources(!), and are there as examples for the Codec Engine
product.Provided
Hello,
Ive
just recently ramped up to 1.10 DVEVM, and am getting started working on some
H264 stuff at the moment, Im using the encode demo files as my
base of operation (allows for H264 encoding on dsp side, and spits out data to
arm shared buffers); however, I want to change the
that warrants a full purchase of the codec J
From: Ring, Chris
[mailto:[EMAIL PROTECTED]
Sent: Wednesday, October 18, 2006
1:56 PM
To: Jerry
Johns; davinci-linux-open-source@linux.davincidsp.com
Subject: RE: DSP Stack Memory Map
The copy codec
packages(e.g. codecs.videnc_copy
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