On Sun, Jan 08, 2012 at 03:32:21PM +0200, Gilad Ben-Yossef wrote:
on_each_cpu always returns a hard coded return code of zero.
Removing all tests based on this return value saves run time
cycles for compares and code bloat for branches.
Signed-off-by: Gilad Ben-Yossef gi...@benyossef.com
On Sun, Jan 08, 2012 at 03:32:28PM +0200, Gilad Ben-Yossef wrote:
on_each_cpu returns the retunr value of smp_call_function
which is hard coded to 0.
Refactor on_each_cpu to a void function and the few callers
that check the return value to save compares and branches.
Signed-off-by: Gilad
On Saturday, January 07, 2012, Thomas Abraham wrote:
A device node pointer is added to generic pm domain structure to associate
the domain with a node in the device tree. The platform code parses the
device tree to find available nodes representing the generic power domain,
instantiates the
Hi Benoit,
On Tue, Jan 03, 2012 at 03:09:49PM +0100, Cousson, Benoit wrote:
On 1/2/2012 10:04 AM, Grant Likely wrote:
On Thu, Dec 22, 2011 at 03:56:37PM +0100, Benoit Cousson wrote:
Add initial device-tree support for twl familly chips.
The current version is missing the regulator entries
On Sun, Jan 08, 2012 at 08:51:59PM +0800, Richard Zhao wrote:
...
So, this does appear to be conflating the two things: The definition of
what pins are in a pingroup, and the mux function for a particular
setting of that pingroup. I think you need separate nodes for this.
At least
On Sun, Jan 08, 2012 at 09:05:44PM +0800, Richard Zhao wrote:
+enum imx_imx53_pinctrl_pads {
+ MX53_GPIO_19 = 0,
+ MX53_KEY_COL0 = 1,
+ MX53_KEY_ROW0 = 2,
+ MX53_KEY_COL1 = 3,
+ MX53_KEY_ROW1 = 4,
+ MX53_KEY_COL2 = 5,
+ MX53_KEY_ROW2 = 6,
...
Why not describe it in
Jon, I was hoping I'd get some comment on this patch eventually.
On Fri, Oct 28, 2011 at 04:15:25PM +1100, David Gibson wrote:
Here is a draft patch which adds a -C option to dtc, allowing
individual semantic checks to be turned on and off. It also allows
indivudual checks to be set as
Hi,
On Sun, Jan 8, 2012 at 9:23 AM, Aneesh V ane...@ti.com wrote:
Hi,
On Tuesday 20 December 2011 03:08 PM, Aneesh V wrote:
Hi Benoit
On Tuesday 20 December 2011 06:10 PM, Cousson, Benoit wrote:
Hi Aneesh,
snip
In general, is it really feasible to parse the DTB before DDR is
Hi,
[snip lots of discussion]
Someone copied me on this so I feel I can sneak in with a response. I
have read this entire thread and implemented Tegra pinmux in U-boot,
but not much else on the topic so have limited understanding,
particular of the kernel pinmux setup, unfortunately. Sorry if I
On Mon, Jan 09, 2012 at 10:17:03AM +0800, Richard Zhao wrote:
On Mon, Jan 09, 2012 at 10:08:51AM +0800, Shawn Guo wrote:
On Sun, Jan 08, 2012 at 09:05:44PM +0800, Richard Zhao wrote:
+enum imx_imx53_pinctrl_pads {
+ MX53_GPIO_19 = 0,
+ MX53_KEY_COL0 = 1,
+
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