Hi Måns,
21.05.2024 15:43:10 Måns Rullgård :
> Frank Oltmanns writes:
>
>> The Allwinner SoC's typically have an upper and lower limit for their
>> clocks' rates. Up until now, support for that has been implemented
>> separately for each clock type.
>>
&
Dear clk and sunxi-ng maintainers,
Patches 1-4 have been reviewed and there are no pending issues. If there
is something else you need me to do to get this applied, please let me
know.
Thanks,
Frank
On 2024-03-10 at 14:21:10 +0100, Frank Oltmanns wrote:
> On some pinephones the video out
On 2024-03-13 at 19:11:37 +0100, Jernej Škrabec
wrote:
Hi Jernej,
Thank you for your having a thorough look at this!
> Hi Frank!
>
> Thanks on tackling this issue.
>
> Dne nedelja, 10. marec 2024 ob 14:32:29 CET je Frank Oltmanns napisal(a):
>> Allow the dclk to reset
Hello Ondřej,
On 2024-03-10 at 23:23:57 +0100, Ondřej Jirman wrote:
> Hello Frank,
>
> On Sun, Mar 10, 2024 at 02:32:29PM +0100, Frank Oltmanns wrote:
>> +static int sun4i_rate_reset_notifier_cb(struct notifier_block *nb,
>> + unsigned l
rate based on this the new
constraint.
Signed-off-by: Frank Oltmanns
---
I would like to make the Allwinner A64's data-clock keep its rate
when its ancestor's (pll-video0) rate changes. Keeping data-clock's rate
is required, to let the A64 drive both an LCD and HDMI display at the
same time
the other two operating points from the GPU OPP table,
so that the GPU runs at a fixed rate of 432 MHz.
Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805
Acked-by: Erico Nunes
Signed-off-by: Frank Oltmanns
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8
1 file changed, 8
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Reviewed-by: Jernej Skrabec
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 12 +++-
1 file changed, 7 inse
xi-ng: a64: force select PLL_MIPI in TCON0 mux")
Reported-by: Diego Roversi
Closes: https://groups.google.com/g/linux-sunxi/c/Rh-Uqqa66bw
Tested-by: Diego Roversi
Cc: sta...@vger.kernel.org
Reviewed-by: Maxime Ripard
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Reviewed-by: Jernej Skrabec
Signed-off-by: Frank Oltmanns
---
drivers/clk
that it is available for all clock
types.
Suggested-by: Maxime Ripard
Signed-off-by: Frank Oltmanns
Cc: sta...@vger.kernel.org
---
drivers/clk/sunxi-ng/ccu_common.c | 19 +++
drivers/clk/sunxi-ng/ccu_common.h | 3 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/clk/sunxi-ng
h appreciate your feedback!
[1] https://gitlab.com/postmarketOS/pmaports/-/issues/805
Signed-off-by: Frank Oltmanns
---
Changes in v4:
- sunxi-ng: common: Address review comments.
- Link to v3:
https://lore.kernel.org/r/20240304-pinephone-pll-fixes-v3-0-94ab828f2...@oltmanns.dev
Changes in v3:
-
the other two operating points from the GPU OPP table,
so that the GPU runs at a fixed rate of 432 MHz.
Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805
Signed-off-by: Frank Oltmanns
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8
1 file changed, 8 deletions(-)
diff --git
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Reviewed-by: Jernej Skrabec
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 12 +++-
1 file changed, 7 inse
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Reviewed-by: Jernej Skrabec
Signed-off-by: Frank Oltmanns
---
drivers/clk
xi-ng: a64: force select PLL_MIPI in TCON0 mux")
Reported-by: Diego Roversi
Closes: https://groups.google.com/g/linux-sunxi/c/Rh-Uqqa66bw
Signed-off-by: Frank Oltmanns
Tested-by: Diego Roversi
Cc: sta...@vger.kernel.org
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file changed, 2
that it is available for all clock
types.
Suggested-by: Maxime Ripard
Signed-off-by: Frank Oltmanns
Cc: sta...@vger.kernel.org
---
drivers/clk/sunxi-ng/ccu_common.c | 15 +++
drivers/clk/sunxi-ng/ccu_common.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu_common.c
s upstreamed.) I'll probably resend the patch
at a later point in time.
I very much appreciate your feedback!
[1] https://gitlab.com/postmarketOS/pmaports/-/issues/805
Signed-off-by: Frank Oltmanns
---
Changes in v3:
- dts: Pin GPU to 432 MHz.
- nkm and a64: Move minimum and maximum rate handling t
Hi Jernej,
hi Maxime,
hi Ondřej,
On 2024-02-19 at 10:41:19 +0100, Frank Oltmanns wrote:
> Hi Ondřej,
>
> On 2024-02-11 at 20:25:29 +0100, Ondřej Jirman wrote:
>> Hi Frank,
>>
>> On Sun, Feb 11, 2024 at 04:09:16PM +0100, Frank Oltmanns wrote:
>>> Hi Ondře
Hi Maxime,
On 2024-02-22 at 11:29:51 +0100, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> On Sun, Feb 11, 2024 at 04:42:43PM +0100, Frank Oltmanns wrote:
>>
>> On 2024-02-08 at 20:05:08 +0100, Maxime Ripard wrote:
>> > [[PGP Signed Part:Undecided]]
>>
Hi Jernej,
hi Maxime,
On 2024-02-05 at 16:22:26 +0100, Frank Oltmanns wrote:
> According to the Allwinner User Manual, the Allwinner A64 requires
> PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
I should point out that limiting PLL-MIPI also fixes a regr
Hi Ondřej,
On 2024-02-11 at 20:25:29 +0100, Ondřej Jirman wrote:
> Hi Frank,
>
> On Sun, Feb 11, 2024 at 04:09:16PM +0100, Frank Oltmanns wrote:
>> Hi Ondřej,
>>
>> On 2024-02-05 at 17:02:00 +0100, Ondřej Jirman wrote:
>> > On Mon, Feb 05, 2024 at 0
Hi Maxime,
On 2024-02-08 at 13:16:27 +0100, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> On Mon, Feb 05, 2024 at 04:22:26PM +0100, Frank Oltmanns wrote:
>> According to the Allwinner User Manual, the Allwinner A64 requires
>> PLL-MIPI to run at 500MHz-1
On 2024-02-11 at 16:42:43 +0100, Frank Oltmanns wrote:
> On 2024-02-08 at 20:05:08 +0100, Maxime Ripard wrote:
>> [[PGP Signed Part:Undecided]]
>> Hi Frank,
>>
>> On Mon, Feb 05, 2024 at 04:22:28PM +0100, Frank Oltmanns wrote:
>>> This panel is used in th
On 2024-02-08 at 20:05:08 +0100, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> Hi Frank,
>
> On Mon, Feb 05, 2024 at 04:22:28PM +0100, Frank Oltmanns wrote:
>> This panel is used in the pinephone that runs on a Allwinner A64 SOC.
>> The SOC requires pll-mipi to
Hi Ondřej,
On 2024-02-05 at 17:02:00 +0100, Ondřej Jirman wrote:
> On Mon, Feb 05, 2024 at 04:54:07PM +0100, Ondřej Jirman wrote:
>> On Mon, Feb 05, 2024 at 04:22:23PM +0100, Frank Oltmanns wrote:
>> > On some pinephones the video output sometimes freezes (flips between t
On 2024-02-05 at 18:56:09 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 05. februar 2024 ob 16:22:26 CET je Frank Oltmanns napisal(a):
>> According to the Allwinner User Manual, the Allwinner A64 requires
>> PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
&
Hi Jernej,
On 2024-02-05 at 18:45:27 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 05. februar 2024 ob 16:22:24 CET je Frank Oltmanns napisal(a):
>> The Allwinner A64 manual lists the following constraints for the
>> PLL-MIPI clock:
>> - M/N <= 3
>> - (PLL_VI
Set the minimum and maximum rate of Allwinner A64's PLL-MIPI according
to the Allwinner User Manual.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu
at more then 192 MHz reduces the
occurrenc of the issue.
Therefore, increase the minimum rate in the GPU OPP table to 192 MHz.
Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805
Link: https://lore.kernel.org/linux-arm-kernel/2562485.k3LOHGUjKi@kista/T/
Signed-off-by: Frank Oltmanns
---
arch
According to the Allwinner User Manual, the Allwinner A64 requires
PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nkm.c | 13 +
drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
2 files changed, 15 insertions
.
pll-mipi's constraint to run at 500MHz or higher forces us to have a
crtc_clock >= 8 kHz if we want a 60 Hz vertical refresh rate.
Change [hv]sync_(start|end) so that we reach a clock rate of 83502 kHz
so that it is high enough to align with pll-pipi limits.
Signed-off-by: Frank Oltma
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nkm.
-/issues/805
Signed-off-by: Frank Oltmanns
---
Changes in v2:
- dts: Increase minimum GPU frequency to 192 MHz.
- nkm and a64: Add minimum and maximum rate for PLL-MIPI.
- nkm: Use the same approach for skipping invalid rates in
ccu_nkm_find_best() as in ccu_nkm_find_best_with_parent_adj().
- nkm: I
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff
On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns
> napisal(a):
>> The Allwinner A64 manual lists the following constraint for the
>> PLL-VIDEO0 clock: 8 <= N/M <= 25
>>
>> U
On 2023-12-20 at 16:18:49 +0100, Jernej Škrabec
wrote:
> Dne sreda, 20. december 2023 ob 08:14:27 CET je Frank Oltmanns napisal(a):
>>
>> On 2023-12-19 at 18:04:29 +0100, Jernej Škrabec
>> wrote:
>> > Dne ponedeljek, 18. december 2023 ob 14:35:23 CET j
On 2023-12-20 at 19:57:06 +0100, Frank Oltmanns wrote:
> Ok, I've done more detailed testing, and it seems this patch results in
> lots of dropped frames. I'm sorry for not being more thorough earlier.
> I'll do some more testing without this patch and might have to either
> remov
On 2023-12-20 at 16:12:42 +0100, Jernej Škrabec
wrote:
> Dne sreda, 20. december 2023 ob 08:09:28 CET je Frank Oltmanns napisal(a):
>>
>> On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec
>> wrote:
>> > Dne ponedeljek, 18. december 2023 ob 14:35:22 CET j
be achieved when running
PLL-MIPI outside its specied range.
Best regards,
Frank
On 2023-12-20 at 16:18:49 +0100, Jernej Škrabec
wrote:
> Dne sreda, 20. december 2023 ob 08:14:27 CET je Frank Oltmanns napisal(a):
>>
>> On 2023-12-19 at 18:04:29 +0100, Jernej Škrabec
>> wrote:
&g
On 2023-12-19 at 18:04:29 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 18. december 2023 ob 14:35:23 CET je Frank Oltmanns
> napisal(a):
>> This panel is used in the pinephone that runs on a Allwinner A64 SOC.
>> Acoording to it's datasheet, the SOC requires PLL-MIPI to r
On 2023-12-19 at 17:54:19 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 18. december 2023 ob 14:35:22 CET je Frank Oltmanns
> napisal(a):
>> The Allwinner A64 manual lists the following constraint for the
>> PLL-VIDEO0 clock: 8 <= N/M <= 25
>>
>> U
Hi Jernej!
On 2023-12-19 at 17:46:08 +0100, Jernej Škrabec
wrote:
> Hi Frank!
>
> Dne ponedeljek, 18. december 2023 ob 14:35:19 CET je Frank Oltmanns
> napisal(a):
>> The Allwinner A64 manual lists the following constraints for the
>> PLL-MIPI clock:
>> - M/N >
least every other day. With the patches it has not
shown this behavior in over a week.
I very much appreciate your feedback!
[1] https://gitlab.com/postmarketOS/pmaports/-/issues/805
Signed-off-by: Frank Oltmanns
---
Frank Oltmanns (5):
clk: sunxi-ng: nkm: Support constraints on m/n ratio and
The Allwinner A64 manual lists the following constraint for the
PLL-VIDEO0 clock: 8 <= N/M <= 25
Use this constraint.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-
-by: Frank Oltmanns
---
drivers/gpu/drm/panel/panel-sitronix-st7703.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
index b55bafd1a8be..6886fd7f765e 100644
--- a/drivers
The Allwinner A64 manual lists the following constraint for the
PLL-VIDEO0 clock: 8 <= N/M <= 25
The PLL-MIPI clock is implemented as ccu_nm. Therefore, add support for
this constraint.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nm.c | 21 +++--
drive
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N >= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N >= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nkm.
On 2023-12-18 at 14:35:19 +0100, Frank Oltmanns wrote:
> The Allwinner A64 manual lists the following constraints for the
> PLL-MIPI clock:
> - M/N >= 3
> - (PLL_VIDEO0)/M >= 24MHz
>
> The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
> these
On 2023-08-28 at 10:04:51 +0200, Maxime Ripard wrote:
> On Fri, Aug 25, 2023 at 05:07:58PM +0200, Frank Oltmanns wrote:
>> Thank you for your feedback, Maxime!
>>
>> On 2023-08-25 at 10:13:53 +0200, Maxime Ripard wrote:
>> > [[PGP Signed Part:Undecided]]
>>
On 2023-08-28 at 10:25:01 +0200, Maxime Ripard wrote:
> On Sat, Aug 26, 2023 at 11:12:16AM +0200, Frank Oltmanns wrote:
>>
>> On 2023-08-25 at 17:07:58 +0200, Frank Oltmanns wrote:
>> > Thank you for your feedback, Maxime!
>> >
>> > On 2023-08-
On 2023-08-25 at 17:07:58 +0200, Frank Oltmanns wrote:
> Thank you for your feedback, Maxime!
>
> On 2023-08-25 at 10:13:53 +0200, Maxime Ripard wrote:
>> [[PGP Signed Part:Undecided]]
>> Hi,
>>
>> On Fri, Aug 25, 2023 at 07:36:36AM +0200, Frank Oltmann
Thank you for your feedback, Maxime!
On 2023-08-25 at 10:13:53 +0200, Maxime Ripard wrote:
> [[PGP Signed Part:Undecided]]
> Hi,
>
> On Fri, Aug 25, 2023 at 07:36:36AM +0200, Frank Oltmanns wrote:
>> I would like to make the Allwinner A64's pll-mipi to keep its rate when
&g
Allow clocks to keep their rate when parent (or grandparent) rate
changes.
Signed-off-by: Frank Oltmanns
---
drivers/clk/clk.c| 48 +++-
include/linux/clk-provider.h | 2 ++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git
From: Icenowy Zheng
As the clk framework keeps A64's TCON0 clock stable when HDMI changes
its parent's clock, do not protect TCON0 clock on A64 in the TCON driver
to allow PLL-Video0 to get changed by HDMI.
Signed-off-by: Icenowy Zheng
Signed-off-by: Frank Oltmanns
---
drivers/gpu/drm/sun4i
Keep the clock rate of Allwinner A64's pll-mipi even when the parent
(pll-video0) changes its rate. This is required, to drive both an LCD
and HDMI display, because both have pll-video0 as an ancestor.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++-
1 file
l/20230807-pll-mipi_set_rate_parent-v6-0-f173239a4...@oltmanns.dev/
Signed-off-by: Frank Oltmanns
---
Frank Oltmanns (2):
clk: keep clock rate when parent rate changes
clk: sunxi-ng: a64: keep rate of pll-mipi stable across parent rate
changes
Icenowy Zheng (1):
drm/sun4i: tcon: parent kee
On 2023-08-07 at 18:22:26 +0800, Icenowy Zheng wrote:
> 在 2023-08-07星期一的 11:48 +0200，Frank Oltmanns写道：
>>
>> On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng
>> wrote:
>> > 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> > > From: Iceno
On 2023-08-10 at 21:18:12 +0800, Chen-Yu Tsai wrote:
> On Mon, Aug 7, 2023 at 5:36 PM Frank Oltmanns wrote:
>>
>> Hi Icenowy,
>>
>> it is my understanding that you are the original author of the following
>> patches are in Ondřej's 6.4 branch [1] [2] [3] but n
On 2023-08-07 at 17:42:22 +0800, Icenowy Zheng wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng
>>
>> In some situaitons, we will want a clock rate be kept while its
>> parent
>> can change, for example, to make dual-head
On 2023-08-07 at 17:43:52 +0800, Icenowy Zheng wrote:
> 在 2023-08-07星期一的 11:36 +0200，Frank Oltmanns写道：
>> From: Icenowy Zheng
>>
>> Notify TCON0 clock (and in consequence PLL-MIPI by
>> CLK_SET_RATE_PARENT)
>> to reset when PLL-Video0 changes (because of HDMI P
From: Icenowy Zheng
As the A64 CCU driver has already the ability to keep TCON0 clock stable
when HDMI changes its parent's clock, do not protect TCON0 clock on A64
in the TCON driver to allow PLL-Video0 gets changed by HDMI (the CCU
will then restore the TCON0 clock rate).
Signed-off-by:
From: Icenowy Zheng
Notify TCON0 clock (and in consequence PLL-MIPI by CLK_SET_RATE_PARENT)
to reset when PLL-Video0 changes (because of HDMI PHY clk which is a
child of PLL-Video0 and has CLK_SET_RATE_PARENT set). In this way we can
get clock tree to satisfy both pipelines.
---
From: Icenowy Zheng
In some situaitons, we will want a clock rate be kept while its parent
can change, for example, to make dual-head work on A64, TCON0 clock
needs to be kept for LCD display and its parent (or grandparent)
PLL-Video0 need to be changed for HDMI display. (There's a quirk on A64
/e19ccee10a8492535b6cda1ba972074d6e65
Signed-off-by: Frank Oltmanns
---
Icenowy Zheng (3):
clk: sunxi-ng: add support for rate resetting notifier
clk: sunxi-ng: a64: keep tcon0 clock rate when pll-video0's rate changes
drm/sun4i: tcon: hand over the duty to keep TCON0 clock to CCU on A64
drivers/clk
Hi Chris,
hi Guido,
On 2023-06-06 at 08:12:36 +0200, Frank Oltmanns wrote:
> Hi Chris,
> hi Guido,
>
> On 2023-04-26 at 16:54:46 +0200, Guido Günther wrote:
>> Hi Chris,
>> could you check if these two modifications by Frank of the init sequence
>>
>>
Hi Chris,
hi Guido,
On 2023-04-26 at 16:54:46 +0200, Guido Günther wrote:
> Hi Chris,
> could you check if these two modifications by Frank of the init sequence
>
>
> https://lore.kernel.org/dri-devel/20230211171748.36692-2-fr...@oltmanns.dev/
>
>
Hello Roman,
On 2023-05-09 at 13:04:50 +0200, "Roman Beranek" wrote:
> On Mon May 8, 2023 at 10:47 AM CEST, Frank Oltmanns wrote:
>> I played back a 60 fps video (10 seconds) and recorded the panel's
>> output with a 240 fps camera. I noticed only 2 dropped
Hello again,
On 2023-05-08 at 08:54:28 +0200, Frank Oltmanns wrote:
> Hello Roman,
>
> On 2023-05-03 at 16:22:32 +0200, "Roman Beranek" wrote:
>> Hello everyone,
>>
>> I apologize for my absence from the discussion during past week, I got
>> hit w
ropped frames, that I
account to the imperfect data rate of 107.8MHz instead of 108 MHz due to
pll-video0's rate being 294MHz instead of the 297 MHz for reasons I
described in the thread on your v2 of this patch [4]).
Tested-by: Frank Oltmanns
Thanks,
Frank
[1]: https://lore.kernel.org/all/2
Hello Roman,
On 2023-05-03 at 16:22:32 +0200, "Roman Beranek" wrote:
> Hello everyone,
>
> I apologize for my absence from the discussion during past week, I got
> hit with tonsillitis.
I hope you feel better!
> On Mon May 1, 2023 at 3:40 PM CEST, Frank O
Maxime, Jernej, I was trying to understand why pll-video0 is not updated
and I tracked down the culprit to ccu_nkm.c.
On 2023-04-23 at 15:24:33 +0200, Frank Oltmanns wrote:
> On 2023-04-18 at 09:40:01 +0200, Roman Beranek wrote:
>> According to Allwinner's BSP code, in DSI mode, TC
Hi Jernej,
On 2023-04-28 at 08:43:29 +0200, Jernej Škrabec
wrote:
> Dne četrtek, 27. april 2023 ob 11:16:08 CEST je Roman Beranek napisal(a):
>> With pll-mipi as its source clock, the exact rate to which TCON0's data
>> clock can be set to is constrained by the current rate of pll-video0.
>>
Hi Roman,
On 2023-04-18 at 09:40:01 +0200, Roman Beranek wrote:
> According to Allwinner's BSP code, in DSI mode, TCON0 clock needs to be
> running at what's effectively the per-lane datarate of the DSI link.
> Given that the TCON DCLK divider is fixed to 4 (SUN6I_DSI_TCON_DIV),
> DCLK can't be
On 2023-04-03 at 15:52:36 +0200, "Roman Beranek" wrote:
> On Sun Apr 2, 2023 at 12:49 PM CEST, Frank Oltmanns wrote:
>>
>> When apply this to drm-next my panel stays dark. I haven't figured out
>> yet why, though. The other two patches in this series work fi
lock * 1000);
> +
> + /* Set the resolution */
> + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
> + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
> + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
>
> /* Set dithering if needed */
> sun4i_tcon0_mode_set_dithering(tcon, connector);
--
--
Frank Oltmanns
Hi Roman,
On 2023-03-29 at 21:58:02 +0200, Maxime Ripard wrote:
> On Tue, Mar 28, 2023 at 01:48:33AM +0200, Roman Beranek wrote:
>> On Mon Mar 27, 2023 at 10:20 PM CEST, Maxime Ripard wrote:
>> >
>> > On Sat, Mar 25, 2023 at 12:40:04PM +0100, Frank Oltmanns wr
Hi,
On 2023-03-29 at 21:56:39 +0200, Maxime Ripard wrote:
> Hi,
>
> On Tue, Mar 28, 2023 at 09:28:19PM +0200, Frank Oltmanns wrote:
>> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
>> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
>> @@ -819,6 +819,34 @@ static voi
Hi,
On 2023-03-27 at 22:20:45 +0200, Maxime Ripard wrote:
> Hi,
>
> On Sat, Mar 25, 2023 at 12:40:04PM +0100, Frank Oltmanns wrote:
[...]
>> Actually, I had the following third patch prepared that adjusted the
>> dotclock rate so that the
>> required PLL rate is
Hi,
On 2023-03-20 at 17:16:36 +0100, Roman Beranek wrote:
> In the case of DSI output, the value of SUN4I_TCON0_DCLK_DIV (4) does
> not represent the actual dotclock divider, PLL_MIPI instead runs at
> (bpp / lanes )-multiple [1] of the dotclock. [2] Setting 4 as dotclock
> divder thus leads to
Hi Maxime,
On 2023-03-21 at 15:57:39 +0100, Maxime Ripard wrote:
> Hi,
>
> On Sun, Mar 19, 2023 at 05:07:04PM +0100, Frank Oltmanns wrote:
>> Set the required PLL rate by adjusting the dotclock rate when calling
>> clk_set_rate() when using DSI.
>>
>> According
this change the common mode set function would only contain
setting the resolution. Therefore, dissolve the function and transfer
the functionality to the individual mode set functions.
Signed-off-by: Frank Oltmanns
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 --
1
/
[3]
https://github.com/megous/linux/commit/eb5f28fb58727f4a6546f211486aad0d19cdea3f
Frank Oltmanns (1):
drm/sun4i: tcon: Fix setting PLL rate when using DSI
drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 --
1 file changed, 31 insertions(+), 15 deletions(-)
--
2.39.2
Hi Ondřej,
hi Guido,
On 2023-02-19 at 13:35:42 +0100, Ondřej Jirman wrote:
> On Sun, Feb 19, 2023 at 12:45:53PM +0100, Frank Oltmanns wrote:
>> Fix the XBD599 panel’s slight visual stutter by correcting the pixel
>> clock speed so that the panel’s 60Hz vertical refresh rate is
Hi Ondřej,
hi all,
Ondřej Jirman writes:
> On Sun, Feb 19, 2023 at 12:45:53PM +0100, Frank Oltmanns wrote:
>> Fix the XBD599 panel’s slight visual stutter by correcting the pixel
>> clock speed so that the panel’s 60Hz vertical refresh rate is met.
>>
>> Set the clock
Fix the XBD599 panel's slight visual stutter by correcting the pixel
clock speed so that the panel's 60Hz vertical refresh rate is met.
Set the clock speed using the underlying formula instead of a magic
number. To have a consistent procedure for both panels, set the JH057N
panel's clock also as
...@oltmanns.dev/
Frank Oltmanns (1):
drm/panel: st7703: Fix vertical refresh rate of XBD599
drivers/gpu/drm/panel/panel-sitronix-st7703.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--
2.39.1
initialization
function.
The XDB599 does not require a 20 msec delay between the SETBGP and
SETVCOM commands. Therefore, remove the delay from the device specific
initialization function.
Signed-off-by: Frank Oltmanns
Cc: Ondrej Jirman
Reported-by: Samuel Holland
---
drivers/gpu/drm/panel/panel-sitronix
with the JH057N panel used in the Librem
5 devkit. I hereby kindly ask for Librem (i.e. Guido) to test this.
The patch is based on drm-next.
Ondřej, since this is just a very minor refactoring of your work, I
would gladly put you as the author, if you wish so.
Thanks,
Frank
Frank Oltmanns (1):
drm/panel
Hi Ondřej,
ok, now I get it. Thank you very much for your thorough explanation. It really
appreciate it!
Ondřej Jirman writes:
> On Sun, Feb 12, 2023 at 06:52:05PM +0100, Frank Oltmanns wrote:
>> Ondřej Jirman writes:
>>
>> > On Sun, Feb 12, 2023 at 01:08:29PM +01
Hi Ondřej,
hi Guido,
Ondřej, thank you very much for your feedback!
I have a couple of questions.
Ondřej Jirman writes:
> On Sun, Feb 12, 2023 at 01:08:29PM +0100, Frank Oltmanns wrote:
>> In contrast to the JH057N panel, the XBD599 panel does not require a 20
>> m
in a delay. The empty function I used has no side effect on that panel.
The patch is based on drm-next.
Ondřej, since this is just a refactoring, I would gladly add your SoB,
if you wish so.
Thanks,
Frank
Frank Oltmanns (1):
drm/panel: st7703: Fix resume of XBD599 panel
drivers/gpu/drm/panel
This patch fixes intermittent panel initialization failures and screen
corruption during resume from sleep on panel xingbangda,xbd599 (e.g.
used in PinePhone).
It was originally submitted by Ondrej Jirman in July 2020:
https://lore.kernel.org/all/20200716123753.3552425-1-meg...@megous.com/
The
functions for the delays.
The XDB599 does not require a 20 msec delay between the SETBGP and
SETVCOM commands. Therefore, remove the delay from the device specific
initialization function.
Signed-off-by: Frank Oltmanns
Cc: Ondrej Jirman
Reported-by: Samuel Holland
---
drivers/gpu/drm/panel/panel
the power supplies
some time to reach the required voltage, too.
This fixes intermittent panel initialization failures and screen
corruption during resume from sleep on panel xingbangda,xbd599 (e.g.
used in PinePhone).
Signed-off-by: Ondrej Jirman
Signed-off-by: Frank Oltmanns
Reported-by: Samuel
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