Add CRC support to DPU, which is currently not supported by
this driver. Only supports CRC for CRTC for now, but will extend support
to other blocks later on.
Tested on Qualcomm RB3 (debian, sdm845)
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 169
Move initialization of sblk in _sspp_subblk_offset() after NULL check to
avoid potential NULL pointer dereference.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Reported-by: Dan Carpenter
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 8 +
Add NULL checks in KMS CRTC funcs to avoid potential NULL
dereference.
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Reported-by: Dan Carpenter
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 8
drivers/gpu/drm/msm/disp/dpu1/
Change byte_clk_rate, pixel_clk_rate, esc_clk_rate, and src_clk_rate
from u32 to unsigned long, since clk_get_rate() returns an unsigned long.
Fixes: a6bcddbc2ee1 ("drm/msm: dsi: Handle dual-channel for 6G as well")
Reported-by: Dan Carpenter
Signed-off-by: Jessica Zhang
---
drive
On 10/16/2021 12:35 PM, Dan Carpenter wrote:
On Fri, Oct 15, 2021 at 12:34:20PM -0700, Jessica Zhang wrote:
Hey Dmitry,
On 10/15/2021 11:24 AM, Dmitry Baryshkov wrote:
On Fri, 15 Oct 2021 at 04:43, Jessica Zhang wrote:
Hey Dan,
On 10/1/2021 5:31 AM, Dan Carpenter wrote:
Hello Sean Paul
debug->link->phy_params.p_level);
191 if (dp_debug_check_buffer_overflow(rc, _size, ))
192 goto error;
193
--> 194 if (copy_to_user(user_buff, buf, len))
This function does not take "count" into consideration so it can end
u
-by: Jessica Zhang
[1] Skipped on RB5 due to issue related to DPMS. Planning to upload a
fix for this in the future.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 153 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 19 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 56
^
Got it. I'll take care of the null pointer issues, but planning to
address the `(void)pe` issue in this patch:
https://patchwork.freedesktop.org/patch/456592/
Thanks,
Jessica Zhang
You should file a bug report with your compiler devs instead of adding
these sorts of stateme
c:2380 msm_dsi_host_power_on() warn:
missing error code 'ret'
Is there a specific .config you're using (that's not the default
mainline defconfig)? If so, can you please share it?
Thanks,
Jessica Zhang
regards,
dan carpenter
On 10/15/2021 1:12 AM, Dan Carpenter wrote:
On Thu, Oct 14, 2021 at 06:43:22PM -0700, Jessica Zhang wrote:
Hey Dan,
On 10/1/2021 5:31 AM, Dan Carpenter wrote:
Hello Sean Paul,
The patch a6bcddbc2ee1: "drm/msm: dsi: Handle dual-channel for 6G as
well" from Jul 25, 2
Hey Dmitry,
On 10/15/2021 11:24 AM, Dmitry Baryshkov wrote:
On Fri, 15 Oct 2021 at 04:43, Jessica Zhang wrote:
Hey Dan,
On 10/1/2021 5:31 AM, Dan Carpenter wrote:
Hello Sean Paul,
The patch a6bcddbc2ee1: "drm/msm: dsi: Handle dual-channel for 6G as
well" from Jul 25, 2
On 10/11/2021 7:01 PM, Dmitry Baryshkov wrote:
On 12/10/2021 02:41, Jessica Zhang wrote:
Add CRC support to DPU, which is currently not supported by
this driver. Only supports CRC for CRTC for now, but will extend support
to other blocks later on.
Tested on Qualcomm RB3 (debian, sdm845
expansion
of macro ‘static_assert’
192 | static_assert(ARRAY_SIZE(crcs) ==
ARRAY_SIZE(crtc_state->mixers));
| ^
Can be fixed by moving the static_assert() before `crtc_state = ...`
Thanks,
Jessica Zhang
/* Skip first 2 frames in case of "uncooked"
On 10/22/2021 10:20 AM, Rob Clark wrote:
From: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1
r DPU")
Signed-off-by: Rob Clark
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0a
y: Nathan Chancellor
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 2523e829f485..967245b8cc02 100644
--- a/drivers/gpu/drm/msm/
implementation is unchanged for now.
Signed-off-by: Dmitry Baryshkov
Tested-by: Jessica Zhang # RB3 (sdm845) and
RB5 (qrb5165)
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 24 ++-
drivers/gpu/drm
On 1/31/2022 1:05 PM, Dmitry Baryshkov wrote:
In order to simplify DP code, drop hand-coded loops over clock arrays,
replacing them with clk_bulk_* functions.
Signed-off-by: Dmitry Baryshkov
Tested-by: Jessica Zhang # RB3 (sdm845) and
RB5 (qrb5165)
Reviewed-by: Jessica Zhang
.h
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 3172da089421..094b39bfed8c 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -10,7 +10,7 @@
#include
#include
-#include "dpu_io_util.h"
+#include "dp_clk_util.h"
#include "
implementation is unchanged for now.
Signed-off-by: Dmitry Baryshkov
Tested on: Qualcomm RB3 (debian, sdm845), Qualcomm RB5 (debian, qrb5165)
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 24 ++-
drivers
On 1/19/2022 2:16 PM, Dmitry Baryshkov wrote:
Move clock/IO/hrtimer utility functions from msm_drv.c to new
msm_io_utils.c file.
Signed-off-by: Dmitry Baryshkov
Tested on: Qualcomm RB3 (debian, sdm845), Qualcomm RB5 (debian, qrb5165)
Reviewed-by: Jessica Zhang
---
drivers/gpu/drm
.prepare = 50, /* T2 */
+ .enable = 200, /* T3 */
+ .disable = 110, /* T10 */
+ .unprepare = 1000, /* T13 */
The inclusion of the comments seems unnecessary.
Thanks,
Jessica Zhang
+ },
this LGTM.
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
Signed-off-by: Ruihai Zhou
---
This patch base on original fixes series [1]
[1]
https://patchwork.kernel.org/project/dri-devel/cover/20230703-fix-boe-tv101wum-nl6-v3-0-bd6e9432c...@linaro.org/
---
drivers/gpu/drm/panel/panel-boe-tv10
e function? Otherwise this throws a
compiler warning.
With that change,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
+
+ for (i = 0; i < panel_regs_len; i++) {
+ err = mipi_dbi_command(dbi, panel_regs[i].cmd,
+ panel_regs
On 9/11/2023 2:02 AM, John Watts wrote:
SPI drivers needs their own list of compatible device IDs in order
for automatic module loading to work. Add those for this driver.
Hi John,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
Signed-off-by: John Watts
---
drivers/gpu/drm/panel
As I participate more actively in the drm/panel subsystem, I would
like to get notified about new changes in this area.
Since I have contributed and continue to contribute to drm/panel,
add myself as a reviewer for the DRM panel drivers to help the review
process
Signed-off-by: Jessica Zhang
On 9/13/2023 9:09 PM, John Watts wrote:
On Wed, Sep 13, 2023 at 02:34:38PM -0700, Jessica Zhang wrote:
Hi John,
Having a separate panel_regs_len field seems a bit unnecessary to me.
Looks like it's only being called in the panel prepare() and I don't seen
any reason why we shouldn't just
On 9/13/2023 9:12 PM, John Watts wrote:
On Wed, Sep 13, 2023 at 02:43:43PM -0700, Jessica Zhang wrote:
Hi John,
Just curious, what do you mean by these registers being mostly unknown?
I do see them specified in the online specs -- some even seem to map to
existing MIPI_DCS_* enums (ex
() and I don't
seen any reason why we shouldn't just call the ARRAY_SIZE() macro there.
Thanks,
Jessica Zhang
};
struct nv3052c {
@@ -36,12 +43,7 @@ struct nv3052c {
struct gpio_desc *reset_gpio;
};
-struct nv3052c_reg {
- u8 cmd;
- u8 val;
-};
-
-static const
John,
Just curious, what do you mean by these registers being mostly unknown?
I do see them specified in the online specs -- some even seem to map to
existing MIPI_DCS_* enums (ex. 0x01 to MIPI_DCS_SOFT_RESET, and 0x04 to
MIPI_DCS_GET_DISPLAY_ID).
Thanks,
Jessica Zhang
{ 0xe3, 0x00
On 9/24/2023 3:23 AM, Dmitry Baryshkov wrote:
On 22/09/2023 20:49, Jessica Zhang wrote:
On 8/29/2023 1:22 AM, Pekka Paalanen wrote:
On Mon, 28 Aug 2023 17:05:13 -0700
Jessica Zhang wrote:
Loosen the requirements for atomic and legacy commit so that, in cases
where pixel_source != FB
must be NONE or the FB must be NULL
if pixel_source == FB.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 21 ++--
drivers/gpu/drm/drm_atomic_helper.c | 39 +
include/drm/drm_atomic_helper.h | 4 ++--
include/drm
Add solid_fill property data to the atomic plane state dump.
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_plane.c | 8
include/drm/drm_plane.h | 3
lid_fill_blob) checks to helper method
(Dmitry)
- Fixed dropped 'const' warning
- Added helper to convert color fill to BGR888 (Rob)
- Fixed indentation issue (Dmitry)
- Added support for solid fill on planes of varying sizes
---
Jessica Zhang (10):
drm: Introduce pixel_source DRM plane proper
Currently framebuffer checks happen directly in
drm_atomic_plane_check(). Move these checks into their own helper
method.
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 130
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++
drivers/gpu/drm/drm_blend.c | 94 +++
drivers/gpu/drm/drm_plane.c | 19 +--
include/drm/drm_blend.h
to configure the alpha value for the solid fill color.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 38 ---
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
,
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
Signed-off-by: John Watts
---
.../gpu/drm/panel/panel-newvision-nv3052c.c | 24 ---
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
b/drivers/gpu/drm/panel/panel
[1] https://patchwork.freedesktop.org/patch/30/
Tested-by: Jessica Zhang # SC7280
Fixes: bfcc3d8f94f4 ("drm/msm/dp: support setting the DP subconnector type")
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_drm.c | 3 +++
1 file changed, 3
he DP subconnector type")
Signed-off-by: Abel Vesa
Signed-off-by: Dmitry Baryshkov
Tested-by: Jessica Zhang # SC7280
---
drivers/gpu/drm/msm/dp/dp_display.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/g
On 11/2/2023 11:19 AM, Clayton Craft wrote:
This panel is found on laptops e.g., variants of the Thinkpad X13s.
Configuration was collected from the panel's EDID.
Signed-off-by: Clayton Craft
LGTM
Reviewed-by: Jessica Zhang
Thanks,
Jessica Zhang
---
V2: renamed to "*_mode&q
state before the
lcm_reset pin is pulled high.
Was this fixing some panel issue? If so, maybe we can add
Fixes: 6069b66cd962 ("drm/panel: support for STARRY 2081101QFH032011-53G
MIPI-DSI panel")
Otherwise, with the commit msg fix, this looks good to me:
Reviewed-by: Jessica Zhan
On 11/6/2023 9:35 AM, Jessica Zhang wrote:
On 11/4/2023 6:02 AM, Helen Koike wrote:
Hi Jessica,
On 10/10/2023 19:25, Jessica Zhang wrote:
Recently, we've registered a Gitlab runner for a Qualcomm RB5 device
that will be
hosted and maintained in Qualcomm labs.
This series will add
it easier to extend.
Otherwise, can you change the name to "*_mode"? Seems to me that almost
all other panels with a single mode have the name as "*_mode" with the
only exception being a carry-over from older panel-simple.c code.
Thanks,
Jessica Zhang
+ .clock = 15776
On 11/4/2023 6:02 AM, Helen Koike wrote:
Hi Jessica,
On 10/10/2023 19:25, Jessica Zhang wrote:
Recently, we've registered a Gitlab runner for a Qualcomm RB5 device
that will be
hosted and maintained in Qualcomm labs.
This series will add a corresponding CI job for testing SM8250 devices
or example [1]:
Fixes: 01d6c3578379 ("drm/syncobj: add support for timeline point wait v8")
Signed-off-by: Erik Kurzinger
<...>
Thanks,
Jessica Zhang
[1]
https://cgit.freedesktop.org/drm/drm-misc/commit/?h=drm-misc-fixes=101c9f637efa1655f55876644d4439e552267527
Thanks
O
On 10/20/2023 8:02 AM, Chris Morgan wrote:
On Thu, Oct 19, 2023 at 10:22:24AM -0700, Jessica Zhang wrote:
On 10/18/2023 9:18 AM, Chris Morgan wrote:
From: Chris Morgan
Refactor the driver to add support for the powkiddy,rk2023-panel
panel. This panel is extremely similar to the rg353p
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++-
drivers/gpu/drm/msm/disp/dpu1
n:
struct drm_mode_solid_fill {
u32 r, g, b, pad;
};
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9
drivers/gpu/drm/drm_atomic_uapi.c | 26 ++
drivers/gpu/drm/d
Add "SOLID_FILL" as a valid pixel source. If the pixel_source property is
set to "SOLID_FILL", it will display data from the drm_plane "solid_fill"
blob property.
Reviewed-by: Dmitry Baryshkov
Acked-by: Pekka Paalanen
Acked-by: Harry Wentland
Acked-by: Sebastia
Add solid_fill and pixel_source properties to DPU plane
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1
Add pixel source to the atomic plane state dump
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_blend.c | 1 +
drivers/gpu/drm/drm_crtc_internal.h | 1 +
3
On 9/24/2023 3:29 AM, Dmitry Baryshkov wrote:
On 29/08/2023 03:05, Jessica Zhang wrote:
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
On 9/24/2023 3:06 AM, Dmitry Baryshkov wrote:
On 29/08/2023 03:05, Jessica Zhang wrote:
Add support for pixel_source property to drm_plane and related
documentation. In addition, force pixel_source to
DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
legacy userspace
On 8/29/2023 1:22 AM, Pekka Paalanen wrote:
On Mon, 28 Aug 2023 17:05:13 -0700
Jessica Zhang wrote:
Loosen the requirements for atomic and legacy commit so that, in cases
where pixel_source != FB, the commit can still go through.
This includes adding framebuffer NULL checks in other areas
On 9/18/2023 5:58 AM, John Watts wrote:
This display is extremely similar to the LTK035C5444T, but still has
some minor variations in panel initialization.
Signed-off-by: John Watts
Reviewed-by: Jessica Zhang
---
.../gpu/drm/panel/panel-newvision-nv3052c.c | 223
On 9/18/2023 5:58 AM, John Watts wrote:
The panel needs us to wait 120ms between exiting and entering sleep.
Guarantee that by always waiting 150ms before entering sleep mode.
Hi John,
Same question as the last patch -- is this a fix for something?
Thanks,
Jessica Zhang
Signed-off
-by: John Watts
Hi John,
Just wondering, is there some context to this change? I.e., was this
made to fix a specific issue?
This seems like a pretty significant increase in wait time so, if it's
not a fix, I'm not sure if this would be an improvement on the current
behavior.
Thanks,
Jessica
mipi_dsi_generic_write_seq(ctx->dsi, 0xbd, 0x05);
+ usleep_range(1000, 2000);
Just to check my understanding of the comment here.. so the above DCS
command will set the panel to 90Hz, and if we change the parameter to
0x00, it will be set to 60Hz instead?
Thanks,
Jess
)
{
struct device *dev = >dev;
+ struct device_node *np = dev->of_node;
Hi Chris,
Thanks for the patch.
It mostly looks good to me, but just one question here -- why not pass
in `dev->of_node` directly into `of_device_is_compatible()`?
Thanks,
Jessica Zhang
struct panel_nv3
On 9/22/2023 10:12 AM, Helen Koike wrote:
Add job that runs igt on top of vkms.
Signed-off-by: Helen Koike
Tested-by: Jessica Zhang
Acked-by: Jessica Zhang
---
See pipeline:
https://gitlab.freedesktop.org/helen.fornazier/linux/-/pipelines/990494
v2:
- do not mv modules to /lib
/cargo-installkNKRwf`
Caused by:
package `rustix v0.38.13` cannot be built because it requires rustc 1.63 or
newer, while the currently active rustc version is 1.60.0
A patch to Mesa was recently added fixing this error, so update it.
Signed-off-by: Helen Koike
Tested-by: Jessica Zhang
Acked
and all seem to work identical
to the 353 otherwise.
Hi Chris,
LGTM, thanks!
Reviewed-by: Jessica Zhang
BR,
Jessica Zhang
Signed-off-by: Chris Morgan
---
drivers/gpu/drm/panel/panel-newvision-nv3051d.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel
Set CONFIG_INTERCONNECT_QCOM_SM8250 needs to =y so that the ASIX AX88179
USB Ethernet driver can be probed in time to set up nfsroot.
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ci/arm64.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
.
For now, we will keep the job as manual trigger only and drop that rule later
after we stabilize the tests.
[1] https://gitlab.freedesktop.org/drm/msm/-/jobs/50092719
---
Jessica Zhang (3):
drm/ci: Add SM8250 job to CI
drm/ci: enable CONFIG_INTERCONNECT_QCOM_SM8250 for arm64 config
Add skips, fails and flakes for the SM8250 test.
Generated using update-xfails.py [1]
[1] https://patchwork.freedesktop.org/patch/561453/?series=124793=1
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ci/xfails/msm-sm8250-fails.txt | 29
and addressing some outstanding failures.
Signed-off-by: Abhinav Kumar
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/ci/build.sh | 1 +
drivers/gpu/drm/ci/test.yml | 15 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh
for the r66451 command mode panel though the drop reported here seems
more drastic.
I'll try recreating this on SM8550 MTP and investigate it.
Thanks,
Jessica Zhang
Neil
Depends on: "Add prepare_prev_first flag to Visionox VTDR6130" [1]
Changes since v1:
- Changed from email a
uot;, .data = _rgxx3_info },
+ { .compatible = "anbernic,rg351v-panel", .data = _rg351v_info },
+ { .compatible = "anbernic,rg353p-panel", .data = _rg353p_info },
+ { .compatible = "powkiddy,rk2023-panel", .data = _rk2023_info },
{ /* sentine
fore panel enable() by default. Any panel that needs DSI host to be
powered on later could then explicitly set the flag to false in their
respective drivers.
Thanks,
Jessica Zhang
I do not consider it's the right way to fix regression caused by [2]
I consider [2] should be reverted, panel
that this is a common change for a lot of patches in this series.
Thanks,
Jessica Zhang
+
#include "dpu_hwio.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_top.h"
@@ -268,16 +270,17 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
Currently framebuffer checks happen directly in
drm_atomic_plane_check(). Move these checks into their own helper
method.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 130 ---
1 file changed, 73 insertions
Add pixel source to the atomic plane state dump
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_blend.c | 1 +
drivers/gpu/drm/drm_crtc_internal.h | 1 +
3 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers
Add "SOLID_FILL" as a valid pixel source. If the pixel_source property is
set to "SOLID_FILL", it will display data from the drm_plane "solid_fill"
blob property.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_blend.c | 10 +
to configure the alpha value for the solid fill color.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 37 +--
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1
sources will be defined in the
drm_plane_pixel_source enum.
Currently, the only pixel sources are DRM_PLANE_PIXEL_SOURCE_FB (the
default value) and DRM_PLANE_PIXEL_SOURCE_NONE.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 1 +
drivers/gpu/drm/drm_atomic_uapi.c
include/drm/drm_plane.h | 90 ++
include/uapi/drm/drm_mode.h | 24 +
13 files changed, 478 insertions(+), 112 deletions(-)
---
base-commit: 00ee72279c963989ab435b0bc90b5dc05a9aab79
change-id: 20230404-solid-fill-05016175db36
Best regards,
--
Jessica Zhang
Add solid_fill property data to the atomic plane state dump.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_plane.c | 8
include/drm/drm_plane.h | 3 +++
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b
n:
struct drm_mode_solid_fill {
u32 r, g, b;
};
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic_state_helper.c | 9
drivers/gpu/drm/drm_atomic_uapi.c | 26 ++
drivers/gpu/drm/drm_blend.c | 30 ++
include/drm/d
must be NONE or the FB must be NULL
if pixel_source == FB.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 20 +++-
drivers/gpu/drm/drm_atomic_helper.c | 36
include/drm/drm_atomic_helper.h | 4 ++--
include/drm
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 ++-
drivers/gpu/drm/msm/disp/dpu1
Add solid_fill and pixel_source properties to DPU plane
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1
On 8/8/2023 3:57 PM, Jessica Zhang wrote:
On 8/7/2023 6:07 PM, Dmitry Baryshkov wrote:
On 8 August 2023 00:41:07 GMT+03:00, Jessica Zhang
wrote:
On 8/4/2023 6:27 AM, Dmitry Baryshkov wrote:
On Fri, 28 Jul 2023 at 20:03, Jessica Zhang
wrote:
Document and add support
DPU supports a data-bus widen mode for DSI INTF.
Enable this mode for all supported chipsets if widebus is enabled for DSI.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++
drivers
during runtime in the future.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1
Add a DATABUS_WIDEN bit to the MDP_CTRL2 register to allow DSI to enable
databus widen mode.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data instead of 24.
Enable this mode whenever DSC is enabled for supported chipsets.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/dsi/dsi.c | 2 +-
drivers/gpu/drm/msm/dsi/dsi.h | 1
org/r/20230525-add-widebus-support-v1-0-c7069f2ef...@quicinc.com
---
Jessica Zhang (4):
drm/msm/dpu: Move setting of dpu_enc::wide_bus_en to atomic enable()
drm/msm/dpu: Enable widebus for DSI INTF
drm/msm/dsi: Add DATABUS_WIDEN MDP_CTRL2 bit
drm/msm/dsi: Enable widebus for
(55938): []
__do_softirq+0x1e8/0x480
[ 3092.848256] softirqs last disabled at (55923): []
__irq_exit_rcu+0xdc/0x140
[ 3092.857022] ---[ end trace ]---
Thanks,
Jessica Zhang
Cc: "Kazlauskas, Nicholas"
Cc: Dmitry Osipenko
Signed-off-by: Daniel Vetter
---
is patch since the line of
code that was failing is no longer present in the kernel.
Fixes: a670ff578f1f ("drm/msm/dpu: always use mdp device to scale bandwidth")
Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for
display")
Signed-off-by: Douglas Ande
test starts skipping now whereas
it was previously passing.
Restore DRM_MODE_ROTATE_180 bit to the supported rotations
list.
Fixes: dabfdd89eaa92 ("add inline rotation support for sc7280")
Signed-off-by: Abhinav Kumar
Tested-by: Jessica Zhang # Trogdor (SC8170)
---
drivers/gpu/dr
writeback modes according to max_linewidth to allow
even compositors/clients which use only a single SSPP to
use writeback.
Fixes: 77b001acdcfeb ("drm/msm/dpu: add the writeback connector layer")
Reported-by: Jessica Zhang
Tested-by: Jessica Zhang # Trogdor (SC8170)
Signed-off-by: Abh
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 43 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h| 3 +
drivers/gpu/drm
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 ++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu
Refactor existing CRC code for layer mixer and add CRC support for interface
blocks
Jessica Zhang (3):
drm/msm/dpu: Separate LM-specific CRC code from generic CRC code
drm/msm/dpu: Add MISR register support for interface
drm/msm/dpu: Add interface support for CRC debugfs
drivers/gpu/drm
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 72
On 5/27/2022 12:38 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for setting MISR registers within the interface
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 55 -
drivers/gpu/drm/msm/disp/dpu1
On 5/27/2022 12:46 PM, Dmitry Baryshkov wrote:
On 27/05/2022 21:54, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1
On 6/20/2022 11:42 PM, Dmitry Baryshkov wrote:
On Tue, 21 Jun 2022 at 03:50, Jessica Zhang wrote:
Move layer mixer-specific section of dpu_crtc_get_crc() into a separate
helper method. This way, we can make it easier to get CRCs from other HW
blocks by adding other get_crc helper methods
On 6/20/2022 11:36 PM, Dmitry Baryshkov wrote:
On Tue, 21 Jun 2022 at 03:50, Jessica Zhang wrote:
Add support for writing CRC values for the interface block to
the debugfs by calling the necessary MISR setup/collect methods.
Changes since V1:
- Set values_cnt to only include phys
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