Hi All,
This question has to do with the Radeon 8800 drivers that ATI
just released. I know that they were written by ATI, but I have a question
that I believe is an DRI questions.
1) We have 15 identical machines each with a Radeon 8500.
Intermittently, DRI will
Hi All, I know that this topic has come up many times in the past, but here goes. I'm one of the poor schleps with a XPRESS 200M in my Compaq laptop. The open-source driver doesn't support it, and the latest fglrx driver just hangs upon X startup.
So... I want to try to fix this. From the DRI
Alex, Thanks for answering my questions. Sorry I'm a little slow to respond. I can usually only work on this when everyone in the house is asleep. (That doesn't come that often..)
You'd probably want to configure the MC in the DDX (xf86-video-ati)although you may have to coordinate with the drm
Alex, I was able to get the latest and greatest of everything compiled and limping. X starts up, and then proceeds to consume 100% of the CPU. I have a good debugging environment, so I'll be able to walk through it with gdb to figure out exactly what's causing the problem. Once it gets in this
Alex, (II) resource ranges after probing:
DRI broken:[33] 00 0x03b0 - 0x03bb (0xc) IS[B][34] 00 0x03c0 - 0x03df (0x20) IS[B] ... fglrx:[34] 00 0xb01203b0 - 0xb01203bb (0xc) IS[B]
[35] 00 0xb01203c0 - 0xb01203df (0x20) IS[B] 1) What are these mappings used for?Not sure.Possibly
Alex, On 11/1/06, Alex Deucher [EMAIL PROTECTED] wrote:
Sorry for the delay in response.No problem. I appreciate the responses.
These are what the bits in the RBBM_STATUS register mean for r300(XPRESS may differ slightly)6:0Available slots in the FIFO 8Host Interface active 9CP request active10
Roland,
On 11/21/06, Roland Scheidegger [EMAIL PROTECTED] wrote:
Phillip Ezolt wrote:
It does get recognized as PCI. However, I had to force it PCIE.
(using OptionBusType PCIE). These cards are definately
PCIE, so the original detection was wrong.
I wonder
where to look to find and help these others ?
What needs to be done ? I've read about some registers that would be
incorrects...
You should drop Phillip Ezolt a line, as he has been trying to debug the
issue. You can reach him thru this list or [EMAIL PROTECTED]
Regards
Erik Andrén
Thanks
Stephane,
What tools do you use for tracing? I know that you have the renouveau
tool and libsegfault.
I'm hacking on the ATI stuff, and it would be handy to have code which can
just out what MMIO writes the kernel driver is doing. Do you guys have
anything to do that?
Cheers,
--Phil
On
Jerome,
I've put up some info about my Radeon 200M status:
http://dri.freedesktop.org/wiki/Radeon200M
I need to add more stuff, but it is a start.
Cheers,
--Phil
On 1/11/07, Jerome Glisse [EMAIL PROTECTED] wrote:
Hi all,
I have setup a page on the DRI wiki:
Hi All,
I've been hacking away at the 200M driver without much success, and would
like to hear if other people with more radeon experience can help me. I have
things setup to use 128M of the sideport memory (and nothing else). I've
been both userspace (libsegfault) and kernelspace (kmmio)
Michel,
On 1/12/07, Michel Dänzer [EMAIL PROTECTED] wrote:
4) Is there a simple command that I can issue to the CP to clear the
screen JUST to see if it is issuing any commands from the ring buffer
at all?
You could do something along the lines of radeon_test_writeback: write
to a
Jerome,
On 1/13/07, Jerome Glisse [EMAIL PROTECTED] wrote:
Is it something like this:
BEGIN_RING(2);
OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG5, 0 ) );\
OUT_RING( 0xDEADBEEF); \
ADVANCE_RING()
COMMIT_RING()
Should be do the work, then you read the
Alex,
On 1/15/07, Alex Deucher [EMAIL PROTECTED] wrote:
On 1/15/07, Phillip Ezolt [EMAIL PROTECTED] wrote:
Jerome,
On 1/13/07, Jerome Glisse [EMAIL PROTECTED] wrote:
Is it something like this:
BEGIN_RING(2);
OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG5, 0
Dave,
On 1/15/07, Dave Airlie [EMAIL PROTECTED] wrote:
...
I did a little more digging on this. It really looks like the address
of
ring.start is completely different than what is in
RADEON_CP_RB_BASE. (I
realize that ring.start is a virtual address and RADEON_CP_RB_BASE is a
bus
Roland,
On 1/16/07, Roland Scheidegger [EMAIL PROTECTED] wrote:
Phillip Ezolt wrote:
(A simple explanation about the view of memory from the graphics card
vs. the system would be helpful. I found the following, but I could use
more details:
http://lists.freedesktop.org/archives/xorg/2005
Dave,
On 2/20/07, Dave Airlie [EMAIL PROTECTED] wrote:
How is your card configured?
No on-board RAM.. just UMA... 32MB setup by BIOS..
Hmm. Then our setup is a bit different.
After looking at the debug output from the fglrx 8.32.5 driver, I think
that
there is a GART table at the
Dave,
On 2/21/07, Dave Airlie [EMAIL PROTECTED] wrote:
Can you dump that memory area? see if it has a GART table in it.. GART
tables usually are fairly easy to spot lots of page pointers..
Ok. More digging.
It looks like the area from 0xCFFE - 0xCFFF is not the GART table.
Nigel,
On 2/21/07, Nigel Cunningham [EMAIL PROTECTED] wrote:
Hi guys.
I was wondering this morning, could it potentially help to dump the
contents of the memory that fglrx allocates when the driver is
suspended? I have a 200M as well (same 32MB config as you, Dave), and so
could see what I
Dave,
I turned on PC recording in kmmio. It reveals some interesting things
about what those indirect memory accesses are doing. First, all of the
calls to the 168/16C registers are in: MCIL_ModifyRegister (So it looks like
this is the Memory Controller that it is accessing.)
Next, I recorded
Dave,
On 3/4/07, Dave Airlie [EMAIL PROTECTED] wrote:
only enough to map 512k... (Also, the addresses are stored in big
endian.. I
think.) I might be interesting to actually look at what is in these
addresses.
That mght make sense on your card as you have actual RAM, the GART is
On 3/5/07, Phillip Ezolt [EMAIL PROTECTED] wrote:
Dave,
On 3/4/07, Dave Airlie [EMAIL PROTECTED] wrote:
only enough to map 512k... (Also, the addresses are stored in big
endian.. I
think.) I might be interesting to actually look at what is in these
addresses.
That mght make sense
Dave,
On 3/4/07, Dave Airlie [EMAIL PROTECTED] wrote:
Have you done this yet? I'd be interested in finding out how the
entries
in the table map to memory space.. there are two mappings types sso
far,
PCI and PCIE... PCI is just the bus addres, PCIE is bus address 8 |
0xc..
On 3/12/07, Daniel Stone [EMAIL PROTECTED] wrote:
On Mon, Mar 12, 2007 at 09:35:43AM -0400, Phillip Ezolt wrote:
So, if you compare the first and last column, you can see the equation
is:
address in table = (bus_address 0xc);
I modified the gart code to allocate a table in RAM
Hi,
Is there a simple way for me to test whether the GART is working on a
radeon driver?
I'm hacking the Radeon 200M, and I think that I've setup the GART properly.
(unfortunately, the CP still doesn't work...)
Is there a way for me to test if the memory is mapped in properly?
Ideally, I
Dave Roland,
On 4/9/07, Roland Scheidegger [EMAIL PROTECTED] wrote:
Dave Airlie wrote:
Okay the GART is working fine on the rs480 from my branch,
Congratulations on getting it to work. I've tested your DRM branch on my
HP laptop with a 200M, and it works. (128M of video RAM, 0
On 4/9/07, Zoltan Boszormenyi [EMAIL PROTECTED] wrote:
Hi,
Dave Airlie írta:
Okay the GART is working fine on the rs480 from my branch, however the
Congrats!
r300 driver causes a chip lockup, I've loaded fglrx and from what I can
see it disables the Vertex Shaders in hw and does that
Oliver Dave,
You maybe have missed out on #dri-devel on freenode irc, it works
reasonably well for getting insta-answers depending on timezone etc..
Ah. I HAVE missed that. I'll have to hang out there. I usually have
the wireless network turned off when I'm X hacking, but this gives me
a
Oliver,
On 4/26/07, Oliver McFadden [EMAIL PROTECTED] wrote:
Currently this is hard-coded, because I haven't done dynamic calculation of
those variables yet.
You can determine REG_ADDR from lspci -v; you want the line that matches
(32-bit, non-prefetchable) [size=64K]. In the following
Dave,
So I tested the (git from last night 5/10) the latest code
(x+mesa+drm) on my RS480
In general, things are MUCH better, but I was running through the
sample programs in Mesa, and I found some remaining issues. I ran the
tests on fglrx, took some screenshots, and compared them to the R300
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