> the above three lines are redundant.
> OK with those removed.
Got it, will commit it after no surprise in test for removal.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 23, 2024 7:49 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; k
55;
return _2;
}
-Original Message-
From: Li, Pan2
Sent: Thursday, May 23, 2024 12:17 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; pins...@gmail.com
Subject: RE: [PATCH v2] Match: Support __builtin_add_overf
.
Not sure if my understanding is correct or not, thanks again for help.
#define SAT_ADD_U_1(T) \
T sat_add_u_1_##T(T x, T y) \
{ \
return (T)(x + y) >= x ? (x + y) : -1; \
}
SAT_ADD_U_1(uint8_t);
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, May 22, 2024 9:14 PM
To: Li,
Thanks Richard for comments, will merge the rest form of .SAT_ADD in one middle
end patch for fully picture, as well as comments addressing.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, May 22, 2024 9:16 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, May 22, 2024 9:04 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; pins...@gmail.com
Subject: Re: [PATCH v2] Match: Extract integer_types_ternary_match helpe
a better understanding for this.
Pan
-Original Message-
From: Andrew Pinski
Sent: Tuesday, May 21, 2024 8:34 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Christina ;
Richard Guenther
Subject: Re: [PATCH v1 1/2] Match: Support __builtin_add_overflow branch form
for unsigne
tial idea is to catch both the (IFN_ADD_OVERFLOW @0 @1) and
(IFN_ADD_OVERFLOW @1 @0).
It is unnecessary if IFN_ADD_OVERFLOW takes care of this already.
Pan
From: Andrew Pinski
Sent: Tuesday, May 21, 2024 7:40 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Christina ;
Richard
> Thanks, looks good to me! You still need approval from a maintainer..
Thanks Tamar, let's wait for a while, !
Pan
-Original Message-
From: Tamar Christina
Sent: Tuesday, May 21, 2024 11:19 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.
ina
Sent: Monday, May 20, 2024 7:20 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: RE: [PATCH v1] Match: Extract integer_types_ternary_match helper to
avoid code dup [NFC]
> -Original Message-
> F
Thanks Andrew for comments, updated in v2.
Pan
From: Andrew Pinski
Sent: Sunday, May 19, 2024 12:25 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Cheng ; Tamar Christina ;
Richard Guenther
Subject: Re: [PATCH v1] Match: Extract integer_types_ternary_match helper to
avoid code dup [NFC
Committed, thanks Jeff. Let's wait for a while before backporting.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, May 20, 2024 12:23 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu, Hongtao
; richard.guent...@gmail.com
Subject: Re
Thanks for quick response, !
Pan
-Original Message-
From: Eric Botcazou
Sent: Sunday, May 19, 2024 5:40 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Robin
Dapp ; Jeff Law
Subject: Re: [PATCH] Add widening expansion of MULT_HIGHPART_EXPR
Hi Botcazou,
Just notice that this patch may result in some ICE when build libc++ for the
riscv port, details as below.
Please note not all configuration can reproduce this issue, feel free to ping
me if you cannot reproduce this issue. CC more riscv port people for awareness.
during GIMPLE
Thanks Tamer for enlightening, will have a try for the ingenious idea!
Pan
-Original Message-
From: Tamar Christina
Sent: Friday, May 17, 2024 10:46 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Committed with more comments, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, May 18, 2024 3:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v6] RISC-V: Implement IFN SAT_ADD
741824]:
# _2 = PHI <65535(2), _1(3)>
return _2;
}
Pan
-Original Message-
From: Tamar Christina
Sent: Wednesday, May 15, 2024 5:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 16, 2024 8:19 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; tamar.christina
; Richard Biener ;
richard.sandiford ; Li, Pan2
Subject: Re: [PATCH v2 3/3] RISC-V: Enable vectorizable early exit testsuite
RISC-V part
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 16, 2024 8:19 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; tamar.christina
; Richard Biener ;
richard.sandiford ; Li, Pan2
Subject: Re: [PATCH v2 2/3] RISC-V: Implement vectorizable early exit with
vcond_mask_len
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 8:13 PM
To: Tamar Christina
Cc: Li, Pan2 ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Richard Sandiford
Subject: Re: [PATCH v2 1/3] Vect: Support loop len
> For the series, the riscv specific part of course needs riscv approval.
Thanks a lot, have a nice day!
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 7:59 PM
To: Li, Pan2
Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito
> OK.
Thanks Richard for help and coaching. To double confirm, are you OK with this
patch only or for the series patch(es) of SAT middle-end?
Thanks again for reviewing and suggestions.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, May 16, 2024 4:10 PM
To: Li, Pan2
Kindly ping, looks no build error from Linaro for arm.
Pan
-Original Message-
From: Li, Pan2
Sent: Friday, May 3, 2024 9:52 AM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu,
Hongtao ; richard.guent...@gmail.com; Li, Pan2
> LGTM but you'll need an OK from Richard,
> Thanks for working on this!
Thanks Tamar for help and coaching, let's wait Richard for a while,!
Pan
-Original Message-
From: Tamar Christina
Sent: Wednesday, May 15, 2024 5:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: ju
Yes, we can add it back in future if we really changed cfg, will update in v5
(include vect patch 2/3) after all test passed.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, May 14, 2024 9:18 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.
It
> also fits better
> In the existing code.
Ack, will follow the existing code.
Pan
-Original Message-
From: Tamar Christina
Sent: Monday, May 13, 2024 11:03 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu
Ack, thanks Jeff and will fix it ASAP.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, May 14, 2024 2:10 AM
To: Li, Pan2 ; Kito Cheng ;
juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16
scalar
On 5/13/24 9:00 AM
Committed, thanks Juzhe and Kito. Let's wait for a while before backport to 14.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, May 13, 2024 10:11 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16
From: Tamar Christina
Sent: Monday, May 13, 2024 5:10 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v4 1/3] Internal-fn: Support new IFN SAT_ADD for unsigned
scalar int
Hi Pan,
>
Sure thing, see below PR.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Pan
From: Vladimir Makarov
Sent: Thursday, May 9, 2024 8:21 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Subject: Re: [pushed][PR114810][LRA]: Recognize alternatives with lack of
available registers for insn and demote
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 9, 2024 5:05 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for
optimization
lgtm
juzhe.zh...@rivai.ai
CC more RISC-V port people for awareness.
Pan
From: Li, Pan2
Sent: Thursday, May 9, 2024 11:25 AM
To: Vladimir Makarov ; gcc-patches@gcc.gnu.org
Subject: RE: [pushed][PR114810][LRA]: Recognize alternatives with lack of
available registers for insn and demote them.
Hi Vladimir,
Looks
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel
free to ping me if more information is needed for reproducing.
= Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
Try to invoke validate_subreg directly in v4 as below.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650596.html
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, April 30, 2024 7:36 PM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch
-Original Message-
From: Tamar Christina
Sent: Thursday, May 2, 2024 8:58 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v3] Internal-fn: Introduce new internal function SAT_ADD
>
-Original Message-
From: Tamar Christina
Sent: Thursday, May 2, 2024 11:26 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v3] Internal-fn: Introduce new internal function SAT_ADD
>
the cheaper check so perform it early.
Sure thing.
Thanks again and will send the v4 with all comments addressed, as well as the
test results.
Pan
-Original Message-
From: Tamar Christina
Sent: Thursday, May 2, 2024 1:06 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.a
REGMODE_NATURAL_SIZE(MODE)
sparc_regmode_natural_size (MODE)
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, April 30, 2024 3:17 PM
To: gcc-patches@gcc.gnu.org
Cc: jeffreya...@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Liu,
Hongtao ; richard.guent...@gmail.com; Li
anks Jeff, I will prepare a v3 for this with full and well tested results.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, April 29, 2024 11:20 PM
To: Li, Pan2 ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Ya
Committed to trunk, thanks Kito.
Backported to releases/gcc-14, thanks Jakub.
Pan
-Original Message-
From: Jakub Jelinek
Sent: Monday, April 29, 2024 3:53 PM
To: Kito Cheng
Cc: Li, Pan2 ; Jeff Law ;
gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai
Subject: Re: [PATCH v2] RISC-V: Fix
Thanks Kito, sent v2 for addressing comments.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, April 29, 2024 2:37 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg
const_poly_move
> diff --git a/
Kindly ping^^ for this ice fix.
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, April 18, 2024 9:46 AM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Liu, Hongtao
Subject: RE: [PATCH v2] DSE
Kinding ping for SAT_ADD.
Pan
-Original Message-
From: Li, Pan2
Sent: Sunday, April 7, 2024 3:03 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Wang, Yanzhang
; tamar.christ...@arm.com; richard.guent...@gmail.com;
Liu, Hongtao ; Li, Pan2
Subject
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, April 25, 2024 5:27 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2 ; Kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
LGTM. THANKS
Committed, thanks Kito and Juzhe.
Pan
From: Kito Cheng
Sent: Thursday, April 25, 2024 11:19 AM
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart register
overlap of vwcvt
LGTM
juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai
Committed, thanks Kito and Juzhe.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, April 25, 2024 2:24 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
LGTM, thanks :)
On Thu, Apr 25
rue currently.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 10:38 PM
To: Robin Dapp ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: RE: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> Just notice
Sent: Wednesday, April 24, 2024 10:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> (define_insn "@pred_vwsll_scalar"
>
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, April 24, 2024 9:11 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt&q
Request review as this revert patch contains some manually resolved conflict
changes.
Passed the rv64gcv fully regression test with isl build.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 8:59 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, April 24, 2024 2:46 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of
vext.vf
LGTM
ARGET="-O0 -g"
make -j $(nproc) all-gcc && make install-gcc
3. ../__RISC-V_INSTALL___RV64/bin/riscv64-unknown-elf-gcc
gcc/testsuite/gcc.dg/graphite/pr111878.c -O3 -fgraphite-identity
-fsave-optimization-record -march=rv64gcv -mabi=lp64d -c -S -o -
Pan
-Original Message
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, April 23, 2024 8:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d
and e65aaf8efe1
This patch
From: Palmer Dabbelt
Sent: Tuesday, April 23, 2024 8:43 AM
To: juzhe.zh...@rivai.ai
Cc: Patrick O'Neill ; Li, Pan2 ; Robin
Dapp ; gcc-patches@gcc.gnu.org; Kito Cheng
Subject: Re: Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and
xfail tests
On Mon, 22 Apr 2024 15:07:59 PDT (-0700),
Sure thing. Sorry for that Fortran is not fully tested for this change, will
take a look into it ASAP.
Pan
From: 钟居哲
Sent: Tuesday, April 23, 2024 6:06 AM
To: patrick ; Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc
Subject: Re: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 2:40 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 11:49 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for widening register
overlap of vf4/vf8
LGTM
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Sunday, April 21, 2024 7:59 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
lgtm
juzhe.zh...@rivai.ai
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, April 20, 2024 7:46 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Add xfail test case for wv insn highest
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Saturday, April 20, 2024 9:20 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
LGTM.
juzhe.zh
3b2799b872 and then file the patch for the xfail tests.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, April 19, 2024 10:54 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Revert RVV
Kindly ping^ for this ice fix.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, April 6, 2024 8:02 PM
To: Li, Pan2 ; Jeff Law ; Robin Dapp
; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
Subject
Message-
From: Li, Pan2
Sent: Friday, April 12, 2024 6:58 PM
To: Kito Cheng
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: RE: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Sure thing, the FP_RETURN only acts on ABI_xxx similar to below:
#define FP_RETURN
-
From: Kito Cheng
Sent: Friday, April 12, 2024 4:56 PM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to
compile that case without F
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, April 12, 2024 2:11 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
LGTM。
juzhe.zh
Thanks Edwin, should be one silly mistake, will fix it ASAP.
Pan
-Original Message-
From: Edwin Lu
Sent: Friday, April 12, 2024 5:20 AM
To: Li, Pan2 ; Bernd Edlinger ;
Kito Cheng ; juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return
, April 11, 2024 7:52 PM
To: Li, Pan2 ; Kito Cheng ;
juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode
switch
On 4/11/24 05:03, Li, Pan2 wrote:
> Committed, thanks Juzhe and Kito.
>
> Pan
Hi Pan,
this commit caused a
Committed, thanks Juzhe and Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, April 11, 2024 10:50 AM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode
switch
I was thinking we may guarded
Kindly ping for this ice.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, March 23, 2024 1:45 PM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
Subject: RE: [PATCH v2
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, March 31, 2024 9:05 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Fix misspelled term builtin in error message
lgtm
On Sat, Mar 30, 2024
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Sunday, March 31, 2024 8:54 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse
LGTM
On Sat, Mar 30
in v2.
Pan
-Original Message-
From: Li, Pan2
Sent: Thursday, March 28, 2024 3:32 PM
To: Kito Cheng
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: RE: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target
Thanks kito, looks missed this part in test,
Thanks kito, looks missed this part in test, let me check it out.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, March 28, 2024 2:44 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic
Committed, thanks kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Monday, March 25, 2024 8:04 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function
target("arch=+v")
LG
validate_subreg if read_mode size is < reg natural. */
+&& known_ge (GET_MODE_SIZE (read_mode), REGMODE_NATURAL_SIZE (read_mode)))
read_reg = gen_lowpart (read_mode, copy_rtx (store_info->rhs));
else
read_reg = extract_low_bits (read_mode, store_mode,
Pan
-Origin
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, March 22, 2024 6:06 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; rdapp@gmail.com; vine...@rivosinc.com;
pal...@rivosinc.com
Subject: Re: [PATCH v4] RISC-V
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, March 22, 2024 10:24 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v2] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
LG
Sorry for disturbing, kindly ping for this ICE.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, March 12, 2024 10:09 AM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
are of it for
risk control consideration.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, March 21, 2024 9:25 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; rdapp@gmail.com; vine...@rivosinc.com;
pal...@rivosinc.com
Subject: Re: [PATCH v3
Thanks Kito, will send v2 for this change.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, March 21, 2024 8:39 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("ar
Thanks Kito, will commit it after the ICE fix.
Pan
-Original Message-
From: Kito Cheng
Sent: Thursday, March 21, 2024 8:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Bugfix function target attribute pollution
dy.
Hi Kito
Could you please help to correct me the behavior of the riscv_rvv_vector_bits
attribute?
Sort of details and I suspect there is something missing, or different behavior
compared with clang side.
Pan
-Original Message-
From: Stefan O'Rear
Sent: Tuesday, March 12, 2024 9:
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, March 12, 2024 3:11 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]
LGTM :)
On Tue, Mar
Hi Jeff,
Is there any suggestion(s) for how to fix this ICE in the reasonable approach?
Thanks a lot.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, March 5, 2024 2:23 PM
To: Jeff Law ; Robin Dapp ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com
.
Pan
-Original Message-
From: Vineet Gupta
Sent: Thursday, March 7, 2024 3:19 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Wang, Yanzhang
; rdapp@gmail.com; pal...@rivosinc.com
Subject: Re: [PATCH v2] RISC-V: Introduce gcc att
essage-
From: Richard Biener
Sent: Monday, March 11, 2024 1:05 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Wang,
Yanzhang ; rdapp@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v2] VECT: Fix ICE for vectorizable LD/ST when both len and
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Sunday, March 10, 2024 2:53 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; Wang,
Yanzhang ; rdapp@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v2] VECT
allow assertion
during transform, to
see if there is any regressions and send the v2.
> It possibly was before Robins costing reorg?
Sorry, not very sure which commit from robin.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, March 8, 2024 10:03 PM
To: Li, Pan2
Cc: gc
Thanks a lot for coaching, really save my day. I will have a try for
usadd/ssadd includes both the scalar and vector (ISEL/widen_mult) modes in v3.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, March 7, 2024 4:41 PM
To: Li, Pan2
Cc: Tamar Christina ; gcc-patches
b;
}
sint32_t sat_abs (sint32_t a)
{
return a >= 0 ? a : (a == INT32_MIN ? INT32_MAX : -a);
}
Pan
-----Original Message-
From: Richard Biener
Sent: Tuesday, March 5, 2024 4:41 PM
To: Li, Pan2
Cc: Tamar Christina ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; Wang, Yanzhang ;
kito.c
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Tuesday, March 5, 2024 5:15 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Wang, Yanzhang
; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize
[NFC]
LGTM. Thanks for clean up
ond like below? I am debugging into
gimple_simplify_COND_EXPR for why not hit the pattern...
+(simplify
+ (cond
+(lt @0 integer_zerop)
+(plus:c @0 @1)
+(cond (lt @1 integer_zerop) @1 @0))
+ (IFN_SAT_ADD @0 @1))
Pan
-Original Message-
From: Richard Biener
Sent: Monday, March 4, 2024 6
cceptable fix, aka find some
where to filter-out the invalid
modes before goes to gen_low_part.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, March 4, 2024 6:47 AM
To: Robin Dapp ; Li, Pan2 ;
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rich
", '3', gen_intv_fp_libfunc)
OPTAB_VX(subv_optab, "sub$F$a3")
-OPTAB_NL(sssub_optab, "sssub$Q$a3", SS_MINUS, "sssub", '3',
gen_signed_fixed_libfunc)
-OPTAB_NL(ussub_optab, "ussub$Q$a3", US_MINUS, "ussub", '3',
gen_unsigned_fixed_libfunc)
+O
Robin Dapp
Sent: Thursday, February 29, 2024 9:29 PM
To: Li, Pan2 ; Jeff Law ;
gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
richard.guent...@gmail.com; Wang, Yanzhang ; Liu,
Hongtao
Subject: Re: [PATCH v2] DSE: Bugfix ICE after allow vector ty
Sure thing.
Pan
-Original Message-
From: Vineet Gupta
Sent: Saturday, March 2, 2024 3:00 AM
To: Li, Pan2 ; Kito Cheng ; 钟居哲
Cc: gcc-patches ; Wang, Yanzhang
; rdapp.gcc ; Jeff Law
Subject: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV
Hi Pan,
On 2/28/24 17
_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
}
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, February 29, 2024 1:33 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gm
To: 钟居哲
Cc: Li, Pan2 ; gcc-patches ; Wang,
Yanzhang ; rdapp.gcc ; Jeff Law
Subject: Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for
RVV
Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other two
if we think that might still useful? But anyway I have
ght behavior here, when mrvv-vector-bits is
given while riscv-autovec-preference is none...
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, February 28, 2024 8:57 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
; rdapp@gmail.com; jeffreya.
Updated in v3, please help to continue review below link. Sorry for sending
another v3 by mistake.
https://gcc.gnu.org/pipermail/gcc-patches/2024-February/646734.html
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, February 28, 2024 2:33 PM
To: Kito Cheng
Cc: gcc-patches
march=zvl* + mrvv-vector-bits=zvl means exactly the VLEN like 128 bits. I
will update it in
v3 accordingly for the difference semantics here.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, February 28, 2024 2:17 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh
1 - 100 of 802 matches
Mail list logo
