On 2/14/2024 1:14 PM, Eliot Moss via gem5-users wrote:
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register
On 2/14/2024 12:52 PM, reverent.green--- via gem5-users wrote:
I would like to add some additional information. The register number does
vary in each iteration, sometimes it is above 100. So I think it should be
the physical register value. If my understanding is correct, the physical
register
um 18:35 Uhr
Von: "Eliot Moss"
An: "The gem5 Users mailing list"
Cc: reverent.gr...@web.de
Betreff: Re: [gem5-users] Re: Architectural state of registers - O3CPU
On 2/14/2024 12:26 PM, reverent.green--- via gem5-users wrote:
> Hey Eliot,
> thank you for your answer. I
On 2/14/2024 12:26 PM, reverent.green--- via gem5-users wrote:
Hey Eliot,
thank you for your answer. I have a follow-up question.
I know, that there are more physical registers than architectural ones and that the achitectural state should be set in
the final commit state.
So if the debug
024 um 17:47 Uhr
Von: "Eliot Moss"
An: "The gem5 Users mailing list"
Cc: reverent.gr...@web.de
Betreff: Re: [gem5-users] Architectural state of registers - O3CPU
On 2/14/2024 11:19 AM, reverent.green--- via gem5-users wrote:
> Hello everyone,
> can someone give me a hin
On 2/14/2024 11:19 AM, reverent.green--- via gem5-users wrote:
Hello everyone,
can someone give me a hint, where exactly in the code the architectural state of (load) instructions is getting set and
becomes visible? I tried to trace instructions during the execution via log outputs, but got a
