On Fri, 27 May 2011, Daniel Chang wrote:
I am trying to find the last cache miss information so that I can get
the accesses right before they go to the main memory controller.
Specifically when they are sent to the controller (cycle), the type of
miss (read/write) and the address. This is the
--
From: Nilay Vaish ni...@cs.wisc.edu
Sent: Friday, May 27, 2011 12:39 PM
To: Daniel Chang dwch...@wisc.edu
Cc: gem5-users@m5sim.org
Subject: Re: [gem5-users] Getting accurate L2 Cache Miss Information
(missCycle, Address, Type)
On Fri, 27 May 2011, Daniel Chang wrote:
I am trying
To: Daniel Chang dwch...@wisc.edu
Cc: gem5-users@m5sim.org
Subject: Re: [gem5-users] Getting accurate L2 Cache Miss Information
(missCycle, Address, Type)
On Fri, 27 May 2011, Daniel Chang wrote:
I am trying to find the last cache miss information so that I can
get the accesses right before
On Thu, 26 May 2011, Daniel Chang wrote:
I am trying to produce DRAMSim compatible memory traces for applications I
normally run on M5 and am having some difficulty obtaining accurate cache miss
information. Specifically DRAMSim needs three bits of information: the cycle at
which the memory
