On Wed, 8 Jun 2011, prasanth wrote:
Hi,
I am using MESI_CMP_directory protocol. I would like to change the cache block
size in L1 cache and L2 cache to 1 word to simplify some techniques which I am
experimenting on.
For the Classic Memory System, configs/common/CacheConfig.py file sets the
Hi,
I have been trying to change cache line size (to 128) using that option. But
I get following error
fatal: port A size 64, port B size 128
Busses don't have the same block size... Not supported.
@ cycle 0
[init:build/ALPHA_FS/mem/
bridge.cc, line 99]
I don't think just specifying the
On Wed, 8 Jun 2011, Abhishek Rawat wrote:
Hi,
I have been trying to change cache line size (to 128) using that option. But
I get following error
fatal: port A size 64, port B size 128
Busses don't have the same block size... Not supported.
@ cycle 0
[init:build/ALPHA_FS/mem/
bridge.cc, line
I have tried the latest versions from both the stable and dev repositories.
I am running FS mode and have tried both O3 and timing CPU. I haven't made
any changes and I am running PARSEC benchmarks. I have not made any changes
to the configuration scripts. The only minor changes I have made are
On Wed, 8 Jun 2011, Abhishek Rawat wrote:
I have tried the latest versions from both the stable and dev repositories.
I am running FS mode and have tried both O3 and timing CPU. I haven't made
any changes and I am running PARSEC benchmarks. I have not made any changes
to the configuration
No, I am not using Ruby. But, I thought Ruby model is not yet integrated to
O3 cores.
On Wed, Jun 8, 2011 at 9:28 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Wed, 8 Jun 2011, Abhishek Rawat wrote:
I have tried the latest versions from both the stable and dev
repositories.
I am running FS
