[gem5-users] m5.switchCpus and cache connections

Hey All, Does calling m5.switchCpus move the cache connections from the existing cpu to the switch cpu as well? I am running ALPHA_SE using the standard-switch option and restoring from a checkpoint (created cacheless using AtomicSimpleCPU). To restore from the checkpoint, test_sys.cpu =

[gem5-users] Getting accurate L2 Cache Miss Information (missCycle, Address, Type)

I am trying to produce DRAMSim compatible memory traces for applications I normally run on M5 and am having some difficulty obtaining accurate cache miss information. Specifically DRAMSim needs three bits of information: the cycle at which the memory request is sent to the memory controller,

Re: [gem5-users] Getting accurate L2 Cache Miss Information (missCycle, Address, Type)

On Thu, 26 May 2011, Daniel Chang wrote: I am trying to produce DRAMSim compatible memory traces for applications I normally run on M5 and am having some difficulty obtaining accurate cache miss information. Specifically DRAMSim needs three bits of information: the cycle at which the memory