Re: [gem5-users] [m5-users] Tick Cycle Clarification

ipc is instructions per cycle, but you're calculation doesn't have instructions in it anywhere. Ticks are an unspecified unit of time, so you would need to divide them by the number of ticks in a single clock period (or use a function to do that, if there is one) to find out how cycles there were.

[gem5-users] Inorder - MultDivUnit

Hello, I am using M5's inorder model (in ALPHA_SE mode). I found out that the InOrderCPU::createBackEndSked only makes schedules for the MultDivUnit IF the instruction is an Integer multiplication/division. It doesn't do this for floating point mul/divs. Is there a special purpose for this?

Re: [gem5-users] Inorder - MultDivUnit

There's no special purpose for this, other than testing probably hasn't been done for floating-point intensive workloads. Can you submit the patch on the reviewboard? On Fri, May 27, 2011 at 8:09 AM, Maximilien Breughe maximilien.breu...@elis.ugent.be wrote: Hello, I am using M5's inorder

Re: [gem5-users] Inorder - MultDivUnit

On 05/27/2011 03:42 PM, Ali Saidi wrote: Normally, the hw that does an integer div or mul is very different the hw executes the fp version.Float mult/div should probably be handled by a different unit. I agree, but this doesn't matter for the simulator (since it's not simulating RTL but

Re: [gem5-users] Inorder - MultDivUnit

Good point, an all-powerful FloatingPoint unit isnt exactly the most realistic hardware. The problem is, right now the code will default to the all-powerful ALU. From a generic standpoint, we are still waiting a X number of cycles for an operation to finish (perhaps pipelined), so you can just

Re: [gem5-users] Getting accurate L2 Cache Miss Information (missCycle, Address, Type)

On Fri, 27 May 2011, Daniel Chang wrote: I am trying to find the last cache miss information so that I can get the accesses right before they go to the main memory controller. Specifically when they are sent to the controller (cycle), the type of miss (read/write) and the address. This is the

Re: [gem5-users] Getting accurate L2 Cache Miss Information (missCycle, Address, Type)

Nilay, I am editing the M5 memory system and am actually working with Trimaran, which incorporates the M5 system in something called M5elements. I have specifically been editing files in Trimaran that make function calls to M5 named send_dcache_request(req) and send_icache_request(req). I

Re: [gem5-users] Getting accurate L2 Cache Miss Information (missCycle, Address, Type)

That version of M5's memory system is pretty old and was ported over by someone working on Trimaran, so we might not be able to help you very much. Gabe Quoting Daniel Chang dwch...@wisc.edu: Nilay, I am editing the M5 memory system and am actually working with Trimaran, which

[gem5-users] M5 changes behavior when running in GDB

Hi all, I heavily modified the O3 cpu to implement my own architecture and I am still debugging it for some corner cases. However, I am experiencing a really weird behavior in m5. When I debug m5 in gdb (either with eclipse or kdbg) I see the outputs deviate from the expected behavior. The runs

Re: [gem5-users] M5 changes behavior when running in GDB

On Fri, 27 May 2011, Andrea Pellegrini wrote: Hi all, I heavily modified the O3 cpu to implement my own architecture and I am still debugging it for some corner cases. However, I am experiencing a really weird behavior in m5. When I debug m5 in gdb (either with eclipse or kdbg) I see the

Re: [gem5-users] M5 changes behavior when running in GDB

Valgrind could be your best friend here. I'd say run your program for a non-trivial amount of ticks (~1 billion?) in valgrind with the tool=memcheck and leak-check=yes on and usually that reveals some memory leak somewhere. If that leak is in your edited part of the code, then you probably have

Re: [gem5-users] M5 changes behavior when running in GDB

I'd say valgrind is a good idea, but it's probably something that's not initialized rather than a memory leak. You could look at what instruction is writing the register that's different and see what it's operands are and which version is correct. That looks like a stack address, so there

Re: [gem5-users] M5 changes behavior when running in GDB

note that valgrind will also tell you if use a value that is not initialized. The flag should be show-uninitialized or something like that. On Fri, May 27, 2011 at 6:03 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: I'd say valgrind is a good idea, but it's probably something that's

Re: [gem5-users] ALPHA SE mode : How to run a producer consumer type of example?

Hi, My thesis is related to Application-aware Inter-processor Communication. Based on memory access patterns of the application, system could help in reducing running time of some applications. *That is why*, I was looking to build a producer-consumer kind of example, with which I would like to

[gem5-users] ruby_random_tester

Hey all, I have developed a cache coherency protocol for a course project and I like to test its capability: 1. I have written a very simple multithreaded program that has the features my protocol best fits to and cross-compiled it for alpha architecture but when I ran it (using se.py) it

Re: [gem5-users] ruby_random_tester

Do you run into the problem in 2 on more than one CPU model? Does an unmodified version of gem5 from the most recent version of the development repository hit the same problem? If so, please send me your binary directly (to spare everyone's inboxes) and I'll take a look. What instruction