Hi,
I am new to m5 and am trying to simulate CMPs with super-scalar cores in SE
mode. Has there been any known issues related to super-scalar implementation
? I looked at the mail archive and didn't find any but just wanted to make
sure that it works. I am using a 64-bit machine.
Thanks in
Thanks for the reply. I have a follow up question. So, lets say I am only
using one O3 core and If I want to run 2-threaded SMT that means I will have
to provide as input for instance 2 FFT benchmarks. And for 4-threaded SMT
similarly I will have to provide as input 4 FFT benchmark. In this case
wrote:
If the benchmark is explicitly multithreaded and compiled against the
m5threads library, then you can run it on an SMT O3 CPU and it should
work.
Steve
On Thu, Apr 15, 2010 at 9:43 PM, abhishek rawat abhi...@gmail.com wrote:
Thanks for the reply. I have a follow up question. So, lets
Hi,
I have been trying to change the stageWidth parameter in inorder CPU model
(ALPHA SE mode) and I keep getting the following from the simulation output:
Exiting @ cycle 9223372036854775807 because simulate() limit reached
I am running splash2's Radix benchmark.
Also, even after setting
Hi everyone,
I am running PARSEC benchmarks using M5 ALPHA_FS inorder cores. I keep
getting following error:
File /net/uf16/ar8eb/Desktop/gem5/m5/configs/common/Simulation.py, line
54, in setCPUClass
class TmpClass(InOrderCPU): pass
NameError: global name 'InOrderCPU' is not defined
I have
Hi everyone,
I am running O3 cores in ALPHA FS. I am trying to change the cache line size
of caches. But I keep getting following error :
fatal: port A size 64, port B size 128
Busses don't have the same block size... Not supported.
@ cycle 0
[init:build/ALPHA_FS/mem/bridge.cc, line 99]
I
Hi,
I have been trying to change cache line size (to 128) using that option. But
I get following error
fatal: port A size 64, port B size 128
Busses don't have the same block size... Not supported.
@ cycle 0
[init:build/ALPHA_FS/mem/
bridge.cc, line 99]
I don't think just specifying the
are those
which were required to support PARSEC.
Thanks,
Abhishek
On Wed, Jun 8, 2011 at 7:13 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Wed, 8 Jun 2011, Abhishek Rawat wrote:
Hi,
I have been trying to change cache line size (to 128) using that option.
But
I get following error
fatal: port
I have also been thinking about the same issue with bus being a bottleneck.
And I know that with the Ruby memory model we can use other interconnects,
but I think that only works for the timing cpu. I am particularly interested
in O3 and inorder cpu models. Is there a way we can address this issue
No, I am not using Ruby. But, I thought Ruby model is not yet integrated to
O3 cores.
On Wed, Jun 8, 2011 at 9:28 PM, Nilay Vaish ni...@cs.wisc.edu wrote:
On Wed, 8 Jun 2011, Abhishek Rawat wrote:
I have tried the latest versions from both the stable and dev
repositories.
I am running FS
config.ini you must have missed one of them.
Ali
On Jun 7, 2011, at 10:39 AM, Abhishek Rawat wrote:
Hi everyone,
I am running O3 cores in ALPHA FS. I am trying to change the cache line
size of caches. But I keep getting following error :
fatal: port A size 64, port B size 128
Busses
it.
Gabe
Quoting Abhishek Rawat abhi...@gmail.com:
Thanks Ali. It works when I manually update config.ini to change the block
size. But, its not working when I use cacheline_size parameter from
command line.
On Thu, Jun 9, 2011 at 2:16 AM, Ali Saidi sa...@umich.edu wrote:
You need
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