On 3/26/2024 12:26 PM, Jani Nikula wrote:
On Tue, 26 Mar 2024, "Nautiyal, Ankit K" wrote:
On 3/25/2024 8:48 PM, Jani Nikula wrote:
On Fri, 22 Mar 2024, Ankit Nautiyal wrote:
Currently we probe for lspcon, inside lspcon init. Which does 2 things:
probe the lspcon and set the expected
On Tue, 26 Mar 2024, "Nautiyal, Ankit K" wrote:
> On 3/25/2024 8:48 PM, Jani Nikula wrote:
>> On Fri, 22 Mar 2024, Ankit Nautiyal wrote:
>>> Currently we probe for lspcon, inside lspcon init. Which does 2 things:
>>> probe the lspcon and set the expected LS/PCON mode.
>>>
>>> If there is no
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
>
> 2. Assigns all the CCS slices to one single user engine. The user
>will then be able to query
Hi Imre,
Thanks for the DSC fixes.
Would the line buf depth calculation that was getting set to 0 impact
DSC on all platforms
or was this issue only specific to MTL and was getting set correctly
with older platforms?
We didnt notice any DSC issues/corruptions with ADL based systems.
The actual
On Tue, Mar 26, 2024 at 04:02:41PM +0530, Ravi Kumar Vodapalli wrote:
> New PCI IDs are added in Bspec for DG2 platform, add them in driver
>
> Bspec: 44477
> Signed-off-by: Ravi Kumar Vodapalli
Reviewed-by: Matt Roper
> ---
> include/drm/i915_pciids.h | 4 +++-
> 1 file changed, 3
The bigjoiner master handling in modset_enables/disables looks good.
Reviewed-by: Manasi Navare
Manasi
On Mon, Mar 25, 2024 at 12:20 AM Srinivas, Vidya
wrote:
>
> Thank you Stan. Rev 14 works.
> Tested-by: Vidya Srinivas
>
> > -Original Message-
> > From: Lisovskiy, Stanislav
> >
On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K
wrote:
>
>
> On 3/21/2024 1:41 AM, Imre Deak wrote:
> > The expected link symbol clock unit when calculating the DSC DPT bpp
> > limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit
> > based on the crtc clock. As opposed to this
On Tue, Mar 26, 2024 at 02:12:47PM +0200, Ville Syrjälä wrote:
> On Mon, Mar 25, 2024 at 09:03:32PM +0200, Lisovskiy, Stanislav wrote:
> > On Mon, Mar 25, 2024 at 08:43:10PM +0200, Ville Syrjälä wrote:
> > > On Mon, Mar 25, 2024 at 08:29:56PM +0200, Lisovskiy, Stanislav wrote:
> > > > On Mon, Mar
Joonas,
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
do we need a documentation update here?
Andi
On Wed, Mar 13, 2024 at 09:19:51PM +0100, Andi Shyti wrote:
> Enable only one CCS engine by default with all the compute sices
> allocated to it.
>
> While generating the list of UABI engines to be exposed to the
> user, exclude any additional CCS engines beyond the first
> instance.
>
> This
Hi Dave and Sima,
Please pull the drm-xe-fixes for this week targeting v6.9-rc2.
drm-xe-fixes-2024-03-26:
- Fix build on mips
- Fix wrong bound checks
- Fix use of msec rather than jiffies
- Remove dead code
The following changes since commit 4cece764965020c22cff7665b18a012006359095:
Linux
On Tue, Mar 26, 2024 at 10:31:26PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we always reprogram CDCLK from the
> intel_set_cdclk_post_plane_update() when using squahs/crawl.
> The code only works correctly for the cd2x update or full
> modeset cases, and it was simply
Hi Michal, Mark,
can you please ack from your side this first batch of changes?
Thanks,
Andi
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
>
>
Looks good to me
Reviewed-by: Manasi Navare
Manasi
On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy
wrote:
>
> And we have at least one trivial place in
> intel_ddi_update_active_dpll() where we can use it
> immediately, so let's do that.
>
> v2: - Fixed conflicts, part of patch didn't
From: Ville Syrjälä
Currently we always reprogram CDCLK from the
intel_set_cdclk_post_plane_update() when using squahs/crawl.
The code only works correctly for the cd2x update or full
modeset cases, and it was simply never updated to deal with
squash/crawl.
If the CDCLK frequency is increasing
From: Ville Syrjälä
Fix the CDCLK programming sequence when using squash or crawl,
and also drop the tgl/dg2 hacks since we have no idea what those
are for.
Ville Syrjälä (3):
drm/i915/cdclk: Fix CDCLK programming order when pipes are active
drm/i915/cdclk: Fix voltage_level programming
From: Ville Syrjälä
Currently we only consider the relationship of the
old and new CDCLK frequencies when determining whether
to do the repgramming from intel_set_cdclk_pre_plane_update()
or intel_set_cdclk_post_plane_update().
It is technically possible to have a situation where the
CDCLK
From: Ville Syrjälä
No ever figured out why bumping the cdclk helped
with whatever issue we were having at the time.
Remove the hacks and start from scratch so that we
can actually see if any problems still remain.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c |
Quoting Ville Syrjala (2024-03-26 17:31:26-03:00)
>From: Ville Syrjälä
>
>Currently we always reprogram CDCLK from the
>intel_set_cdclk_post_plane_update() when using squahs/crawl.
Hm... I'm not following this sentence. Looks like cdclk_state->pipe will
be INVALID_PIPE unless it is a cd2x
Reviewed-by: Manasi Navare
Manasi
On Tue, Mar 26, 2024 at 5:54 AM Nautiyal, Ankit K
wrote:
>
>
> On 3/21/2024 1:41 AM, Imre Deak wrote:
> > Factor out a function to check for UHBR channel coding support used by a
> > follow-up patch in the patchset.
> >
> > Cc: dri-de...@lists.freedesktop.org
On Tue, Mar 26, 2024 at 1:04 PM Manasi Navare wrote:
>
> On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K
> wrote:
> >
> >
> > On 3/21/2024 1:41 AM, Imre Deak wrote:
> > > The expected link symbol clock unit when calculating the DSC DPT bpp
> > > limit is kSymbols/sec, aligning with the
Hi Imre,
Would this impact/fix DSC functionality on ADL based platforms as well
or will this change only impact platforms that support UHBR?
Manasi
On Tue, Mar 26, 2024 at 5:55 AM Nautiyal, Ankit K
wrote:
>
>
> On 3/21/2024 1:41 AM, Imre Deak wrote:
> > Instead of checking each compressed bpp
On Tuesday, 26 March 2024 13:48:38 CET Badal Nilawar wrote:
> i915_hwmon and its resources are managed resources of i915 dev.
> During i915 driver unregister flow the function i915_hwmon_unregister()
> explicitly makes i915_hwmon resource NULL. This happen before
> hwmon is actually unregistered.
Hi Matt,
On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > + /*
> > +* Do not create the command streamer for CCS slices
> > +* beyond the first. All the workload
On Tue, Mar 26, 2024 at 07:42:34PM +0100, Andi Shyti wrote:
> Hi Matt,
>
> On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> > On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > > + /*
> > > + * Do not create the command streamer for CCS
On Tue, Mar 26, 2024 at 06:42:09PM -0300, Gustavo Sousa wrote:
> Quoting Ville Syrjala (2024-03-26 17:31:26-03:00)
> >From: Ville Syrjälä
> >
> >Currently we always reprogram CDCLK from the
> >intel_set_cdclk_post_plane_update() when using squahs/crawl.
>
> Hm... I'm not following this sentence.
== Series Details ==
Series: drm/i915: Add new PCI IDs to DG2 platform in driver
URL : https://patchwork.freedesktop.org/series/131625/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14489 -> Patchwork_131625v1
Summary
== Series Details ==
Series: drm/i915/hwmon: Remove i915_hwmon_unregister() during driver unbind
URL : https://patchwork.freedesktop.org/series/131630/
State : warning
== Summary ==
Error: dim checkpatch failed
c41351a42cf0 drm/i915/hwmon: Remove i915_hwmon_unregister() during driver unbind
The current intel_bw_atomic_check do not check the possbility
of a sagv configuration change after the hw state readout.
Hence cannot update the sagv configuration until some other
relevant changes like data rates, number of planes etc. happen.
Introduce a flag to force qgv check in such cases.
From: Stanislav Lisovskiy
Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all
restricted, causing issues.
Lets disable SAGV initially to force proper QGV point
Extract the code to prepare the QGV points mask as per the
format expected by the pcode as this could be utlized from
multiple points.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff
From: Stanislav Lisovskiy
We need that in order to force disable SAGV in next patch.
Also it is beneficial to separate that code, as in majority cases,
when SAGV is enabled, we don't even need those calculations.
Also we probably need to determine max PSF GV point as well, however
currently we
From: Stanislav Lisovskiy
There could be multiple qgv and psf gv points with similar values
In case if we need to set one such QGV or psf gv point where there
could be duplicate entries, we would have to select all those
points. Otherwise pcode might reject the GV configuration. We do
handle
We have couple of customer issues, related to SAGV/QGV point
calculation. Those patches contain fixes plus some additional
debugs for those issues.
Stanislav Lisovskiy (4):
drm/i915/display: Add meaningful traces for QGV point info error
handling
drm/i915/display: Extract code required to
From: Stanislav Lisovskiy
For debug purposes we need those - error path won't flood the log,
however there has been already numerous cases, when due to lack
of debugs, we couldn't immediately tell what was the problem on
customer machine, which slowed down the investigation, requiring
to get
== Series Details ==
Series: drm/i915/hwmon: Remove i915_hwmon_unregister() during driver unbind
URL : https://patchwork.freedesktop.org/series/131630/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14489 -> Patchwork_131630v1
== Series Details ==
Series: QGV/SAGV related fixes (rev9)
URL : https://patchwork.freedesktop.org/series/126962/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1:
== Series Details ==
Series: QGV/SAGV related fixes (rev9)
URL : https://patchwork.freedesktop.org/series/126962/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14489 -> Patchwork_126962v9
Summary
---
**FAILURE**
> Subject: [PATCH] drm/i915/dp: Fix the computation for compressed_bpp for
> DISPLAY < 13
>
> For DISPLAY < 13, compressed bpp is chosen from a list of supported
> compressed bpps. Fix the condition to choose the appropriate compressed
> bpp from the list.
>
LGTM,
Reviewed-by: Suraj Kandpal
>
On 27-03-2024 02:58, Krzysztofik, Janusz wrote:
On Tuesday, 26 March 2024 13:48:38 CET Badal Nilawar wrote:
i915_hwmon and its resources are managed resources of i915 dev.
During i915 driver unregister flow the function i915_hwmon_unregister()
explicitly makes i915_hwmon resource NULL. This
== Series Details ==
Series: drm/i915: Add new pciid's to DG2 platform
URL : https://patchwork.freedesktop.org/series/131621/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
> -Original Message-
> From: Kandpal, Suraj
> Sent: Wednesday, March 27, 2024 9:06 AM
> To: Borah, Chaitanya Kumar ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: Initalizalize capability variables
>
> > Hello Suraj,
> >
> > > -Original Message-
On Tue, Mar 05, 2024 at 11:07:36AM +0200, Jani Nikula wrote:
> Add kconfig to enable -Werror subsystem wide. This is useful for
> development and CI to keep the subsystem warning free, while avoiding
> issues outside of the subsystem that kernel wide CONFIG_WERROR=y might
> hit.
>
> v2: Don't
> -Original Message-
> From: Borah, Chaitanya Kumar
> Sent: Wednesday, March 27, 2024 9:32 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915/display: Initalizalize capability variables
>
>
>
> > -Original Message-
> > From: Kandpal,
From: Ville Syrjälä
Currently we only consider the relationship of the
old and new CDCLK frequencies when determining whether
to do the repgramming from intel_set_cdclk_pre_plane_update()
or intel_set_cdclk_post_plane_update().
It is technically possible to have a situation where the
CDCLK
Hi Matt,
On Tue, Mar 26, 2024 at 02:30:33PM -0700, Matt Roper wrote:
> On Tue, Mar 26, 2024 at 07:42:34PM +0100, Andi Shyti wrote:
> > On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> > > On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > > > + /*
>
== Series Details ==
Series: drm/i915/cdclk: CDCLK fixes (rev3)
URL : https://patchwork.freedesktop.org/series/131662/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/cdclk: CDCLK fixes (rev3)
URL : https://patchwork.freedesktop.org/series/131662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14489 -> Patchwork_131662v3
Summary
---
From: Ville Syrjälä
Currently we always reprogram CDCLK from the
intel_set_cdclk_pre_plane_update() when using squahs/crawl.
The code only works correctly for the cd2x update or full
modeset cases, and it was simply never updated to deal with
squash/crawl.
If the CDCLK frequency is increasing
Hi Ville,
Regarding the patch 5/6 in this series, I have asked the pcode team for
clarifications on how to
handle cases with duplicate QGV points.
Please note that I added a new patch to force the QGV check after HW state
readout (patch 6/6)
without that we won't be updating the QGV unless
== Series Details ==
Series: drm/i915: Add new pciid's to DG2 platform
URL : https://patchwork.freedesktop.org/series/131621/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14489 -> Patchwork_131621v1
Summary
---
> Hello Suraj,
>
> > -Original Message-
> > From: Kandpal, Suraj
> > Sent: Tuesday, March 26, 2024 10:45 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Borah, Chaitanya Kumar ; Kandpal,
> > Suraj
> > Subject: [PATCH] drm/i915/display: Initalizalize capability variables
>
> Typo:
This patch series fixes the UBSAN warning which gets called
when hdcp_info is invoked accompanied by some other logical fixes
required in the hdcp capability function.
Signed-off-by: Suraj Kandpal
Suraj Kandpal (2):
drm/i915/display: Initialize capability variables
drm/i915/hdcp: Fix get
Initialize HDCP capability variables to false to avoid UBSAN
warning in boolean value.
--v2
-Fix Typo [Chaitanya]
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
HDCP 1.x capability needs to be checked even if setup is not
HDCP 2.x capable.
Fixes: 813cca96e4ac ("drm/i915/hdcp: Add new remote capability check shim
function")
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 9 -
1 file changed, 4 insertions(+), 5
== Series Details ==
Series: Fix UBSAN warning in hdcp_info
URL : https://patchwork.freedesktop.org/series/131673/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1:
The 2024 X.Org Foundation membership renewal period has been extended
one additional week and elections will start the following week on 01
April 2024.
Please note that only current members can vote in the upcoming election,
and that the deadline for new memberships or renewals to vote in the
On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> We want a fixed load CCS balancing consisting in all slices
> sharing one single user engine. For this reason do not create the
> intel_engine_cs structure with its dedicated command streamer for
> CCS slices beyond the first.
>
>
New pciid's are added in Bspec for DG2 platform
Bspec: 44477
Signed-off-by: Ravi Kumar Vodapalli
---
include/drm/xe_pciids.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
index ab4a8987ac65..c7fc288dacee 100644
---
On 3/21/2024 1:41 AM, Imre Deak wrote:
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall
On 3/21/2024 1:41 AM, Imre Deak wrote:
The DSC DPT bpp limit check should only fail if the available DPT BW is
less than the required BW, fix the check accordingly.
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1
Hi Janusz and Chris,
> Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Janusz Krzysztofik
> Cc: Chris Wilson
> Cc: # v5.4+
with the tags rearranged
New PCI IDs are added in Bspec for DG2 platform, add them in driver
Bspec: 44477
Signed-off-by: Ravi Kumar Vodapalli
---
include/drm/i915_pciids.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index
Hi Nirmoy,
...
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > index a2195e28b625..57a2dda2c3cc 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > @@ -276,7 +276,7 @@
Hi Janusz,
On Tue, Mar 05, 2024 at 03:35:05PM +0100, Janusz Krzysztofik wrote:
> Object debugging tools were sporadically reporting illegal attempts to
> free a still active i915 VMA object when parking a GT believed to be idle.
>
> [161.359441] ODEBUG: free active (active state 0) object:
On 3/21/2024 1:41 AM, Imre Deak wrote:
The DSC DPT interface BW limit check should take into account the link
clock's (aka DDI clock in bspec) channel coding efficiency overhead.
Bspec doesn't mention this, however this matches how the link BW limit
is checked (that is the BW limit on wire as
On 3/26/2024 3:47 PM, Nautiyal, Ankit K wrote:
On 3/21/2024 1:41 AM, Imre Deak wrote:
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1
Hello Suraj,
> -Original Message-
> From: Kandpal, Suraj
> Sent: Tuesday, March 26, 2024 10:45 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Kandpal,
> Suraj
> Subject: [PATCH] drm/i915/display: Initalizalize capability variables
Typo: Initialize
>
On 3/21/2024 1:41 AM, Imre Deak wrote:
The expected link symbol clock unit when calculating the DSC DPT bpp
limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit
based on the crtc clock. As opposed to this port_clock is used - which
has a 10 kbits/sec unit - with the resulting
On Tue, 26 Mar 2024, Ravi Kumar Vodapalli
wrote:
> New pciid's are added in Bspec for DG2 platform
drm/i915 subject prefix does not match the patch, which is for xe.
Do the i915 PCI IDs also need updating?
And please call them PCI IDs instead of "pciid's".
BR,
Jani.
>
> Bspec: 44477
>
On 3/21/2024 1:41 AM, Imre Deak wrote:
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Tue, Mar 26, 2024 at 04:57:57AM +, Borah, Chaitanya Kumar wrote:
> > -Original Message-
> > From: Intel-gfx On Behalf Of Ville
> > Syrjala
> > Sent: Monday, March 25, 2024 11:28 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: sta...@vger.kernel.org; Borislav Petkov
> > Subject:
i915_hwmon and its resources are managed resources of i915 dev.
During i915 driver unregister flow the function i915_hwmon_unregister()
explicitly makes i915_hwmon resource NULL. This happen before
hwmon is actually unregistered. Doing so may cause UAF if hwmon
sysfs is being accessed:
<7>
On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote:
>
> On 3/21/2024 1:41 AM, Imre Deak wrote:
> > The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
> > do so.
> >
> > Bspec: 49259
> >
> > Signed-off-by: Imre Deak
> > ---
> >
On Mon, Mar 25, 2024 at 09:03:32PM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Mar 25, 2024 at 08:43:10PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 25, 2024 at 08:29:56PM +0200, Lisovskiy, Stanislav wrote:
> > > On Mon, Mar 25, 2024 at 07:11:21PM +0200, Ville Syrjälä wrote:
> > > > On Mon, Mar
On 3/21/2024 1:41 AM, Imre Deak wrote:
Factor out a function to check for UHBR channel coding support used by a
follow-up patch in the patchset.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
On 3/26/2024 5:41 PM, Imre Deak wrote:
On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote:
On 3/21/2024 1:41 AM, Imre Deak wrote:
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Signed-off-by: Imre Deak
---
On Thu, 21 Mar 2024, gareth...@intel.com wrote:
> From: Gareth Yu
>
> Turn on the panel from zero brightness of the last state, the panel was
> set a maximum PWM in the flow. Once the panel initialization is completed,
> the backlight is restored to xero brightness. There is a flckering
>
On Tue, Mar 26, 2024 at 01:36:29PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 26, 2024 at 04:57:57AM +, Borah, Chaitanya Kumar wrote:
> > > -Original Message-
> > > From: Intel-gfx On Behalf Of
> > > Ville
> > > Syrjala
> > > Sent: Monday, March 25, 2024 11:28 PM
> > > To:
Hi Andi,
On 3/26/2024 12:12 PM, Andi Shyti wrote:
Hi Nirmoy,
...
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index a2195e28b625..57a2dda2c3cc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++
On Mon, 25 Mar 2024, Gustavo Sousa wrote:
> Quoting Jani Nikula (2024-03-20 13:01:22-03:00)
>>Do some renames on the register wait functions for clarity and brevity:
>>
>>intel_de_wait_for_register-> intel_de_wait
>>intel_de_wait_for_register_fw-> intel_de_wait_fw
On Mon, Mar 25, 2024 at 07:21:35PM +0100, Borislav Petkov wrote:
> On Mon, Mar 25, 2024 at 07:57:38PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Calling i915_gem_object_get_dma_address() from the vblank
> > evade critical section triggers might_sleep().
> >
> > While we know
On 3/21/2024 1:41 AM, Imre Deak wrote:
Factor out a function to check if an MST port is logical, used by a
follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++---
On 3/21/2024 1:41 AM, Imre Deak wrote:
Instead of checking each compressed bpp value against the maximum
DSC/DPT bpp, simplify things by calculating the maximum bpp upfront and
limiting the range of bpps looped over using this maximum.
While at it add a comment about the origin of the DSC/DPT
From: Arnd Bergmann
This is a follow-up on a couple of patch series I sent in the past,
enabling -Wextra (aside from stuff that is explicitly disabled),
-Wcast-function-pointer-strict and -Wrestrict.
I have tested these on 'defconfig' and 'allmodconfig' builds across
all architectures, as well
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