On 10/11/2015 16:38, Jan Kiszka wrote:
> On 2015-11-10 13:22, Paolo Bonzini wrote:
>> Yes, these can happen. The issue is that benign exceptions are
>> delivered serially, but two of them (#DB and #AC) can also happen
>> during exception delivery itself. The subsequent infinite stream
>> of
On 06/11/2015 01:24, Andrew Jones wrote:
> From: Alex Bennée
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Andrew Jones
> ---
> README | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git
On 06/11/2015 01:24, Andrew Jones wrote:
> With this $TEST_DIR/run can output test specific error messages.
>
> Signed-off-by: Andrew Jones
> ---
> run_tests.sh | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/run_tests.sh b/run_tests.sh
> index
On 11/09/15 14:01, Eduardo Habkost wrote:
> On Mon, Nov 09, 2015 at 08:33:55AM +0800, haozhong.zh...@intel.com wrote:
> > On 11/06/15 13:12, Eduardo Habkost wrote:
> > > On Fri, Nov 06, 2015 at 10:32:24AM +0800, haozhong.zh...@intel.com wrote:
> > > > On 11/05/15 14:05, Eduardo Habkost wrote:
> >
The patch "MIPS: CPS: Early debug using an ns16550-compatible UART" in
linux-next causes a build warning in locore.S by adding an identical
definition of CP0_EBASE in asm/mipsregs.h.
arch/mips/kvm/locore.S:41:0: warning: "CP0_EBASE" redefined
#define CP0_EBASE $15,1
^
In file included
On 09/11/2015 21:53, Andrew Jones wrote:
> It's pretty safe to not even bother checking for NULL when
> using malloc and friends, but if we do check, then fail
> hard.
>
> Signed-off-by: Andrew Jones
> ---
> v2: no code in asserts [Thomas Huth]
>
> lib/virtio-mmio.c | 6
On 10/11/2015 17:37, Andrew Jones wrote:
> On Tue, Nov 10, 2015 at 05:22:41PM +0100, Paolo Bonzini wrote:
>>
>>
>> On 06/11/2015 01:24, Andrew Jones wrote:
>>> Use bash in the makefiles, like we do in the scripts. Without
>>> this some platforms using dash fail to execute make targets
>>> that
On 10 November 2015 at 16:59, Andrew Jones wrote:
> On Tue, Nov 10, 2015 at 04:29:31PM +, Peter Maydell wrote:
>> On 10 November 2015 at 00:23, Andrew Jones wrote:
>> > -/* KVM uses PAGE_SIZE in its definition of COALESCED_MMIO_MAX */
>> > -#define
On 10/11/2015 01:23, Andrew Jones wrote:
> Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated
> reason. I didn't use qemu_real_host_page_size as kvm_set_phys_mem()
> does, because we'd need to make sure page_size_init() has run first.
>
> Signed-off-by: Andrew Jones
On Sun, Nov 08, 2015 at 12:49:46PM +0100, Joerg Roedel wrote:
> On Sun, Nov 08, 2015 at 12:37:47PM +0200, Michael S. Tsirkin wrote:
> > I have no problem with that. For example, can we teach
> > the DMA API on intel x86 to use PT for virtio by default?
> > That would allow merging Andy's patches
On 2015-11-10 13:22, Paolo Bonzini wrote:
> Yes, these can happen. The issue is that benign exceptions are
> delivered serially, but two of them (#DB and #AC) can also happen
> during exception delivery itself. The subsequent infinite stream
> of exceptions causes the processor to never exit
On 06/11/2015 01:24, Andrew Jones wrote:
> From: Alex Bennée
>
> This is useful information for the run scripts to know, especially if
> they want to drop to using TCG.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Andrew Jones
On 06/11/2015 01:24, Andrew Jones wrote:
> From: Christopher Covington
>
> Signed-off-by: Christopher Covington
> Reviewed-by: Andrew Jones
> ---
> arm/selftest.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On 06/11/2015 01:24, Andrew Jones wrote:
> From: Alex Bennée
>
> This introduces a new flush_tlb_page function which does exactly what
> you expect. It's going to be useful for the future TLB torture test.
>
> Signed-off-by: Alex Bennée
>
On 06/11/2015 01:24, Andrew Jones wrote:
> From: Alex Bennée
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Andrew Jones
> ---
> lib/printf.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git
On 10/11/2015 16:57, Andrew Jones wrote:
> On Tue, Nov 10, 2015 at 04:41:16PM +0100, Paolo Bonzini wrote:
>>
>>
>> On 10/11/2015 01:23, Andrew Jones wrote:
>>> Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated
>>> reason. I didn't use qemu_real_host_page_size as
On 06/11/2015 01:24, Andrew Jones wrote:
> Many of these patches were posted once. Some weren't, but anyway
> almost everything is pretty trivial. I'd like to get these in, or
> at least get definitive nacks on them (and then drop them) in order
> to clean my queue before more patches (coming
On 06/11/2015 01:24, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> README | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/README b/README
> index eab5ea28f7fab..45587f2a97ec6 100644
> --- a/README
> +++ b/README
> @@ -1,3 +1,9 @@
> +Welcome to
On 06/11/2015 01:24, Andrew Jones wrote:
> This is a fix just due to being too much of a type-A person.
> I noticed the issue while reading over the function, and
> decided to fix it, even though it's unlikely to be a problem
> ever because top is read-mostly (like written once, then only
>
On 06/11/2015 01:24, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
> ---
> lib/string.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/string.h b/lib/string.h
> index 7820db86ee4e0..4e24f54d9e231 100644
> --- a/lib/string.h
> +++
On 06/11/2015 01:24, Andrew Jones wrote:
> Arguably all of uart0_init() is unnecessary, as we're pretty sure
> that the address we initialize uart0_base to is correct. We go
> through the motions of finding the uart anyway though, because it's
> easy. It's also easy to check chosen/stdout-path
On 06/11/2015 01:24, Andrew Jones wrote:
> KVM can be configured to only support a few vcpus. ARM and AArch64
> currently have a default config of only 4. While it's nice to be
> able to write tests that use the maximum recommended, nr-host-cpus,
> we can't assume that nr-host-cpus ==
On 10 November 2015 at 00:23, Andrew Jones wrote:
> Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated
> reason. I didn't use qemu_real_host_page_size as kvm_set_phys_mem()
> does, because we'd need to make sure page_size_init() has run first.
>
>
On 06/11/2015 01:24, Andrew Jones wrote:
> Inspired by a patch by Alex Bennée. This version uses a new
> unittests.cfg variable and includes support for DRYRUN.
>
> Signed-off-by: Andrew Jones
> ---
> arm/run | 43 +--
On 09/11/2015 21:57, Andrew Jones wrote:
> assert() is classically a macro which could also be disabled, so if
> somebody introduces a switch to "#define assert(...) /*nothing*/" in
> the future, we'd lose code.
>
> Suggested-by: Thomas Huth
> Signed-off-by: Andrew Jones
On Tue, Nov 10, 2015 at 05:22:41PM +0100, Paolo Bonzini wrote:
>
>
> On 06/11/2015 01:24, Andrew Jones wrote:
> > Use bash in the makefiles, like we do in the scripts. Without
> > this some platforms using dash fail to execute make targets
> > that use bash-isms.
> >
> > Signed-off-by: Andrew
On Tue, Nov 10, 2015 at 05:38:38PM +0100, Paolo Bonzini wrote:
>
>
> On 06/11/2015 01:24, Andrew Jones wrote:
> > Many of these patches were posted once. Some weren't, but anyway
> > almost everything is pretty trivial. I'd like to get these in, or
> > at least get definitive nacks on them (and
On Tue, Nov 10, 2015 at 04:41:16PM +0100, Paolo Bonzini wrote:
>
>
> On 10/11/2015 01:23, Andrew Jones wrote:
> > Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated
> > reason. I didn't use qemu_real_host_page_size as kvm_set_phys_mem()
> > does, because we'd need to make sure
On 06/11/2015 01:24, Andrew Jones wrote:
> Use bash in the makefiles, like we do in the scripts. Without
> this some platforms using dash fail to execute make targets
> that use bash-isms.
>
> Signed-off-by: Andrew Jones
> ---
> Makefile | 2 ++
> 1 file changed, 2
On Tue, Nov 10, 2015 at 04:29:31PM +, Peter Maydell wrote:
> On 10 November 2015 at 00:23, Andrew Jones wrote:
> > Just noticed this while grepping TARGET_PAGE_SIZE for an unrelated
> > reason. I didn't use qemu_real_host_page_size as kvm_set_phys_mem()
> > does, because
On Nov 10, 2015 7:02 AM, "Michael S. Tsirkin" wrote:
>
> On Sun, Nov 08, 2015 at 12:49:46PM +0100, Joerg Roedel wrote:
> > On Sun, Nov 08, 2015 at 12:37:47PM +0200, Michael S. Tsirkin wrote:
> > > I have no problem with that. For example, can we teach
> > > the DMA API on intel
On Nov 10, 2015 2:38 AM, "Benjamin Herrenschmidt"
wrote:
>
> On Mon, 2015-11-09 at 21:35 -0800, Andy Lutomirski wrote:
> >
> > We could do it the other way around: on powerpc, if a PCI device is in
> > that range and doesn't have the "bypass" property at all, then it's
>
On Mon, 2015-11-09 at 15:24 +0300, Dan Carpenter wrote:
> Smatch complains about a possible out of bounds error:
>
> drivers/vfio/pci/vfio_pci_config.c:1241 vfio_cap_init()
> error: buffer overflow 'pci_cap_length' 20 <= 20
>
> The problem is that pci_cap_length[] was defined as
Linus,
The following changes since commit a3eaa8649e4c6a6afdafaa04b9114fb230617bb1:
KVM: VMX: Fix commit which broke PML (2015-11-05 11:34:11 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to
On Tue, 2015-11-10 at 11:27 +0100, Joerg Roedel wrote:
>
> You have the same problem when real PCIe devices appear that speak
> virtio. I think the only real (still not very nice) solution is to add a
> quirk to powerpc platform code that sets noop dma-ops for the existing
> virtio
On Tue, 2015-11-10 at 14:43 +0200, Michael S. Tsirkin wrote:
> But not virtio-pci I think - that's broken for that usecase since we use
> weaker barriers than required for real IO, as these have measureable
> overhead. We could have a feature "is a real PCI device",
> that's completely
On Tue, 2015-11-10 at 10:54 -0800, Andy Lutomirski wrote:
>
> Does that work on powerpc on existing kernels?
>
> Anyway, here's another crazy idea: make the quirk assume that the
> IOMMU is bypasses if and only if the weak barriers bit is set on
> systems that are missing the new DT binding.
On Tue, Nov 10, 2015 at 2:27 PM, Benjamin Herrenschmidt
wrote:
> On Tue, 2015-11-10 at 10:54 -0800, Andy Lutomirski wrote:
>>
>> Does that work on powerpc on existing kernels?
>>
>> Anyway, here's another crazy idea: make the quirk assume that the
>> IOMMU is bypasses if
Improves cacheline transfer flow of available ring header.
Virtqueues are implemented as a pair of rings, one producer->consumer
avail ring and one consumer->producer used ring; preceding the
avail ring in memory are two contiguous u16 fields -- avail->flags
and avail->idx. A producer posts work
On 2015/11/09 19:14, Paolo Bonzini wrote:
Can you also change kvm_mmu_mark_parents_unsync to use
for_each_rmap_spte instead of pte_list_walk? It is the last use of
pte_list_walk, and it's nice if we have two uses of for_each_rmap_spte
with parent_ptes as the argument.
No problem, I will do.
On 10/11/2015 10:05, Takuya Yoshikawa wrote:
>
>
>> BTW, on my todo list is to change the rmap items to a struct (with a
>> single u64 inside) for type safety. Since you are touching this code,
>> perhaps you can give it a shot?
>
> Yes, almost done here (assuming that you mean 'unsigned
On Mon, 2015-11-09 at 14:17 +0100, Paolo Bonzini wrote:
> > > static inline bool permission_fault(struct kvm_vcpu *vcpu,
> > > struct kvm_mmu *mmu,
> > > - unsigned pte_access,
> > > unsigned pfec)
> > > + unsigned pte_access, unsigned pte_pkeys,
> > >
On 10/11/2015 10:28, Han, Huaitong wrote:
> > pkru = is_long_mode(vcpu) ? read_pkru() : 0;
> > if (unlikely(pkru) && (pfec & PFERR_PK_MASK)) {
> > ... from above ... */
> >
> > /* Flip PFERR_PK_MASK if pkru_bits is non-zero */
> > pfec ^= -pkru_bits &
On Tue, 2015-11-10 at 13:04 +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2015-11-09 at 16:46 -0800, Andy Lutomirski wrote:
> > The problem here is that in some of the problematic cases the
> > virtio
> > driver may not even be loaded. If someone runs an L1 guest with an
> > IOMMU-bypassing
(adding lists)
On 10 November 2015 at 10:45, Ard Biesheuvel wrote:
> Hi all,
>
> I wonder if this is a better way to address the problem. It looks at
> the nature of the memory rather than the nature of the mapping, which
> is probably a more reliable indicator of
On Mon, 2015-11-09 at 21:35 -0800, Andy Lutomirski wrote:
>
> We could do it the other way around: on powerpc, if a PCI device is in
> that range and doesn't have the "bypass" property at all, then it's
> assumed to bypass the IOMMU. This means that everything that
> currently works continues
On Tue, Nov 10, 2015 at 01:04:36PM +1100, Benjamin Herrenschmidt wrote:
> The "in absence of the new DT binding" doesn't make that much sense.
>
> Those platforms use device-trees defined since the dawn of ages by
> actual open firmware implementations, they either have no iommu
> representation
Hello!
Tested-by: Pavel Fedin
Personally i have a small concern about this way of testing. I know many ports
of the kernel to proprietary systems, and they tend to have drivers which just
deal with hardcoded physical memory regions on their own, without even
On 2015-11-10 03:18, Andy Lutomirski wrote:
> On Mon, Nov 9, 2015 at 6:04 PM, Benjamin Herrenschmidt
>> I thus go back to my original statement, it's a LOT easier to handle if
>> the device itself is self describing, indicating whether it is set to
>> bypass a host iommu or not. For L1->L2, well,
The decision on whether to use hardware APIC virtualization used to be
taken globally, based on the availability of the feature in the CPU
and the value of a module parameter.
However, under certain circumstances we want to control it on per-vcpu
basis. In particular, when the userspace
The function to determine if the vector is handled by ioapic used to
rely on the fact that only ioapic-handled vectors were set up to
cause vmexits when virtual apic was in use.
We're going to break this assumption when introducing Hyper-V
synthetic interrupts: they may need to cause vmexits too.
Actually kvm_arch_irq_routing_update() should be
kvm_arch_post_irq_routing_update() as it's called at the end
of irq routing update.
This renaming frees kvm_arch_irq_routing_update function name.
kvm_arch_irq_routing_update() weak function which will be used
to update mappings for arch-specific
SynIC (synthetic interrupt controller) is a lapic extension,
which is controlled via MSRs and maintains for each vCPU
- 16 synthetic interrupt "lines" (SINT's); each can be configured to
trigger a specific interrupt vector optionally with auto-EOI
semantics
- a message page in the guest
A new vcpu exit is introduced to notify the userspace of the
changes in Hyper-V SynIC configuration triggered by guest writing to the
corresponding MSRs.
Changes v4:
* exit into userspace only if guest writes into SynIC MSR's
Changes v3:
* added KVM_EXIT_HYPERV types and structs notes into docs
On Tue, Nov 10, 2015 at 09:37:54PM +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2015-11-09 at 21:35 -0800, Andy Lutomirski wrote:
> >
> > We could do it the other way around: on powerpc, if a PCI device is in
> > that range and doesn't have the "bypass" property at all, then it's
> > assumed to
Signed-off-by: Andrey Smetanin
Reviewed-by: Roman Kagan
Signed-off-by: Denis V. Lunev
CC: Paolo Bonzini
CC: Richard Henderson
CC: Eduardo Habkost
CC: "Andreas Färber"
This patch brings in the necessary changes from the corresponding kernel
patchset. It's included only for completeness; ideally these changes
should arrive via the standard kernel header pull.
Signed-off-by: Andrey Smetanin
Reviewed-by: Roman Kagan
This patch does Hyper-V Synthetic interrupt
controller(Hyper-V SynIC) MSR's support and
migration. Hyper-V SynIC is enabled by cpu's
'hv-synic' option.
This patch does not allow cpu creation if
'hv-synic' option specified but kernel
doesn't support Hyper-V SynIC.
Changes v2:
* activate Hyper-V
Hyper-V SynIC (synthetic interrupt controller) support:
* msr's support
* irq routing setup
* irq injection
* irq ack's callbacks
* event/message pages changes tracking at Hyper-V exit
* Hyper-V test device to test SynIC by kvm-unit-tests
Signed-off-by: Andrey Smetanin
'hyperv-testdev' will be used by kvm-unit-tests
to setup Hyper-V SynIC SINT's routing and to inject
Hyper-V SynIC SINT's.
Hyper-V test device is ISA type device that creates 0x3000
IO memory region and catches write access into it. Every
write operation data decoded into ctl code and parameters
Hyper-V SynIC(synthetic interrupt controller) helpers for
Hyper-V SynIC irq routing setup, irq injection, irq ack
notifications event/message pages changes tracking for future use.
Signed-off-by: Andrey Smetanin
Reviewed-by: Roman Kagan
PAGE_S2_DEVICE is a pgprot val and needs to be accessed using the proper
accessors. Switch to these accessors to avoid errors with
STRICT_MM_TYPECHECK.
Signed-off-by: Laura Abbott
---
Found in the course of other work
---
arch/arm/kvm/mmu.c | 6 --
1 file
On Tue, 2015-11-10 at 15:44 -0800, Andy Lutomirski wrote:
>
> > What about partition <-> partition virtio such as what we could do on
> > PAPR systems. That would have the weak barrier bit.
> >
>
> Is it partition <-> partition, bypassing IOMMU?
No.
> I think I'd settle for just something that
On Tue, Nov 10, 2015 at 01:22:52PM +0100, Paolo Bonzini wrote:
> From: Eric Northup
>
> It was found that a guest can DoS a host by triggering an infinite
> stream of "alignment check" (#AC) exceptions. This causes the
> microcode to enter an infinite loop where the core
On Mon, Nov 02, 2015 at 09:58:14AM -0600, Andrew Jones wrote:
> On Fri, Oct 30, 2015 at 03:32:43PM -0400, Christopher Covington wrote:
> > Hi Drew,
> >
> > On 10/30/2015 09:00 AM, Andrew Jones wrote:
> > > On Wed, Oct 28, 2015 at 03:12:55PM -0400, Christopher Covington wrote:
> > >> Calculate the
On Mon, Nov 09, 2015 at 03:13:15PM -0800, Mario Smarduch wrote:
>
>
> On 11/5/2015 7:02 AM, Christoffer Dall wrote:
> > On Fri, Oct 30, 2015 at 02:56:33PM -0700, Mario Smarduch wrote:
> >> This patch enables arm64 lazy fp/simd switch, similar to arm described in
> >> second patch. Change from
On Tue, 2015-11-10 at 10:45 +0100, Knut Omang wrote:
> Can something be done by means of PCIe capabilities?
> ATS (Address Translation Support) seems like a natural choice?
Euh no... ATS is something else completely
Cheers,
Ben.
--
To unsubscribe from this list: send the line "unsubscribe
2015-11-03 18:47 GMT+08:00 Paolo Bonzini :
>
>
> On 28/10/2015 09:10, Nadav Amit wrote:
>> Here are my 5 cents. Note that vmx_vcpu_reset calls:
>>
>> vmcs_writel(GUEST_RFLAGS, 0x02);
>>
>> (And the RFLAGS value is not cached by KVM, so no consistency problem should
>>
After make lkvm-static & make clean, the dependency files for static
objects (.xxx.static.o.d) are not removed.
Signed-off-by: Xiaochen Shen
Signed-off-by: Dimitri John Ledkov
Signed-off-by: James Hunt
---
Makefile |
Because #DB is now intercepted unconditionally, this callback
only operates on #BP for both VMX and SVM.
Signed-off-by: Paolo Bonzini
---
arch/x86/include/asm/kvm_host.h | 2 +-
arch/x86/kvm/svm.c | 2 +-
arch/x86/kvm/vmx.c | 2 +-
Yes, these can happen. The issue is that benign exceptions are
delivered serially, but two of them (#DB and #AC) can also happen
during exception delivery itself. The subsequent infinite stream
of exceptions causes the processor to never exit guest mode.
Paolo
Eric Northup (1):
KVM: x86:
From: Eric Northup
It was found that a guest can DoS a host by triggering an infinite
stream of "alignment check" (#AC) exceptions. This causes the
microcode to enter an infinite loop where the core never receives
another interrupt. The host kernel panics pretty quickly
This is needed to avoid the possibility that the guest triggers
an infinite stream of #DB exceptions (CVE-2015-8104).
VMX is not affected: because it does not save DR6 in the VMCS,
it already intercepts #DB unconditionally.
Reported-by: Jan Beulich
Cc: sta...@vger.kernel.org
This patchset implements the KVM part of the synthetic interrupt
controller (SynIC) which is a building block of the Hyper-V
paravirtualized device bus (vmbus).
SynIC is a lapic extension, which is controlled via MSRs and maintains
for each vCPU
- 16 synthetic interrupt "lines" (SINT's); each
The open coded tests for checking whether a PTE maps a page as
uncached use a flawed '(pte_val(xxx) & CONST) != CONST' pattern,
which is not guaranteed to work since the type of a mapping is
not a set of mutually exclusive bits
For HYP mappings, the type is an index into the MAIR table (i.e, the
On Tue, Nov 10, 2015 at 03:11:20PM +0100, Ard Biesheuvel wrote:
> The open coded tests for checking whether a PTE maps a page as
> uncached use a flawed '(pte_val(xxx) & CONST) != CONST' pattern,
> which is not guaranteed to work since the type of a mapping is
> not a set of mutually exclusive
On Nov 10, 2015 4:44 PM, "Benjamin Herrenschmidt"
wrote:
>
> On Tue, 2015-11-10 at 15:44 -0800, Andy Lutomirski wrote:
> >
> > > What about partition <-> partition virtio such as what we could do on
> > > PAPR systems. That would have the weak barrier bit.
> > >
> >
> >
On Tue, 2015-11-10 at 20:46 -0800, Andy Lutomirski wrote:
> Me neither. At least it wouldn't be a regression, but it's still
> crappy.
>
> I think that arm is fine, at least. I was unable to find an arm QEMU
> config that has any problems with my patches.
Ok, give me a few days for my headache
On 10/11/2015 13:52, Andrey Smetanin wrote:
> This patch does Hyper-V Synthetic interrupt
> controller(Hyper-V SynIC) MSR's support and
> migration. Hyper-V SynIC is enabled by cpu's
> 'hv-synic' option.
>
> This patch does not allow cpu creation if
> 'hv-synic' option specified but kernel
>
On 10 November 2015 at 13:22, Christoffer Dall
wrote:
> On Tue, Nov 10, 2015 at 10:45:37AM +0100, Ard Biesheuvel wrote:
>> Hi all,
>>
>> I wonder if this is a better way to address the problem. It looks at
>> the nature of the memory rather than the nature of the
On Tue, Nov 10, 2015 at 02:15:45PM +0100, Ard Biesheuvel wrote:
> On 10 November 2015 at 13:22, Christoffer Dall
> wrote:
> > On Tue, Nov 10, 2015 at 10:45:37AM +0100, Ard Biesheuvel wrote:
> >> Hi all,
> >>
> >> I wonder if this is a better way to address the
On 10 November 2015 at 14:40, Christoffer Dall
wrote:
> On Tue, Nov 10, 2015 at 02:15:45PM +0100, Ard Biesheuvel wrote:
>> On 10 November 2015 at 13:22, Christoffer Dall
>> wrote:
>> > On Tue, Nov 10, 2015 at 10:45:37AM +0100, Ard
On 11/09/2015 07:13 PM, Igor Mammedov wrote:
On Fri, 6 Nov 2015 16:31:43 +0800
Xiao Guangrong wrote:
On 11/05/2015 10:49 PM, Igor Mammedov wrote:
On Thu, 5 Nov 2015 21:33:39 +0800
Xiao Guangrong wrote:
On 11/05/2015
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