As a résumé of this discussion I feel that it would be very viable to to
a commercial or non-commercial project that allows for easy use of a
single (or even multiple ) dedicated AMP CPU(s) working together with an
SMP Linux system in a multi core ARM Cortex A9 chip.
Here the supplier would
On 08/05/2013 12:00 PM, Lambrecht Jürgen wrote:
Actually, you can check on ARM community web site, where you will see that the
CortexA9/GIC infrastructure enables AMP implementation.
http://forums.arm.com/index.php?/topic/15656-cortex-a9-amp/
Here I see:
In the Cortex-A9 MPCore Technical
On 08/07/2013 10:23 AM, Michael Schnell wrote:
In the Cortex-A9 MPCore Technical Reference Manual I found the
SMPnAMP Signal which switches between SMP or AMP for each Processor.
I found this:
SMPnAMP - Set whether the processor is part of a coherent domain.
Which does not help, because
I also found:
This processor is in the inner shared domain, and uses its cache
coherency protocol.
I understand that some kind of memory coherency needs to be guaranteed
in AMP applications as well, if memory is used for communication between
the systems.
Of course with AMP can avoid
On 08/03/2013 09:11 PM, Robert Schwebel wrote:
One recent example: on MX6 (quadcore Cortex-A9), when you run a
certain cpuburn tool, the temperature rises up to the maximum allowed
value in just a couple of seconds, and then you either have the choice
to burn your hardware or to use the
On 08/04/2013 11:28 PM, Lambrecht Jürgen wrote:
The Xilinx Zynq is of course purpose-built for this kind of stuff.
Also Altera has such a SoC (System on Chip). My student also found
examples of an AMP solution with Linux/FreeRTOS and Linux/eCos.
I feel that for many virtual Peripheral
On 08/02/2013 06:16 PM, Jon Sevy wrote:
You might try the Open Source Automation Development Labs website for real-time
Linux latency measurements and methodology:
http://www.osadl.org/
Thanks for the pointer !
On the first glace I see that this might help with legal and similar
issues, but
On Mon, Aug 05, 2013 at 09:25:18AM +0200, Michael Schnell wrote:
You can't. And you can't, even if you try to run bare-metal software
on a dedicated core. I can't imagine how for example the cache
influences between the cores could be determined.
This would render all efforts for hard
On 08/05/2013 10:21 AM, Robert Schwebel wrote:
https://www.osadl.org/QA-Farm-Realtime.qa-farm-about.0.html
Interesting stuff !
-Michael
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On 08/05/2013 10:17 AM, Robert Schwebel wrote:
On Mon, Aug 05, 2013 at 09:25:18AM +0200, Michael Schnell wrote:
You can't. And you can't, even if you try to run bare-metal software
on a dedicated core. I can't imagine how for example the cache
influences between the cores could be determined.
Hi,
I am using vanilla linux in an AMP setup on freescale P1022
successfully. The needed
linux bootargs are:
maxcpus=1 mem=448M memmap=64M$0x1C00
Then there is a linux userspace program and a kernel module (using kernel
function mpic_reset_core) to start an application (another OS) on the
On 08/05/2013 11:06 AM, Guenter Ebermann wrote:
I am using vanilla linux in an AMP setup on freescale P1022
successfully
Great to know this !
Thanks,
-Michael
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On 08/04/2013 11:28 PM, Lambrecht Jürgen wrote:
On 08/02/2013 10:33 AM, Michael Schnell wrote:
[snip]
- how to assign certain interrupts to that core and have ISRs run
there only dedicatedly interrupting the main loop and not ever being
blocked by any Linux activity ?
here I found this:
Hi,
On Fri, Aug 02, 2013 at 04:53:50PM +0200, Marco Stornelli wrote:
In fact I need a way to do very guaranteed low latency. regarding the
high clock rate (about 1 GHz) modern ARM chips can provide, maybe
preempt-rt with the cpu affinity might be a decent way to go.
Modern hardware has
Hi Experts.
Is there a kind of official way to set aside one of the available
cores in an SMP system from the Linux OS to do deeply embedded
extremely-low-latency stuff in a kind of single task main loop type
environment ? I.e. creating a true coprocessor from an SMP hardware.
Some of the
On 08/02/2013 01:42 PM, Robert Schwebel wrote:
Before hacking around (which might also lead to interesting solutions),
I would start using a kernel with preempt-rt support and play with the
cpu affinity:
http://lxr.linux.no/#linux+v3.10.4/Documentation/kernel-parameters.txt#L1257
Robert !
Il 02/08/2013 14:13, Michael Schnell ha scritto:
On 08/02/2013 01:42 PM, Robert Schwebel wrote:
Before hacking around (which might also lead to interesting solutions),
I would start using a kernel with preempt-rt support and play with the
cpu affinity:
On 08/02/2013 04:53 PM, Marco Stornelli wrote:
- how to assign an interrupt (e.g. a dedicated timer) to the
subsystem ?
Interrupt handler are kernel thread, so you can schedule your kernel
thread on your normal cpu.
Sorry. I don't understand.
The point I'd like to make is, that for
Il 02/08/2013 17:24, Michael Schnell ha scritto:
On 08/02/2013 04:53 PM, Marco Stornelli wrote:
- how to assign an interrupt (e.g. a dedicated timer) to the
subsystem ?
Interrupt handler are kernel thread, so you can schedule your kernel
thread on your normal cpu.
Sorry. I don't
On 08/02/2013 05:37 PM, Marco Stornelli wrote:
I don't know your hw so my consideration are really general.
The hardware is not decided yet (it will be some A9 thingy). So for me
really general is just fine.
ISRs in rt kernel doesn't exist or at least the only work is to wake
up the kernel
Il 02/08/2013 18:00, Michael Schnell ha scritto:
On 08/02/2013 05:37 PM, Marco Stornelli wrote:
I don't know your hw so my consideration are really general.
The hardware is not decided yet (it will be some A9 thingy). So for me
really general is just fine.
ISRs in rt kernel doesn't exist or
You might try the Open Source Automation Development Labs website for real-time
Linux latency measurements and methodology:
http://www.osadl.org/
\
Jon
Marco Stornelli marco.storne...@gmail.com wrote:
Il 02/08/2013 18:00, Michael Schnell ha scritto:
On 08/02/2013 05:37 PM, Marco Stornelli
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