On Thu, 16 Nov 2006 23:12:19 +0100
Sylvain Munaut [EMAIL PROTECTED] wrote:
* The manual states we should check for the TIP bit before all
PIO transaction. That's not really supported by libata and requires
reimplementing almost all the hooks. But after talking to Freescale,
it turnsout it's
On Fri, 17 Nov 2006 19:04:06 +0100
Arnaud Patard [EMAIL PROTECTED] wrote:
A break; is missing in the cable detection switch() statement, leading
to a wrong detection of the cable type.
Signed-off-by: Arnaud Patard [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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On Sat, 18 Nov 2006 16:20:12 -0500
Jeff Garzik [EMAIL PROTECTED] wrote:
I don't know if they're still concerns, nor if they're fatal concerns
either. But I've been sitting on that patch for nearly five months.
This isn't driver-specific, so a similar change should be applied to the
core.
On Sun, 19 Nov 2006 11:39:23 -0500
Dominik Brodowski [EMAIL PROTECTED] wrote:
Acked-by: Alan Cox [EMAIL PROTECTED]
to both
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On Tue, 28 Nov 2006 14:52:28 +0800
Albert Lee [EMAIL PROTECTED] wrote:
Some devices raise irq early before clearing the BSY.
This patch waits up to 10 microseconds to workaround the early irq problem.
Signed-off-by: Albert Lee [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
The IRQ
The IRQ delivery is async to the I/O so this makes a lot of sense for all
cases.
I don't think that's true unless the controller is doing something funky
as in SET XFERMODE. Can you enlighten me?
It is true for all cases. There is no synchronization between interrupt
delivery and I/O
.
Alan
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patch which leaked a scsi host reference
Signed-off-by: Alan Cox [EMAIL PROTECTED]
diff -u --exclude-from /usr/src/exclude --new-file --recursive
linux.vanilla-2.6.19-rc6-mm1/drivers/scsi/ide-scsi.c
linux-2.6.19-rc6-mm1/drivers/scsi/ide-scsi.c
--- linux.vanilla-2.6.19-rc6-mm1/drivers/scsi/ide
Does this fix it
--- drivers/ata/pata_via.c~ 2006-11-29 15:16:10.961387472 +
+++ drivers/ata/pata_via.c 2006-11-29 15:17:08.784597008 +
@@ -60,7 +60,7 @@
#include linux/libata.h
#define DRV_NAME pata_via
-#define DRV_VERSION 0.2.0
+#define DRV_VERSION 0.2.1
/*
* The
On Thu, 30 Nov 2006 17:43:51 +0800
Albert Lee [EMAIL PROTECTED] wrote:
Some devices raise irq early before clearing the BSY.
This patch adds blacklist and waits up to 10 microseconds to workaround the
early irq problem.
Signed-off-by: Albert Lee [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL
it but got no useful answer.
Its clearly based on some of the GPL IDE controller code and blocks of it
are cut/pasted.
If you want to write the driver then I'm happy to write the description of
the device. It's basically an SFF device with MMIO on BAR5
Alan
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Ok I noiw have a copy of the driver which is clearly marked as GPL and
since it credits me anyway makes it clear enough for anyone I'd think
libata driver will follow, just needs a test victim...
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On Fri, 1 Dec 2006 19:34:16 +0100 (MET)
Olaf Hering [EMAIL PROTECTED] wrote:
The printk in pci_request_region has 'bar + 1', so 6 should be possible
if i becomes 5.
Does the IO region of the last bar look correct?
I've no idea. That really depends upon the platform.
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doing a READ LONG command for me, a very similar state to what Linus reported.
Looks like it may in fact be a chip erratum. Turn off PPE unconditionally
and try and repeat it (if you look at ata_piix right now its turned off
for ATAPI only).
Alan
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layers that the resource was
not allocated. It is reporting that the resource *was* allocated, and at a
bogus address of zero.
If you trust the firmware that is fine, but you need to report the truth,
at which point pci_request_resources() will work correctly.
Alan
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original behavior and drivers/ide's behavior.
Signed-off-by: Tejun Heo [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
One possibility however would be to invert the flag we have now so we can
try turning -on- IRQ polling on some devices in future and maybe figure
it out that way around
it also pops up all over the place with the new EH code and not
the old its damn near impossible to debug any PATA problems that look
like this at the moment.
Alan
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a difference.
Alan
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On Sat, 02 Dec 2006 09:19:43 +1100
We don't have a choice but to trust the firmware on those machines. We
can't assign things ourselves on most of them for various reasons (in
many cases, the hypervisor won't let us).
So you suggest that I clear resource-flags in that case ?
That will do
On Mon, 04 Dec 2006 09:15:10 +0100
Sylvain Munaut [EMAIL PROTECTED] wrote:
This patch adds libata support for the Freescale MPC5200 IDE
controller.
nit timings to PIO0 */
urce(op-node, 0, res_mem);
Acked-by: Alan Cox [EMAIL PROTECTED]
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Wang from SiS Corporation
published on SiS Website.
Signed-off-by: Uwe Koziolek [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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.
Ok so if the pata_sis driver exports
sis_info133 (UDMA 133 port_info structure)
is that sufficient for you to attach the PATA port to the PATA methods
for this chipset ?
Alan
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On Mon, 4 Dec 2006 13:40:26 +0100 (MET)
Olaf Hering [EMAIL PROTECTED] wrote:
the hald media changed polling does really confuse things.
noone knows why the delays are needed, but they give us access to
the CD.
Can you tell me what happens if you completely pull the reset out of the
port just like zero is not a valid IRQ. Stick a real IDE resource at zero
and drivers/ide can't cope.
Alan
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in circulation.
Alan
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) or Greg can give a definitive answer then we can go fix the
offenders now.
Alan
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On Mon, 4 Dec 2006 15:34:09 +0200
Thinus Viljoen [EMAIL PROTECTED] wrote:
How do I go about setting/clearing this nIEN bit from my own module?
Open a handle to /dev/sda and calling some or other IOCTL, perhaps? (
I haven't accessed the HDD on this low level before, so I would
appreciate some
On Mon, 04 Dec 2006 15:26:02 +0100
Tomasz Chmielewski [EMAIL PROTECTED] wrote:
his patch adds VT6421 PATA support to sata_via.
NAK
This shouldn't be compile time
It doesn't handle MWDMA properly
It uses the old error/reset code
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Wants testing... so test and report
Signed-off-by: Alan Cox [EMAIL PROTECTED]
--- linux.vanilla-2.6.19-rc6-mm1/drivers/ata/sata_via.c 2006-11-24
13:58:05.0 +
+++ linux-2.6.19-rc6-mm1/drivers/ata/sata_via.c 2006-12-04 14:57:34.719099648
+
@@ -59,11 +59,14
is that sufficient for you to attach the PATA port to the PATA methods
for this chipset ?
Alan
It should be sufficient .
Consider it done
Signed-off-by: Alan Cox [EMAIL PROTECTED]
Please push with the SATA driver changes to use it.
diff -u --new-file --recursive --exclude-from
is found.
This code has been tested and confirmed to fix the problem on the tested
systems.
Signed-off-by: Alan Cox [EMAIL PROTECTED]
(Most of the hard work done by Stratus however)
diff -u --new-file --recursive --exclude-from /usr/src/exclude
linux.vanilla-2.6.19-rc6-mm1/drivers/ide/ide-cd.c
the drivers/ide driver and wants to do the merge for
drivers/ide (Bart ??) then I'll forward it.
Signed-off-by: Alan Cox [EMAIL PROTECTED]
diff -u --new-file --recursive --exclude-from /usr/src/exclude
linux.vanilla-2.6.19-rc6-mm1/drivers/ata/Kconfig
linux-2.6.19-rc6-mm1/drivers/ata/Kconfig
Was the duplication of timings[] deliberate?
It's actually duplicated in all the PIIX/ICH-alike drivers. I could move
it in them all. Jeff - its copied from your piix driver - shall I move
them all ?
diff -puN
include/linux/pci_ids.h~pata_it8213-add-new-driver-for-the-it8213-card-tidy
On Wed, 06 Dec 2006 11:58:23 +0100
Uwe Koziolek [EMAIL PROTECTED] wrote:
There is a wrong order to initialize the drivers. The IDE-platform
driver was initialized before pata_sis.
So the generic platform driver is driving the IDE controller instead of
pata_sis.
I would suggest not trying to
compute for the DMA cases. Also the other
pattern to these reports is ATAPI, although that might I guess be a
symptom of slave.
The other problem is that mmio bus reset is broken, but the AMD always
uses PIO cycles so that shouldn't be involved.
Alan (still baffled by this one)
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The ata timing computation code makes some mistakes in PIO5/6 because a
check was not updated correctly when I put this support into the kernel.
Signed-off-by: Alan Cox [EMAIL PROTECTED]
diff -u --new-file --recursive --exclude-from /usr/src/exclude
linux.vanilla-2.6.19-rc6-mm1/drivers/ata
On Mon, 11 Dec 2006 20:33:34 -0800 (PST)
Leigh [EMAIL PROTECTED] wrote:
Hi
How did this go? I doubt I'm the only one who fell afoul of the has linux
drivers implication on initio's website...
I know its early days, but any idea when this might be ready for production?
I sent Tejun the
Kasichainula.
Signed-off-by: Tejun Heo [EMAIL PROTECTED]
Cc: Manoj Kasichainula [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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Kmemleak by Catalin Marinas.
Signed-off-by: Tejun Heo [EMAIL PROTECTED]
Cc: Catalin Marinas [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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quirk to match the current -mm
behaviour with the ATA resource tree. Otherwise - nice driver.
Alan
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is
relevant because of the way the BAR values work we know legacy bar values
are never 8 so the test is sufficient [but should be commented about
the assumption]
Alan
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Waste of space having a busproc routine. The maintainer removed all the
usable hotplug support from old IDE so this might as well be dropped.
I took over IDE when hotplug was already broken (late 2.5), moreover IDE
hotplug support has been always a quick hack according to its original
Unfortunately it seems that not everybody has moved on. It is not
about your not accepted patches but about the maintainer removed
all the usable hotplug support from old IDE false accusations which
are unproven and untrue.
I invite anyone who cares to study the archive.
Welcome back to my
that the original version included (well,
it had much more mess)...
Signed-off-by: Sergei Shtylyov [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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+config PATA_IT8213
+ tristate IT8213 PATA support (Experimental)
+ depends on PCI EXPERIMENTAL
+ help
+ This option enables support for the ITE 821 PATA
Typo (IT8213) - probably my fault but only just noticed it
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On Sat, 16 Dec 2006 18:22:16 +0200
Taneli Vähäkangas [EMAIL PROTECTED] wrote:
Hello,
I'm using pata_ali with ULi M1697, which has this:
00:16.0 IDE interface [0101]: ALi Corporation M5229 IDE [10b9:5229] (rev c7)
IDE works with either pata_ali or alim15x3, but pata_ali complains
at
On Sun, 17 Dec 2006 10:50:08 +0900
Tejun Heo [EMAIL PROTECTED] wrote:
Driver for Initio 162x SATA controllers. ATA r/w, ATAPI r, hotplug
and suspend/resume work. ATAPI w (recording, that is) broken.
Does atapi write work if you just clip it to PIO for writing ?
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this
and found the slave channel end of DMA handling was using the wrong port
I think.
Signed-off-by: Alan Cox [EMAIL PROTECTED]
--- linux.vanilla-2.6.20-rc3/drivers/ata/pata_hpt37x.c 2007-01-01
21:43:27.0 +
+++ linux-2.6.20-rc3/drivers/ata/pata_hpt37x.c 2007-01-02 14:30
When the old IDE layer calls into methods in the driver during error
handling it is essentially random whether ide_lock is already held. This
causes a deadlock in the atiixp driver which also uses ide_lock internally
for locking.
Switch to a private lock instead.
Signed-off-by: Alan Cox [EMAIL
For 16 byte commands via SG_IO you know the command is 16 bytes long as
the command length is passed in hdr-cmd_len which becomes rq-cmd_len.
Is that not sufficient to avoid this ATA_16 test if you pass it on to the
required functions ?
No. The SCSI code calculates the expected cmd_len
old libata and lots of problems have been fixed
since then, including some that do sound rather like your description.
Alan
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On Thu, 4 Jan 2007 07:42:54 +0100
Olaf Hering [EMAIL PROTECTED] wrote:
On Mon, Dec 04, Alan wrote:
On Mon, 4 Dec 2006 13:40:26 +0100 (MET)
Olaf Hering [EMAIL PROTECTED] wrote:
the hald media changed polling does really confuse things.
noone knows why the delays are needed
the
CONFIG ifdef stuff goes away too.
Alan
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IMO creating a new check_atapi_dma function for first-gen chips would be
the preferred way to add this check.
A mode filter would be even better, that will mean the list of modes on
the device is correct and ATAPI devices are shown as PIO on such a
controller.
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or poked around in ugly places your
argument would make sense. In this case I don't think your argument makes
sense, but if you want a pointless tiny pata_sis module to waste memory
on everyones boxes you can just ask and I'll send you a diff or two.
Alan
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Far better would be, then, to combine the drivers into a single ata_sis
driver, it sounds like.
Why do pure PATA users need all the SATA crap loaded ?
Alan
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Alan/Bart/anybody, could you enlighten me why hwif-rw_disk() method came
into being at all?
When you needed to wrap entire disk operations. The -dma_ methods only
wrap DMA commands.
For the current support hardware it can probably go, no idea if anyone
embedded uses it any more and can't
I tried both the 2.6.19 version and one based on 2.6.20-rc4, same
problem. Is there anything specific the driver needs to do work with
disks 137GB?
It is the boundary for LBA48 accesses.
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in by asm-generic/pci.h
Please fix the IA64 tree to do the right thing.
Alan
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think this causes a bug as they don't use the
DMA layer, but its a bug waiting to happen if the mmio==1 case doesn't
get handled correctly or BUG()
Alan
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On Fri, 12 Jan 2007 05:28:00 +0100
Bartlomiej Zolnierkiewicz [EMAIL PROTECTED] wrote:
[PATCH] ide: add ide_use_fast_pio() helper
* add ide_use_fast_pio() helper for use by host drivers
* add DMA capability and autodma checks to ide_use_dma()
- au1xxx-ide/it8213/it821x drivers didn't check
Generally looks very good - couple of odd items I noticed I've send
replies about. Good to have someone working on the old IDE code again.
Alan
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It seems that it821x_tune_chipset() is buggy since it sends SET FEATURES
command even when in smart mode. Shouldn't there be don't tune flag
in it812x_fixups() to tell it821x_tune_chipset() to not send SET FEATURES
commands?
It's itdev-smart but falls through to ide_config_drive_speed while
the
latency yourself directly AND the card could be plugged into an arbitary
PCI slot on a 32bit PC.
Alan
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also the disk is a Westen Digital raptor and it's probably the most
benchmarked drive one could get so I was not expecting a problem with
the drive.
A lot of early NCQ firmware seems to reduce performance and cause
problems. At least one other raptor is in our don't NCQ list in the
kernel
Should be fixed in the current upstream code by Tejun's updates and some
workarounds for mode setting.
Alan
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On Tue, 16 Jan 2007 14:55:51 +0900
Tejun Heo [EMAIL PROTECTED] wrote:
Some uli controllers have stuck SIMPLEX bit which can't be cleared
with ata_pci_clear_simplex(), but the controller is capable of doing
DMAs on both channels simultaneously. Ignore it.
Acked-by: Alan Cox [EMAIL PROTECTED
On Tue, 16 Jan 2007 19:46:14 +0900
Akira Iguchi [EMAIL PROTECTED] wrote:
When enabling IRQ, ap-ops-irq_on is checked.
Because most drivers can use ata_irq_on() as is, this
patch allows ap-ops-irq_on to be NULL.
If it is NULL, ata_irq_on() are used.
Acked-by: Alan Cox [EMAIL PROTECTED
On Tue, 16 Jan 2007 19:46:23 +0900
Akira Iguchi [EMAIL PROTECTED] wrote:
When enabling IRQ, ap-ops-irq_on is checked.
Because most drivers can use ata_irq_on() as is, this
patch allows ap-ops-irq_on to be NULL.
If it is NULL, ata_irq_on() are used.
I believe you can now remove the
On Tue, 16 Jan 2007 17:45:56 -0500
Jeff Garzik [EMAIL PROTECTED] wrote:
Alan wrote:
The other oddity I've been seeing is that I am getting zero length
commands,
such as TEST_UNIT_READY with a dma_dir of DMA_FROM_DEVICE. Shouldn't this
be
DMA_NONE? I'm still tracking this down.
I
);
+ if (rc)
+ dev_printk(KERN_WARNING, cs5530_0-dev,
+WARNING: failed to set MWI\n);
Please drop this patch. Users don't need to scared by this bogus message.
Alan
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The PCI IDE spec specifies the simplex bit, but a /vast majority/ of
controllers, PATA as well as SATA, hardwire the bit, or program it to a
value set by BIOS. As such, most drivers really should /just know/ that
their hardware need never worry about this odd simplex concept.
The ULi is
On Mon, 22 Jan 2007 21:17:33 +0300
Ugh, I'm not seeing any *actual* support for MW/SW DMA in this driver...
Thats long been broken. Should be correct in the libata driver
Alan
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Ugh, I'm not seeing any *actual* support for MW/SW DMA in this
driver...
Thats long been broken. Should be correct in the libata driver
Here's a surprise for you. pata_cmd64x copied the SW/MW DMA setup code
from the IDE driver. No way it could be working. You may check
problems which run after the probe.
There isn't a good way to handle this with the old IDE layer. PMac does
it by walking the hwif array itself (without any proper locking). Adding
the call you need might be a good idea, but moving fixup will break
things.
Alan
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for debugging/testing
courtesy of a company using them and the one I have seems to pass all the
testing I've thrown at it.
Alan
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is the regression. Even the ancient drivers/ide code
does this properly.
Alan
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address setup time.
(searching mailboxes more...) Oh, and the dropping of common PIO mode
selection was agreed upon by Jeff and Alan.
One way or the other, this only affects PATA devices and as long as all
PATA LLDs guarantee that selection timing isn't violated, this can go.
I thought PATA
seem to do
it under any OS so I assume its ok. The timing stuff should be pretty
much the same for both ide and libata as libata lifted most of the rather
nice ide-timing stuff directly from the old IDE layer.
Alan
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. The polling
SETXFER is I fear just hiding the real issue which we've seen on the VIA,
SiS and also with a weird timing fix on the sl8c205
Alan
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Were it not for the PATA and interrupt storm bits, I would say that
Marvell 6145 works with a simple PCI ID addition.
The 6101 driver should drive the 6145 pata port via the legacy registers
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that IORDY *must*
be enabled.
Yes. It is more complex than the current code handles. That's one reason
I added ata_pio_need_iordy(), because it would need to change and
hardcoding it would be particularly ugly.
This will matter for supporting some utterly ancient junk.
Alan
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Atttaching my (already obsolete) patch, just in case...
Thanks. Double checking my code it looks similar although I don't bother
with the DMA check as the drivers know that in DMA cases the PIO call will
be made before the DMA mode is set when DMA modes are in use.
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On Tue, 30 Jan 2007 11:02:03 +0800
Albert Lee [EMAIL PROTECTED] wrote:
patch 2/2 (revised):
- Fix drive-waiting_for_dma to work with CDB-intr devices.
- Do the dma status clearing in ide_intr() and add a new
hwif-ide_dma_clear_irq for Intel controllers.
This should probably only be done for
: task_no_data_intr: status=0x51 { DriveReady SeekComplete Error }
hda: task_no_data_intr: error=0x04 { DriveStatusError }
ide: failed opcode was: 0x37
We try and set the disk size to 185074430006016 sectors.. it objects
unsuprisingly to this proposal.
Alan
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Acked-by: Alan Cox [EMAIL PROTECTED]
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.
Alan
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have been fixed a while ago with the others that had that
same bug. Must have escaped somewhere.
Acked-by: Alan Cox [EMAIL PROTECTED]
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they are the same and thus not report an HPA.
This essentially confirms your hardware or driver is bust.
Alan
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I don't have the hardware combination to test this one so would
appreciate people testing it before it goes anywhere further
diff -u --new-file --recursive --exclude-from /usr/src/exclude
linux.vanilla-2.6.20-rc6-mm3/drivers/ata/pata_pdc2027x.c
linux-2.6.20-rc6-mm3/drivers/ata/pata_pdc2027x.c
-existant media is 512 bytes per
sector or zero. Setting it to 1 causes us to generate 512 bytes/sector
accesses and error properly.
Signed-off-by: Alan Cox [EMAIL PROTECTED]
Based on a fix found lurking in an ancient bugzilla entry since about 2004
(ugghhh)
diff -u --new-file --recursive --exclude
Two fixes in this test patch. One of them allows old CF cards to refuse
pio mode setting, and one to wait for the drive to settle after a set
features changes the speed settings, which is based upon the workarounds
used by drivers/ide.
Please test and report back if you have an afflicted system.
-off-by: Alan Cox [EMAIL PROTECTED]
--- linux.vanilla-2.6.20-rc6-mm3/include/linux/libata.h 2007-01-31
14:20:43.0 +
+++ linux-2.6.20-rc6-mm3/include/linux/libata.h 2007-01-31 17:19:04.703229512
+
@@ -1052,6 +1053,8 @@
/**
* ata_busy_wait - Wait for a port status register
On Thu, 01 Feb 2007 11:58:09 -0500
Mark Lord [EMAIL PROTECTED] wrote:
Fix libata to perform CDB len validation per device
rather than per host. This way, validation still works
when we have a mix of 12-byte and 16-byte devices on
a common host interface.#
Users can pass 16byte commands in
version 2.6.18, 2.6.19.1 and they give the same result. If I connect
the drive to my SiI 3114 controller and boot 2.6.20-rc6 the drive
works perfectly.
Very interesting it is tied to the controller, but that fits what Tejun
was seeing.
I also tried booting kernel version 2.6.17. It gives an
This patch makes JMicron PCI quirk clear SATA IDE mode bits and set
AHCI mode bits and remove the respective part from pata_jmicron.
Tested on JMB361, 363 and 368.
Signed-off-by: Tejun Heo [EMAIL PROTECTED]
Acked-by: Alan Cox [EMAIL PROTECTED]
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Note that both normal commands and EH commands timeouts are adjusted
to 7 secs, but cache flushses still have 30sec timeout. This is a
side effect of the way sd makes use of sdev-timeout, but this is a
good side effect in that ATA spec requires cache flushes are given
longer timeout.
Our
and stuff up and going
again before stalling at the other end of the faulty area.
Alan
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user setup. Either work or fail within n seconds
Alan
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your system requirements are, what the system is trying to do (i.e.,
when trying to recover a failing but not dead yet disk, IO errors should
be as quick as possible and we should choose an IO scheduler that does
not combine IO's).
If this is the right strategy for disk recovery for a
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