From: Guo Ren <ren_...@c-sky.com>
CK810 pmu only support event with index 0-8 and 0xd; CK860 only
support event 1~4, 0xa~0x1b. So do not register unsupport event
to hardware cache event, which may leader to unknown behavior.
Signed-off-by: Guo Ren <ren_...@c-sky.com>
Signed-off-by: Mao Han <han_...@c-sky.com>
Cc: Guo Ren <guo...@kernel.org>
Cc: linux-c...@vger.kernel.org
---
arch/csky/kernel/perf_event.c | 60 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/arch/csky/kernel/perf_event.c b/arch/csky/kernel/perf_event.c
index af09885..dc84dc7 100644
--- a/arch/csky/kernel/perf_event.c
+++ b/arch/csky/kernel/perf_event.c
@@ -737,6 +737,20 @@ static const int csky_pmu_hw_map[PERF_COUNT_HW_MAX] = {
#define CACHE_OP_UNSUPPORTED 0xffff
static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = {
+#ifdef CONFIG_CPU_CK810
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0x5,
+ [C(RESULT_MISS)] = 0x6,
+ },
+#else
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x14,
[C(RESULT_MISS)] = 0x15,
@@ -746,9 +760,10 @@ static const int
csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(RESULT_MISS)] = 0x17,
},
[C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0x5,
- [C(RESULT_MISS)] = 0x6,
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
+#endif
},
[C(L1I)] = {
[C(OP_READ)] = {
@@ -765,6 +780,20 @@ static const int
csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
},
},
[C(LL)] = {
+#ifdef CONFIG_CPU_CK810
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0x7,
+ [C(RESULT_MISS)] = 0x8,
+ },
+#else
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x18,
[C(RESULT_MISS)] = 0x19,
@@ -774,29 +803,48 @@ static const int
csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(RESULT_MISS)] = 0x1b,
},
[C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0x7,
- [C(RESULT_MISS)] = 0x8,
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
+#endif
},
[C(DTLB)] = {
+#ifdef CONFIG_CPU_CK810
[C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x5,
- [C(RESULT_MISS)] = 0xb,
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
+#else
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = 0x14,
+ [C(RESULT_MISS)] = 0xb,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = 0x16,
+ [C(RESULT_MISS)] = 0xb,
+ },
+#endif
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(ITLB)] = {
+#ifdef CONFIG_CPU_CK810
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+#else
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x3,
[C(RESULT_MISS)] = 0xa,
},
+#endif
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
--
2.7.4
