:
> - Improve Kconfig description, fix typos and other comments.
> - Update target kernelversion in sysfs doc.
> - Fix issues reported by kbuild.
> - Simplify pcie driver by using pcim_xxx functions.
>
> Changes from v5:
> - Improve functions/APIs naming per suggestion from Alan
On Mon, Mar 5, 2018 at 8:08 PM, Wu Hao <hao...@intel.com> wrote:
> On Mon, Mar 05, 2018 at 04:46:02PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao...@intel.com> wrote:
>>
>> Hi Hao,
>
> Hi Alan,
>
> Thanks for the comments
On Wed, Mar 7, 2018 at 1:47 PM, Rob Herring <r...@kernel.org> wrote:
> On Thu, Mar 01, 2018 at 06:19:32PM -0600, richard.g...@linux.intel.com wrote:
>> From: Alan Tull <at...@kernel.org>
>>
>> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manage
On Sun, Mar 11, 2018 at 11:29 PM, Wu Hao wrote:
> On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com
> wrote:
>>
>> Hi Hao,
>>
>> I do think we should consider different hw implementations with this code
>> because it does look like most of it is
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> This patch adds compat_id support when driver creates the platform
> device for dfl-fme-region. It allows dfl-fme-region platform driver
> to create fpga-region with correct compat_id.
>
> Signed-off-by: Wu Hao
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> This patch introduces a compat_id member and sysfs interface for each
> fpga-region, e.g userspace applications could read the compat_id
> from the sysfs interface for compatibility checking before PR.
>
> Signed-off-by:
On Wed, Feb 28, 2018 at 11:49 PM, Wu Hao <hao...@intel.com> wrote:
> On Wed, Feb 28, 2018 at 05:06:57PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao...@intel.com> wrote:
>> > +
>> > + compat_id.id_l = readq(fme_pr + FME_PR_I
yi.z.zh...@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> Signed-off-by: Wu Hao <hao...@intel.com>
Acked-by: Alan Tull <at...@kernel.org>
> ---
> v3: split from another patch
> use c
d-off-by: Enno Luebbers <enno.luebb...@intel.com>
> Signed-off-by: Shiva Rao <shiva@intel.com>
> Signed-off-by: Christopher Rauer <christopher.ra...@intel.com>
> Signed-off-by: Zhang Yi <yi.z.zh...@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong
On Wed, Mar 7, 2018 at 7:24 PM, Rob Herring <r...@kernel.org> wrote:
> On Wed, Mar 7, 2018 at 4:20 PM, Alan Tull <at...@kernel.org> wrote:
>> On Wed, Mar 7, 2018 at 1:47 PM, Rob Herring <r...@kernel.org> wrote:
>>> On Thu, Mar 01, 2018 at 06:19:32PM -0600, ric
On Wed, Mar 14, 2018 at 12:21 AM, Wu Hao wrote:
>> > +
>> > + drvdata->cdev = cdev;
>> > +
>> > +enum_info_free_exit:
>> > + fpga_enum_info_free(info);
>>
>> This is the only place I saw fpga_enum_info_free being called.
>
> It doesn't need to keep the enumeration
lt;p.pis...@gmail.com>
Acked-by: Alan Tull <at...@kernel.org>
Replace GPLv2 boilerplate with SPDX in FPGA code that came from me or
from Altera.
Signed-off-by: Alan Tull <at...@kernel.org>
---
drivers/fpga/altera-fpga2sdram.c | 13 +
drivers/fpga/altera-freeze-bridge.c| 13 +
drivers/fpga/altera-hps2fpga.c
an extra device for each child region to hold
drvdata.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@huawei.com>
Acked-by: Moritz Fischer <m...@kernel.org>
---
v2: No change to this patch in v2 of patchset
v3: Add Moritz' ack
v4: Reword header
---
. However, PCIe based
devices may have multiple FPGA mgr/bridge/regions under one PCIe
device. Without these changes, PCIe-based solutions have to create an
extra device for each child mgr/bridge/region to hold drvdata.
Alan Tull (4):
fpga: region: don't use drvdata in common fpga code
fpg
);
Update the drivers that call fpga_mgr_register with the new API.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@huawei.com>
---
v2: change fpga_mgr_register to not need parent device param
v3: minor changes to make diffs smaller and more obviously correct
fpga_bridge *br);
Update the drivers that call fpga_bridge_register with the new API.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@huawei.com>
---
v2: change fpga_bridge_register to not need parent device param
fix undeclared - s/dev/>dev/
v3: minor
"region->dev.groups = groups;"
after calling fpga_region_create.
Update the drivers that call fpga_region_register with the new API.
Signed-off-by: Alan Tull <at...@kernel.org>
---
v2: This patch added in this version of the patchset
v3: minor changes to make diffs smaller
From: Paolo Pisati <p.pis...@gmail.com>
This patch adds support to the FPGA manager for programming
MachXO2 device’s internal flash memory, via slave SPI.
Signed-off-by: Paolo Pisati <p.pis...@gmail.com>
[at...@kernel.org: use existing FPGA mgr API]
Signed-off-by: Alan Tull <a
From: Paolo Pisati <p.pis...@gmail.com>
Add dt binding documentation details for Lattice MachXO2 FPGA configuration
over Slave SPI interface.
Signed-off-by: Paolo Pisati <p.pis...@gmail.com>
Acked-by: Rob Herring <r...@kernel.org>
Acked-by: Moritz Fischer <m...@kernel.org
This is Paolo's v10 with a minor fixup. I had asked him to rebase his
patch on a branch with a new FPGA manager API. That API change ended
up not going upstream, so I've fixed it for the current API. This patch
applies cleanly on the current linux-next.
Paolo Pisati (2):
dt: bindings: fpga:
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
One minor thing below.
> On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
> reprogrammed for different functions. It connects to the FPGA
> infrastructure("blue bistream") via a Port. Port CSRs are
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> From: Kang Luwei
>
> The FPGA Management Engine (FME) provides power, thermal management,
> performance counters, partial reconfiguration and other functions. For each
> function, it is packaged
On Thu, Mar 22, 2018 at 1:07 AM, Wu Hao <hao...@intel.com> wrote:
> On Wed, Mar 21, 2018 at 09:55:52AM -0700, Moritz Fischer wrote:
>> On Wed, Mar 21, 2018 at 10:50:01AM +0800, Wu Hao wrote:
>> > On Tue, Mar 20, 2018 at 03:32:34PM -0500, Alan Tull wrote:
>> > >
On Mon, Apr 2, 2018 at 8:36 PM, Wu Hao <hao...@intel.com> wrote:
> On Mon, Apr 02, 2018 at 02:06:56PM -0500, Alan Tull wrote:
>> On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao <hao...@intel.com> wrote:
>> > On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
>>
On Tue, Apr 24, 2018 at 12:29 AM, Jan Kiszka <jan.kis...@web.de> wrote:
> On 2018-04-24 00:38, Frank Rowand wrote:
>> Hi Jan,
>>
>> + Alan Tull for fpga perspective
>>
>> On 04/22/18 03:30, Jan Kiszka wrote:
>>> On 2018-04-11 07:42, Jan Kiszka wr
On Tue, Apr 24, 2018 at 11:08 AM, Alan Tull <at...@kernel.org> wrote:
> On Tue, Apr 24, 2018 at 12:29 AM, Jan Kiszka <jan.kis...@web.de> wrote:
>> On 2018-04-24 00:38, Frank Rowand wrote:
>>> Hi Jan,
>>>
>>> + Alan Tull for fpga perspective
>>&
On Tue, Apr 24, 2018 at 3:56 PM, Frank Rowand <frowand.l...@gmail.com> wrote:
> Hi Alan,
>
> On 04/23/18 15:38, Frank Rowand wrote:
>> Hi Jan,
>>
>> + Alan Tull for fpga perspective
>>
>> On 04/22/18 03:30, Jan Kiszka wrote:
>>> On 2018-04-11
On Thu, Mar 29, 2018 at 4:39 PM, Moritz Fischer <m...@kernel.org> wrote:
> On Thu, Mar 29, 2018 at 03:42:51PM -0500, Alan Tull wrote:
>> On Thu, Mar 29, 2018 at 12:06 PM, Greg KH <gre...@linuxfoundation.org> wrote:
>>
>> Hi Greg,
>>
>> >> -
On Wed, Mar 28, 2018 at 11:26 AM, Alan Tull <at...@kernel.org> wrote:
> On Fri, Mar 23, 2018 at 7:27 AM, Paolo Pisati <p.pis...@gmail.com> wrote:
>
> Hi Paolo,
One more thing. The api for registering a FPGA manager is changing.
It won't be hard to adapt. I've pushed a
26, 2018 at 12:21:23PM -0500, Alan Tull wrote:
>> On Thu, Mar 22, 2018 at 11:33 PM, Wu Hao <hao...@intel.com> wrote:
>>
>> >> > +
>> >> > +/*
>> >> > + * This function resets the FPGA Port and its accelerator (AFU) by
>> >&
On Tue, Mar 27, 2018 at 3:20 PM, <richard.g...@linux.intel.com> wrote:
> From: Alan Tull <at...@kernel.org>
>
> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
>
> Signed-off-by: Alan Tull <at...@kernel.org>
> ---
> v2: this patch is ad
On Thu, Mar 29, 2018 at 12:06 PM, Greg KH wrote:
Hi Greg,
>> -int fpga_region_register(struct device *dev, struct fpga_region *region)
>> +int fpga_region_register(struct fpga_region *region)
>> {
>> + struct device *dev = region->parent;
>> int id, ret =
On Thu, Mar 29, 2018 at 12:01 PM, Greg KH <gre...@linuxfoundation.org> wrote:
Hi Greg,
> On Thu, Mar 29, 2018 at 08:36:53AM -0700, Moritz Fischer wrote:
>> From: Alan Tull <at...@kernel.org>
>>
>> Part of patchset that changes the following fpga_*_registe
On Thu, Mar 29, 2018 at 12:03 PM, Greg KH <gre...@linuxfoundation.org> wrote:
Hi Greg,
> On Thu, Mar 29, 2018 at 08:36:54AM -0700, Moritz Fischer wrote:
>> From: Alan Tull <at...@kernel.org>
>>
>> Change fpga_mgr_register to not set or use drvdata.
>>
>
On Thu, Mar 22, 2018 at 11:33 PM, Wu Hao wrote:
>> > +
>> > +/*
>> > + * This function resets the FPGA Port and its accelerator (AFU) by
>> > function
>> > + * __fpga_port_disable and __fpga_port_enable (set port soft reset bit and
>> > + * then clear it). Userspace can do
On Mon, Apr 2, 2018 at 10:13 AM, Paolo Pisati wrote:
Hi Paolo,
Thanks for making the changes I asked for. Except... is there a
reason to not get state in machxo2_spi_state?
It turns out the API will change again. I can do the fixup when that happens.
Alan
> This patch
On Mon, Apr 2, 2018 at 12:43 PM, kbuild test robot wrote:
This is complaining because Paolo's patch was rebased onto a branch
that had an API change.
Alan
> Hi Paolo,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on linus/master]
> [also
On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao <hao...@intel.com> wrote:
> On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
>> On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao <hao...@intel.com> wrote:
>>
>> Hi Hao,
>>
>> Currently there is one set of f
of fpga_region_register is changed to alloc the
fpga_region struct, fill it in, and pass it to the register
function.
Signed-off-by: Alan Tull <at...@kernel.org>
---
v2: This patch added in this version of the patchset
v3: minor changes to make diffs smaller and more obviously correct
---
Documen
/regions
under one PCIe device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@huawei.com>
---
v2: change fpga_mgr_register to not need p
/bridge/regions
under one pcie device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@huawei.com>
---
v2: change fpga_bridge_register
.
However PCIe based devices may have multiple FPGA mgr/bridge/regions
under one PCIe device. Without these changes, the PCIe solution has
to create an extra device for each child mgr/bridge/region to hold
drvdata.
Signed-off-by: Alan Tull <at...@kernel.org>
Reported-by: Jiuyue Ma <majiu...@h
in the main DT overlay code.
* Minor code cleanup to make it more obvious that the changes
were not breaking anything
* Added Moritz' ack on patch 1
Alan Tull (4):
fpga: region: don't use drvdata in common fpga code
fpga: manager: don't use drvdata in common fpga code
fpga: bridge: don't
On Fri, Mar 23, 2018 at 7:27 AM, Paolo Pisati wrote:
Hi Paolo,
Looking good. A few things below. Also, when you post, please use
the '-v' parameter of 'git format-patch' to add the version to the
subject line such as [PATCH v9].
> This patch adds support to the FPGA
On Tue, Mar 27, 2018 at 3:11 PM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> On Tue, Mar 27, 2018 at 12:59 PM, Alan Tull <at...@kernel.org> wrote:
>> Change fpga_mgr_register to not set or use drvdata.
>>
>> Change the register/unregister function par
igned-off-by: Paolo Pisati <p.pis...@gmail.com>
>> Acked-by: Rob Herring <r...@kernel.org>
> Acked-by: Moritz Fischer <m...@kernel.org>
Acked-by: Alan Tull <at...@kernel.org>
Thanks,
Alan
>> ---
>> .../bindings/fpga/lattice-machxo2-spi.txt | 29
>>
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
Elsewhere we discussed moving #defines used only in this driver either
to this .c file or to a similarly named .h file. A couple minor
things below.
> This patch adds fpga manager driver for FPGA Management Engine (FME).
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> Device Feature List (DFL) defines a feature list structure that creates
> a link list of feature headers within the MMIO space to provide an
> extensible way of adding features. This patch introduces a kernel module
> to
On Wed, Mar 21, 2018 at 1:04 PM, Joe Perches wrote:
> On Wed, 2018-03-21 at 18:35 +0100, Paolo Pisati wrote:
>> This patch adds support to the FPGA manager for programming
>> MachXO2 device’s internal flash memory, via slave SPI.
>
> style trivia:
>
>> diff --git
a...@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> Signed-off-by: Wu Hao <hao...@intel.com>
Acked-by: Alan Tull <at...@kernel.org>
Alan
ff-by: Shiva Rao <shiva@intel.com>
> Signed-off-by: Christopher Rauer <christopher.ra...@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> Signed-off-by: Wu Hao <hao...@intel.com>
> Acked-by: Alan Tull <at...@kernel.org>
> Acke
om>
> Signed-off-by: Christopher Rauer <christopher.ra...@intel.com>
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> Signed-off-by: Wu Hao <hao...@intel.com>
> ---
> v2: moved the code to drivers/fpga folder as suggested by Alan Tull.
> ad
On Tue, Mar 20, 2018 at 2:10 AM, Wu Hao wrote:
>> > +static int afu_mmap(struct file *filp, struct vm_area_struct *vma)
>> > +{
>> > + struct fpga_afu_region region;
>> > + struct platform_device *pdev = filp->private_data;
>> > + struct feature_platform_data
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> +static int
> +build_info_create_dev(struct build_feature_devs_info *binfo,
> + enum fpga_id_type type, const char *name,
> + void __iomem *ioaddr)
> +{
> + struct
On Tue, Mar 20, 2018 at 2:10 AM, Wu Hao <hao...@intel.com> wrote:
> On Mon, Mar 19, 2018 at 03:10:28PM -0500, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao...@intel.com> wrote:
>>
>> Hi Hao,
>>
>> > From: Xiao Guangrong <guangro
On Thu, Mar 1, 2018 at 12:17 AM, Wu Hao <hao...@intel.com> wrote:
> On Wed, Feb 28, 2018 at 04:55:15PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <hao...@intel.com> wrote:
>>
>> Hi Hao,
>
> Hi Alan,
>
> Thanks for the review
;
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> Signed-off-by: Wu Hao <hao...@intel.com>
> ---
> v2: moved the code to drivers/fpga folder as suggested by Alan Tull.
> switched to GPLv2 license.
> removed status from FPGA_FME_PORT_PR
On Wed, Apr 25, 2018 at 3:07 PM, Jan Kiszka <jan.kis...@web.de> wrote:
> On 2018-04-25 20:40, Frank Rowand wrote:
>> On 04/24/18 22:23, Jan Kiszka wrote:
>>> On 2018-04-24 22:56, Frank Rowand wrote:
>>>> Hi Alan,
>>>>
>>>> On 04/23/18
On Wed, Apr 25, 2018 at 12:41 PM, Frank Rowand <frowand.l...@gmail.com> wrote:
> On 04/25/18 07:59, Alan Tull wrote:
>> On Tue, Apr 24, 2018 at 3:56 PM, Frank Rowand <frowand.l...@gmail.com> wrote:
>>> Hi Alan,
>>>
>>> On 04/23/18 15:38, Frank
On Fri, Oct 12, 2018 at 8:12 PM Bridgers, Vince
wrote:
>
>
>
> -Original Message-
> From: Thor Thayer
> Sent: Friday, October 12, 2018 3:49 PM
> To: Greg KH
> Cc: geert+rene...@glider.be; jho...@kernel.org; at...@kernel.org;
> bhelg...@google.com; james.hart...@sondrel.com;
On Mon, Oct 15, 2018 at 1:09 PM Frank Rowand wrote:
>
> On 10/15/18 01:24, Geert Uytterhoeven wrote:
> >
> > Please say explicitly that tree_version contains a 32-bit unsigned
> > decimal number, which is incremented before and after every change.
> > I had to deduce that from the code.
>
> Good
Hi Greg,
Please take these four patches that have been reviewed on the mailing
list. They all apply and build cleanly on the current linux-next and
char-misc-testing. The first 3 add managed create functions for the
FPGA API. The fourth is documentation rework.
Alan
Alan Tull (4):
fpga
Add devm_fpga_bridge_create() which is the managed
version of fpga_bridge_create().
Change current bridge drivers to use
devm_fpga_bridge_create().
Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
---
Documentation/driver-api/fpga/fpga-bridge.rst | 3 ++
drivers
On Mon, Oct 15, 2018 at 7:04 PM Frank Rowand wrote:
>
> On 10/15/18 13:38, Alan Tull wrote:
> > On Mon, Oct 15, 2018 at 1:09 PM Frank Rowand wrote:
> >>
> >> On 10/15/18 01:24, Geert Uytterhoeven wrote:
> >>>
> >>> Please say explicitly that
On Mon, Oct 15, 2018 at 7:28 PM wrote:
Hi Frank,
Thanks for all your work on this!
> From: Frank Rowand
>
> When an overlay is applied or removed, the live devicetree visible in
> /proc/device-tree/, aka /sys/firmware/devicetree/base/, reflects the
> changes. There is no method for user
On Tue, Jul 5, 2016 at 11:45 AM Ricardo Ribalda Delgado
wrote:
I've stumbled across a of_node_get/put imbalance that happens when the
fixed rate clock is added and deleted using device tree. The cause is
that this driver calls of_clk_add_provider() when probed, but doesn't
call
When the fixed rate clock is created by devicetree,
of_clk_add_provider is called. Add a call to
of_clk_del_provider in the remove function to balance
it out.
Signed-off-by: Alan Tull
---
drivers/clk/clk-fixed-rate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk-fixed
On Thu, Oct 18, 2018 at 3:24 PM Stephen Boyd wrote:
>
> Quoting Alan Tull (2018-10-18 12:20:58)
> > On Tue, Jul 5, 2016 at 11:45 AM Ricardo Ribalda Delgado
> > wrote:
> >
> > I've stumbled across a of_node_get/put imbalance that happens when the
> > fixed r
On Thu, Oct 18, 2018 at 3:22 PM Stephen Boyd wrote:
>
> Quoting Alan Tull (2018-10-18 12:54:11)
> > When the fixed rate clock is created by devicetree,
> > of_clk_add_provider is called. Add a call to
> > of_clk_del_provider in the remove function to balance
> &
On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
wrote:
Hi Nava,
>
> This series of patches are created On top of the
> below repo.
> //git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
> BRANCH: next/drivers.
IIUC this is dependent on some patches that aren't released yet.
Please make
On Fri, Oct 19, 2018 at 3:49 AM Nava kishore Manne
wrote:
Hi Nava,
Just some nits, below.
>
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v1:
> Created a Seperate(New) DT binding file as
>
On Mon, Oct 15, 2018 at 9:39 PM wrote:
Hi Frank,
>
> From: Frank Rowand
>
> Add checks:
> - attempted kfree due to refcount reaching zero before overlay
> is removed
> - properties linked to an overlay node when the node is removed
> - node refcount > one during node removal in a
Clarify the intention that interfaces and upper layers use
regions rather than managers directly.
Rearrange API documentation to better group the API functions
used to create FPGA mgr/bridge/regions and the API used for
programming FPGAs.
Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Add devm_fpga_region_create() which is the
managed version of fpga_region_create().
Change current region drivers to use
devm_fpga_region_create().
Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
---
Documentation/driver-api/fpga/fpga-region.rst | 3 ++
drivers
Add devm_fpga_mgr_create() which is the managed
version of fpga_mgr_create().
Change current FPGA manager drivers to use
devm_fpga_mgr_create()
Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
---
Documentation/driver-api/fpga/fpga-mgr.rst | 13 +++---
drivers
Hi Greg,
Please take these four patches that have been reviewed on the mailing
list. They all apply and build cleanly on the current linux-next and
char-misc-testing. The first 3 add managed create functions for the
FPGA API. The fourth is documentation rework.
Alan
Alan Tull (4):
fpga
On Tue, Oct 23, 2018 at 4:26 AM Moritz Fischer wrote:
>
> Hi Andreas,
>
> we're getting there :) It seems your mail setup is still a bit
> funky though. Did you use git send-email / git format-patch?
>
> On Tue, Oct 23, 2018 at 09:01:39AM +, Andreas Puhm wrote:
> > From
le the
> device is actively being accessed by the driver for programming.
>
> This allows both PCAP and ICAP interfaces to be used for PR.
>
> Signed-off-by: Mike Looijmans
> Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Thanks for submitting!
Alan
> ---
> v2: Move th
; properly determine if FPGA Manager functionality can be safely
> > enabled.
> >
> > Fixes: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
> > Signed-off-by: Andreas Puhm
> > Signed-off-by: Anatolij Gustschin
>
> Reviewed-by: Moritz Fischer
Acked-
Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
---
drivers/fpga/altera-cvp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 610a155..144fa2a 100644
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/al
Hi Greg,
Please take these four small fpga fixes patches. They
have been reviewed on the mailing list and apply
cleanly on current linux-next and char-misc-testing.
Thanks,
Alan
Anatolij Gustschin (1):
fpga: altera-cvp: fix 'bad IO access' on x86_64
Andreas Puhm (1):
fpga: altera-cvp: Fix
.
This allows both PCAP and ICAP interfaces to be used for PR.
Signed-off-by: Mike Looijmans
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/zynq-fpga.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index bb82efe
Acked-by: Alan Tull
---
drivers/fpga/dfl-fme-pr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c
index 0b84053..fe5a557 100644
--- a/drivers/fpga/dfl-fme-pr.c
+++ b/drivers/fpga/dfl-fme-pr.c
@@ -444,10 +444,8 @@ static void
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/altera-cvp.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 144fa2a..7395085 100644
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/altera-cvp.c
@@ -40
On Sun, Sep 30, 2018 at 10:49 AM Greg Kroah-Hartman
wrote:
Hi Greg,
>
> On Wed, Sep 12, 2018 at 09:43:26AM -0500, Alan Tull wrote:
> > From: Moritz Fischer
> >
> > Use platform_set_drvdata rather than dev_set_drvdata
> > to match the platform_get_drvdata
On Sun, Sep 30, 2018 at 10:48 AM Greg Kroah-Hartman
wrote:
Hi Greg,
>
> On Wed, Sep 12, 2018 at 09:43:27AM -0500, Alan Tull wrote:
> > From: Moritz Fischer
> >
> > Use platform_get_drvdata() in remove() function of
> > the platform driver rather than
From: Moritz Fischer
Use platform_get_drvdata() in remove() function of
the platform driver rather than dev_get_drvdata()
to match the platform_set_drvdata in the probe().
Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/dfl-fme-region.c | 2 +-
1 file changed, 1 insertion
Hi Greg,
Here's a reposting of the two small fixes for fpga, please
take them in. They've been reviewed on the mailing list
and apply cleanly on today's char-misc-test.
Thanks,
Alan
Moritz Fischer (2):
fpga: of-fpga-region: Use platform_set_drvdata
fpga: dfl-fme-region: Use
From: Moritz Fischer
Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.
Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/of-fpga-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On Mon, Nov 12, 2018 at 12:02 PM Greg Kroah-Hartman
wrote:
>
> On Mon, Nov 12, 2018 at 09:46:53AM -0600, Alan Tull wrote:
> > On Sun, Sep 30, 2018 at 10:48 AM Greg Kroah-Hartman
> > wrote:
> >
> > Hi Greg,
> >
> > >
> > > On Wed, Sep 12, 2
My interest here was in having some discussion on whether connectors
are a good match for handling FPGAs.
The relevant use model is where a user applies a DT overlay targeting
an FPGA region after the kernel has booted. That overlay initiates
FPGA programming and then adds nodes for the new FPGA
intel stratix10 soc fpga manager driver")
> Signed-off-by: Nicolas Saenz Julienne
Acked-by: Alan Tull
> ---
> drivers/fpga/stratix10-soc.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
> index a1a09e04fa
-by: Anatolij Gustschin
Acked-by: Alan Tull
---
drivers/fpga/altera-cvp.c | 34 --
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 7395085..35c3aa5 100644
--- a/drivers/fpga/altera-cvp.c
+++ b
data. This allows driver binding to dynamically
added PS-SPI devices (e.g. when added via spi_new_device() after
hot-plugging).
Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
---
drivers/fpga/altera-ps-spi.c | 40 +++-
1 file changed, 35 insertions(+), 5
Hi Greg,
Please take these two fpga fixes patches. They have been reviewed
on the mailing list and apply cleanly on current linux-next.
Thanks,
Alan
Anatolij Gustschin (2):
fpga: altera-cvp: fix probing for multiple FPGAs on the bus
fpga: mgr: altera-ps-spi: enable usage on non-dt
On Tue, Sep 11, 2018 at 7:37 AM Colin King wrote:
Hi Colin,
>
> From: Colin Ian King
>
> Trivial fix to spelling mistake in the documentation
I took a look, there's other misspellings in this doc. I'd like to
get them all in one patch if possible. If I have time I'll add them
to this patch
A couple drivers were accessing the region struct after it had been
freed. Save off the pointer to the mgr before the region struct gets
freed.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
drivers/fpga/dfl-fme-region.c | 4 +++-
drivers/fpga/of-fpga-region.c | 3 ++-
2 files changed
fpga_bridge_dev_match() returns a FPGA bridge struct, not a
FPGA manager struct so s/manager/bridge/.
Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
---
drivers/fpga/fpga-bridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga
From: Moritz Fischer
Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.
Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
---
drivers/fpga/of-fpga-region.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
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