On Wed, 2012-11-07 at 09:06 +0100, Pantelis Antoniou wrote:
Hi Grant,
On Nov 6, 2012, at 9:45 PM, Grant Likely wrote:
On Tue, Nov 6, 2012 at 7:34 PM, Pantelis Antoniou
pa...@antoniou-consulting.com wrote:
On Nov 6, 2012, at 12:14 PM, Grant Likely wrote:
On Tue, Nov 6, 2012 at 10:30
From: Jamie Iles ja...@jamieiles.com
The controller supports interrupts on bank A (up to 8 interrupt
sources). Use the generic IRQ chip to implement interrupt support for
this bank.
Cc: Grant Likely grant.lik...@secretlab.ca
Cc: Linus Walleij linus.wall...@stericsson.com
Acked-by: Rob Herring
From: Alan Tull at...@altera.com
* Changes to get gpio-dwapb (originally v3.2-rc7) driver building and
working on current kernel.
* Use linear irq domain.
* Fix setting irq edge type for 'rising' and 'both'.
* Support as a loadable module.
* Use bgpio_chip's spinlock during register
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
v5: - handle sparse bank population correctly
v3: - depend on rather than select IRQ_DOMAIN
- split IRQ support
From: Alan Tull at...@altera.com
Resending Jamie's gpio-dwapb driver patches. Adding a patch to get
them building with current irq domain stuff.
Alan Tull
Alan Tull (1):
use linear irq domain in gpio-dwapb
Jamie Iles (2):
gpio: add a driver for the Synopsys DesignWare APB GPIO block
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Alan Tull at...@altera.com
v6: - (atull) squash the set of patches
- use linear irq domain
From: Alan Tull at...@altera.com
Version 6 - Implementing Sebastian's suggestions.
To make reviewing more to-the-point, I squashed all three commits
into one. I hope that expedites things rather than getting in the
way, we will see.
I am currently leaving nr-gpios as a required property
On Wed, 2013-10-02 at 17:35 +0200, Michal Simek wrote:
Through firmware interface:
cat /sys/class/fpga_manager/fpga0/name
echo -n fpga.bin /sys/class/fpga_manager/fpga0/firmware
Through sysfs bin file:
cat /sys/class/fpga_manager/fpga0/fpga_config_state
echo -n write_init
On Fri, 2013-10-04 at 19:44 +0200, Michal Simek wrote:
On 10/04/2013 06:46 PM, H. Peter Anvin wrote:
On 10/04/2013 07:28 AM, Michal Simek wrote:
On 10/04/2013 04:21 PM, H. Peter Anvin wrote:
Yes; I never got too corner Greg ;)
Greg Kroah-Hartman gre...@linuxfoundation.org wrote:
On
On Fri, 2013-10-04 at 17:27 +0200, Michal Simek wrote:
Hi,
On 10/03/2013 11:46 PM, Alan Tull wrote:
On Wed, 2013-10-02 at 17:35 +0200, Michal Simek wrote:
Through firmware interface:
cat /sys/class/fpga_manager/fpga0/name
echo -n fpga.bin /sys/class/fpga_manager/fpga0/firmware
On Fri, 2013-10-04 at 18:28 +0200, Michal Simek wrote:
On 10/02/2013 07:46 PM, Jason Gunthorpe wrote:
On Wed, Oct 02, 2013 at 05:35:58PM +0200, Michal Simek wrote:
+What: /sys/class/fpga_manager/fpgadev-id/fpga_config_state
+Date: October 2013
+KernelVersion:
On Wed, 2013-09-18 at 14:32 -0600, Jason Gunthorpe wrote:
On Wed, Sep 18, 2013 at 03:15:17PM -0400, Jason Cooper wrote:
+ Jason Gunthorpe
Thanks, looks interesting, we could possibly use this interface if it
met our needs..
On Wed, Sep 18, 2013 at 05:56:39PM +0200, Michal Simek
On Thu, 2013-09-19 at 07:18 -0700, Greg KH wrote:
On Thu, Sep 19, 2013 at 04:10:46PM +0200, Michal Simek wrote:
On 09/19/2013 04:06 PM, Greg KH wrote:
On Thu, Sep 19, 2013 at 02:52:37PM +0200, Pavel Machek wrote:
On Thu 2013-09-19 13:22:00, Michal Simek wrote:
On 09/19/2013 01:17 PM,
+/**
+ * fpga_mgr_attr_read - Read data from fpga
+ * @dev: Pointer to the device structure
+ * @attr: Pointer to the device attribute structure
+ * @buf: Pointer to the buffer location
+ *
+ * Function reads fpga bitstream and copy them to output buffer
+ *
+ * Returns the
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Alan Tull at...@altera.com
v7: - use irq_generic_chip
- support one irq per gpio line or one irq
From: Alan Tull at...@altera.com
Minor cleanup from v7 as noted below.
Hi Jamie,
I changed the interrupt implementation of your driver to work with the
current kernel (wouldn't build othewise). Could you please test and
let me know if this will work for you?
Alan
Jamie Iles (1):
gpio: add
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Alan Tull at...@altera.com
Reviewed-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
v8: - remove
From: Alan Tull at...@altera.com
Fix size-cells to show use of OF_GPIO_ACTIVE_LOW flag.
Signed-off-by: Alan Tull at...@altera.com
---
.../devicetree/bindings/gpio/snps-dwapb-gpio.txt |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Jamie Iles ja...@jamieiles.com
Signed-off-by: Alan Tull at...@altera.com
Reviewed-by: Sebastian Hesselbarth
From: Alan Tull at...@altera.com
fix build error with this message:
kernel/irq/Kconfig:41:error: recursive dependency detected!
kernel/irq/Kconfig:41: symbol GENERIC_IRQ_CHIP is selected by GPIO_DWAPB
drivers/gpio/Kconfig:131: symbol GPIO_DWAPB depends on IRQ_DOMAIN
kernel/irq/Kconfig:46
On Tue, 2013-10-08 at 15:00 +0200, Michal Simek wrote:
On 10/07/2013 05:07 PM, H. Peter Anvin wrote:
Special soft IP presenting a PCI device to the host.
ok. It means that you should need just different backend for this device
which is able to communicate over PCI.
I still can't see why
On Fri, 2013-10-04 at 16:33 -0700, Greg Kroah-Hartman wrote:
On Fri, Oct 04, 2013 at 11:12:13AM -0700, H. Peter Anvin wrote:
On 10/04/2013 10:44 AM, Michal Simek wrote:
If you look at it in general I believe that there is wide range of
applications which just contain one bitstream
On Thu, 2013-09-19 at 13:02 +0200, Michal Simek wrote:
On 09/19/2013 12:08 PM, Pavel Machek wrote:
Hi!
The firmware approach is interesting. It might be less flexible
compared with my original code (see link to git below) that this is
On the other hand... that's the interface world
I have ported the altera fpga manager driver to work with your version
of the fpga manager framework. It works fine if I use the
firmware_class.c's built-in support to load the firmware, but not with a
userspace helper.
Hi Michal,
I cleaned up my udev rules and now I see the userspace
On Tue, 2013-09-24 at 17:58 +0200, Michal Simek wrote:
Hi,
On 09/24/2013 05:55 PM, Alan Tull wrote:
I have ported the altera fpga manager driver to work with your version
of the fpga manager framework. It works fine if I use the
firmware_class.c's built-in support to load
* Add this udev rule:
SUBSYSTEM==firmware, ACTION==add, RUN+=/lib/udev/hotplug-script
* Check that there aren't other 'firmware' udev rules to get in the
way.
Hm, don't do that, all modern distros will not do firmware loading
through udev anymore, so please don't try to add
For the Zynq based product I am working on, we encourage the end user to
create their own bitstreams to customize their application. So we need
an easy way for the user to load a bitstream. cat foo.bin /dev/xdevcfg
works well for us.
You probably don't care if this will be
cat
On Mon, May 19, 2014 at 2:37 PM, Thor Thayer tthayer.li...@gmail.com wrote:
diff --git
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..8f8746b
--- /dev/null
+++
On Thu, May 22, 2014 at 4:42 AM, Sebastian Andrzej Siewior
bige...@linutronix.de wrote:
On 05/16/2014 05:01 PM, Linus Walleij wrote:
OK this patch is ACKed by Alan so I would like to apply it but:
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding:
On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote:
On Tue, May 20, 2014 at 9:44 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Tue, May 20, 2014 at 09:31:06AM -0500, Alan Tull wrote
On Tue, May 27, 2014 at 2:42 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, May 27, 2014 at 02:12:17PM -0500, Alan Tull wrote:
On Tue, May 27, 2014 at 2:11 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Wed, May 21, 2014 at 10:38:34AM -0500, Thor Thayer wrote
On Wed, May 28, 2014 at 2:01 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, May 27, 2014 at 03:57:47PM -0500, Alan Tull wrote:
On Tue, May 27, 2014 at 2:42 PM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
On Tue, May 27, 2014 at 02:12:17PM -0500, Alan Tull wrote:
On Tue
. Just realized that it was not the case.
v1…v2:
- using the lopp again but breaking the assignment of type and
handler out of the loop as suggested by delicious quinoa.
Can I have an ACK from Jamie || Alan on this patch so I can apply
it?
Yours,
Linus Walleij
Yes
Acked-by: Alan
From: Alan Tull at...@altera.com
Hi Linus,
If you don't have any further comments, can you take this patch?
Alan
Jamie Iles (1):
gpio: add a driver for the Synopsys DesignWare APB GPIO block
.../devicetree/bindings/gpio/snps-dwapb-gpio.txt | 59 +++
drivers/gpio/Kconfig
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Jamie Iles ja...@jamieiles.com
Signed-off-by: Alan Tull at...@altera.com
Reviewed-by: Sebastian Hesselbarth
with 29 gpios, the
last
one with 27. This patch adds the three controller with the gpio driver which
is
now sitting the gpio tree.
Cc: devicet...@vger.kernel.org
Acked-by: Alan Tull at...@altera.com
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
v1…v2:
- #gpio
On Wed, Jul 9, 2014 at 3:07 PM, Thor Thayer tthayer.li...@gmail.com wrote:
On Thu, Jun 26, 2014 at 4:45 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Jun 25, 2014 at 10:15:26PM +0100, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Add the Altera SDRAM EDAC bindings
be providing register access for this range of registers to a
few drivers, so syscon does that without any trouble.
Alan Tull
aka
delicious quinoa
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Jamie Iles ja...@jamieiles.com
Signed-off-by: Alan Tull at...@altera.com
Reviewed-by: Sebastian Hesselbarth
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of GPIO pins.
Signed-off-by: Jamie Iles ja...@jamieiles.com
Signed-off-by: Alan Tull at...@altera.com
Reviewed-by: Sebastian Hesselbarth
On Sat, Aug 23, 2014 at 9:54 AM, Mark Brown broo...@kernel.org wrote:
On Sat, Aug 23, 2014 at 07:00:44AM -0700, Guenter Roeck wrote:
On 08/22/2014 05:31 PM, atull wrote:
of_get_regulator_init_data() will only have an error if it cannot alloc
the regulator_init_data struct. That's why I did
On Sat, Aug 23, 2014 at 10:10 AM, Guenter Roeck li...@roeck-us.net wrote:
On 08/22/2014 02:45 PM, Mark Brown wrote:
On Fri, Aug 22, 2014 at 04:11:34PM -0500, at...@opensource.altera.com
wrote:
From: Alan Tull at...@opensource.altera.com
Add regulator with support for enabling or disabling
Supports a 2 line by 16 character LCD module over I2C.
Alan Tull (2):
newhaven lcd: device tree bindings documentation
add newhaven lcd tty driver on i2c
.../devicetree/bindings/tty/newhaven_lcd.txt | 21 +
drivers/tty/Kconfig|5 +
drivers/tty
/plat data.
Brightness can be set from a sysfs file, for example:
* echo 6 /sys/devices/soc.0/ffc04000.i2c/i2c-0/0-0028/brightness
Signed-off-by: Alan Tull at...@opensource.altera.com
---
drivers/tty/Kconfig|5 +
drivers/tty/Makefile |1
Add documention for the newhaven lcd device tree bindings.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
.../devicetree/bindings/tty/newhaven_lcd.txt | 21
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/tty
:
$ echo enabled \
/sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup
$ echo -n mem /sys/power/state
Signed-off-by: Alan Tull at...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Steffen Trumtrar
DDR in
self-refresh mode.
Alan Tull (2):
ARM: socfpga: support suspend to ram
ARM: socfpga: dts: add sdram controller dt binding doc
.../arm/altera/socfpga-sdram-controller.txt| 12 ++
arch/arm/mach-socfpga/Kconfig | 10 +-
arch/arm/mach-socfpga/Makefile
Add binding doc for Altera SOCFPGA SDRAM controller.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v4: Add bindings doc
v5: No change for v5
v6: No change for v6
---
.../arm/altera/socfpga-sdram-controller.txt| 12
1 file changed, 12 insertions(+)
create mode
DDR in
self-refresh mode.
Alan Tull (2):
ARM: socfpga: support suspend to ram
ARM: socfpga: dts: add sdram controller dt binding doc
.../arm/altera/socfpga-sdram-controller.txt| 12 ++
arch/arm/mach-socfpga/Kconfig | 10 +-
arch/arm/mach-socfpga/Makefile
Add binding doc for Altera SOCFPGA SDRAM controller.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v4: Add bindings doc
v5: No change for v5
---
.../arm/altera/socfpga-sdram-controller.txt| 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation
:
$ echo enabled \
/sys/devices/soc/ffc02000.serial0/tty/ttyS0/power/wakeup
$ echo -n mem /sys/power/state
Signed-off-by: Alan Tull at...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Steffen Trumtrar
Add binding doc for Altera SOCFPGA SDRAM controller.
Signed-off-by: Alan Tull at...@opensource.altera.com
---
v4: Add bindings doc
---
.../arm/altera/socfpga-sdram-controller.txt| 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicetree/bindings
/state
Signed-off-by: Alan Tull at...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Arnd Bergmann a...@arndb.de
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Steffen Trumtrar s.trumt...@pengutronix.de
---
v2: use Generic on-chip SRAM driver to allocate ocram
rm fncpy_align since
tree binding document for the Altera
SOCFPGA SDRAM controller that is used to put DDR in
self-refresh mode.
Alan Tull (2):
ARM: socfpga: support suspend to ram
ARM: socfpga: dts: add sdram controller dt binding doc
.../arm/altera/socfpga-sdram-controller.txt| 12 ++
arch
examples in the kernel. So this
function call will only work the first time.
Alan Tull
+ if (ret = len)
+ return -ENOMEM;
+
return i;
}
@@ -243,6 +248,9 @@ int led_classdev_register(struct device *parent, struct
led_classdev *led_cdev)
int ret
On Mon, Dec 14, 2015 at 11:16 AM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> Hi Alan,
>
> On Thu, Dec 10, 2015 at 3:37 PM, <at...@opensource.altera.com> wrote:
>> From: Alan Tull <at...@opensource.altera.com>
>>
>> For v14 I'm dropping th
Add pre-apply and pre-remove notifications.
For pre-apply notifications that result from creating an overlay,
include a device node to the overlay fragment in of_reconfig_data.
If a pre-apply notifier return error, reject the changeset.
Signed-off-by: Alan Tull <at...@opensource.altera.
of_overlay_notify_data {
struct device_node *overlay;
struct device_node *target;
};
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: add missing 'static inline' in of.h
---
drivers/of/overlay.c | 47 ++-
include/linux/of.h
.
Alan Tull (6):
fpga: add bindings document for fpga region
ARM: socfpga: add bindings document for fpga bridge drivers
add sysfs document for fpga bridge class
fpga: add fpga bridge framework
fpga: fpga-region: device tree control for FPGA
ARM: socfpga: fpga bridge driver support
New bindings document for FPGA Region to support programming
FPGA's under Device Tree control
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
v9: initial version added to this patchset
v10: s/fpga/FPGA/g
replac
of_overlay_notify_data {
struct device_node *overlay;
struct device_node *target;
};
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
drivers/of/overlay.c | 47 ++-
include/linux/of.h | 25 +
2 files chang
* fpga_bridges_put
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: Minor cleanup
v12: Bump version to line up with simple fpga bus
Remove sysfs
Improve get/put functions, get the low level driver too.
Clean up class implementation
Add kernel doc documentation
FPGA Regions support programming FPGA under control of the Device
Tree.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v9: initial version (this patch added during rest of patchset's v9)
v10: request deferral if fpga mgr or bridges not available yet
cleanup as fpga manage
Add bindings documentation for Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
--
v15: Document added in v15 of patch set
v16: No change to this patch in v16 of patch set
v17: No change to this patch in v17 of patch set
---
Documentation/ABI/testing
during probe. If the property
does not exist, the driver will leave the bridge in its
current state.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
v2:
on next-20160216 and Pantelis' current
bbb-overlays branch.
Alan Tull (1):
of/overlay: of overlay callbacks
drivers/of/overlay.c | 90 +-
include/linux/of.h | 31 +
2 files changed, 120 insertions(+), 1 deletion(-)
--
1.7.9.5
matches a handler's id, the handler
gets called.
The following 4 cases are handled: pre-apply, post-apply,
pre-remove, and post-remove.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
drivers/of/overlay.c | 90 +-
include/linux/of.h
that uses pre-apply and post-remove
handlers. Tested on next-20160216 and Pantelis' current
bbb-overlays branch.
Alan Tull (1):
of/overlay: of overlay callbacks
drivers/of/overlay.c | 90 +-
include/linux/of.h | 31 +
2 files
matches a handler's id, the handler
gets called.
The following 4 cases are handled: pre-apply, post-apply,
pre-remove, and post-remove.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
drivers/of/overlay.c | 90 +-
include/linux/of.h
On Fri, Mar 4, 2016 at 1:44 AM, qiujiang wrote:
> This patch converts device node to fwnode in
> dwapb_port_property for designware gpio driver,
> so as to provide a unified data structure for DT
> and ACPI bindings.
>
> Acked-by: Andy Shevchenko
>
On Tue, Mar 8, 2016 at 8:26 PM, Linus Walleij wrote:
> On Fri, Mar 4, 2016 at 2:44 PM, qiujiang wrote:
>
>> This patchset adds gpio-signaled acpi events support for power button on
>> hisilicon
>> D02 board.
>>
>> The three patches respectively:
>>
On Fri, Mar 25, 2016 at 9:31 PM, qiujiang wrote:
> - if (pp->idx == 0 &&
> - of_property_read_bool(port_np, "interrupt-controller")) {
> - pp->irq = irq_of_parse_and_map(port_np, 0);
> + if (dev->of_node &&
On Wed, Mar 23, 2016 at 6:41 AM, Jiang Qiu <qiuji...@huawei.com> wrote:
> 在 2016/3/11 4:27, Andy Shevchenko 写道:
>> On Thu, Mar 10, 2016 at 9:09 PM, Alan Tull <delicious.qui...@gmail.com>
>> wrote:
>>> On Fri, Mar 4, 2016 at 1:44 AM, qiujiang <qiuji...@huaw
target
and the overlay:
struct of_overlay_notify_data {
struct device_node *overlay;
struct device_node *target;
};
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: add missing 'static inline' in of.h
v3: fix build for !OF_OVERLAY in of.h
add a note in the
e between fixup series is something like 24h. Thus,
> waiting for v10 at least tomorrow or even next week.
>
> Linus, for my point of view next version should be fine and final. The
> current code is in a good shape already.
Reviewed, tested v9, looks good.
Alan Tull
>
>>
>&g
On Thu, Jul 14, 2016 at 3:54 PM, Paul Gortmaker
<paul.gortma...@windriver.com> wrote:
> On Tue, Jul 12, 2016 at 3:36 PM, Alan Tull <at...@opensource.altera.com>
> wrote:
>> This framework adds API functions for enabling/
>> disabling FPGA bridges under kernel contro
Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
drivers/fpga/Kconfig | 6 +
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga-a10.c | 573 ++
during probe. If the property
does not exist, the driver will leave the bridge in its
current state.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
v2:
adding small
patches to fix whatever else.
Alan Tull (6):
fpga: add bindings document for fpga region
ARM: socfpga: add bindings document for fpga bridge drivers
add sysfs document for fpga bridge class
fpga: add fpga bridge framework
fpga: fpga-region: device tree control for FPGA
ARM
Add bindings documentation for Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
New bindings document for FPGA Region to support programming
FPGA's under Device Tree control
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
v9: initial version added to this patchset
v10: s/fpga/FPGA/g
replac
New patch submission for FPGA Manager support for the Altera
SoCFPGA Arria10 plus device tree bindings.
Alan Tull (2):
ARM: socfpga: add bindings doc for arria10 fpga manager
fpga-manager: Add Socfpga Arria10 support
.../bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 19 +
drivers/fpga
Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
.../bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documen
FPGA Regions support programming FPGA under control of the Device
Tree.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v9: initial version (this patch added during rest of patchset's v9)
v10: request deferral if fpga mgr or bridges not available yet
cleanup as fpga manage
* fpga_bridges_put
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: Minor cleanup
v12: Bump version to line up with simple fpga bus
Remove sysfs
Improve get/put functions, get the low level driver too.
Clean up class implementation
Add kernel doc documentation
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
--
v15: Document added in v15 of patch set
v16: No change to this patch in v16 of patch set
v17: No change to this patch in v17 of patch set
v18: No change to this patch
tream is encrypted.
>>
>> The low-level driver will deal with the flag, or return an error,
>> if encrypted bitstreams are not supported.
>>
>> Signed-off-by: Moritz Fischer <m...@kernel.org>
>> Cc: Alan Tull <at...@kernel.org>
>> Cc: Michal Sim
On Tue, Feb 21, 2017 at 11:38 PM, Moritz Fischer
wrote:
Hi Moritz,
> Hi all,
>
> On Tue, Feb 21, 2017 at 9:12 PM, Jason Gunthorpe
> wrote:
>> On Tue, Feb 21, 2017 at 07:49:19PM -0800, Moritz Fischer wrote:
>>
>>> fdt does this out of
On Sat, Feb 18, 2017 at 2:45 PM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> On Sat, Feb 18, 2017 at 02:10:43PM -0600, Alan Tull wrote:
>> On Sat, Feb 18, 2017 at 6:45 AM, Nadathur, Sundar
>> <sundar.nadat...@intel.com> wrote:
>>
>> > Hi all,
>
On Fri, Feb 17, 2017 at 11:14 AM, Li, Yi <yi1...@linux.intel.com> wrote:
> hi Alan
>
>
> On 2/15/2017 10:14 AM, Alan Tull wrote:
>>
>> Document that getting a reference to a FPGA Manager has been
>> separated from locking the FPGA Mangager for use.
>>
>
On Fri, Feb 17, 2017 at 11:52 AM, Moritz Fischer <m...@kernel.org> wrote:
> Alan,
>
> small nits inline
Hi Moritz,
Thanks for the review!
Alan
>
> On Wed, Feb 15, 2017 at 8:14 AM, Alan Tull <at...@kernel.org> wrote:
>> Document that getting a reference to a F
On Sun, Feb 19, 2017 at 9:00 AM, Alan Tull <delicious.qui...@gmail.com> wrote:
> On Sat, Feb 18, 2017 at 2:45 PM, Moritz Fischer
> <moritz.fisc...@ettus.com> wrote:
>> On Sat, Feb 18, 2017 at 02:10:43PM -0600, Alan Tull wrote:
>>> On Sat, Feb 18, 2017 at 6:45 AM, N
On Sat, Feb 18, 2017 at 6:45 AM, Nadathur, Sundar
wrote:
> Hi all,
>Interesting discussion. The discussion so far has brought out many
> concerns such as OS independence. There is an existing format, well-known to
> developers, with widespread support, and which
On Tue, Feb 21, 2017 at 10:35 AM, Alan Tull <delicious.qui...@gmail.com>
Hi Greg,
Would it be helpful for us to resend patches for you to take with you
on cc? Or is it enough that they are on lkml?
Thanks,
Alan Tull
wrote:
> On Tue, Feb 21, 2017 at 7:55 AM, Michal Simek &
On Mon, Feb 20, 2017 at 5:49 PM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> Hi Alan,
>
> On Sun, Feb 19, 2017 at 3:16 PM, Alan Tull <delicious.qui...@gmail.com> wrote:
>> On Sun, Feb 19, 2017 at 9:00 AM, Alan Tull <delicious.qui...@gmail.com>
>> wro
On Tue, Feb 21, 2017 at 12:36 PM, Michal Simek <michal.si...@xilinx.com> wrote:
> On 21.2.2017 19:26, Alan Tull wrote:
>> On Tue, Feb 21, 2017 at 10:35 AM, Alan Tull <delicious.qui...@gmail.com>
>>
>> Hi Greg,
>>
>> Would it be helpful for us to res
ypted to the fpga-region and ultimately to the low-level driver.
>>
>> Signed-off-by: Moritz Fischer <m...@kernel.org>
>> Cc: Alan Tull <at...@kernel.org>
>> Cc: Michal Simek <michal.si...@xilinx.com>
>> Cc: Sören Brinkmann <soren.b
e booted in secure mode.
>>
>> In order for on-the-fly decryption to work, the PCAP clock rate
>> needs to be lowered via the PCAP_RATE_EN bit.
>>
>> Signed-off-by: Moritz Fischer <m...@kernel.org>
>> Cc: Alan Tull <at...@kernel.org>
>> Cc: Michal Simek <
On Wed, Feb 22, 2017 at 10:44 AM, Moritz Fischer
<moritz.fisc...@ettus.com> wrote:
> On Wed, Feb 22, 2017 at 8:33 AM, Alan Tull <delicious.qui...@gmail.com> wrote:
>> On Tue, Feb 21, 2017 at 11:38 PM, Moritz Fischer
>> <moritz.fisc...@ettus.com> wrot
1 - 100 of 1677 matches
Mail list logo