Hi All,
I have few queries on of_platform_populate and of_platform_bus_probe functions.
Use-case is, I want to explicitly register platform devices from some nodes at
post-core or late-init level(like child@1).
And I don't want of_platform_populate to register platform devices for that
node
On 31/10/12 15:21, Rob Herring wrote:
On 10/31/2012 09:54 AM, Srinivas KANDAGATLA wrote:
Hi All,
I have few queries on of_platform_populate and of_platform_bus_probe
functions.
Use-case is, I want to explicitly register platform devices from some nodes
at post-core or late-init level
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch add new code to correctly add resources into platform device.
Issue with the existing code was the resources are added as flat entry
without creating any tree, this is very much different to what non-dt
platform code does
On 23/10/12 14:15, Rob Herring wrote:
Adding lkml. DT patches should go to both lists.
On 10/23/2012 05:30 AM, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
As part of of_platform_populate call, the existing code iterates each
child node and then creates
On 23/10/12 14:15, Rob Herring wrote:
re-sending my reply again, as it did not appear in my inbox from dt
mailing list.
Adding lkml. DT patches should go to both lists.
On 10/23/2012 05:30 AM, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
As part
On 01/02/13 19:25, Stephen Warren wrote:
On 02/01/2013 10:27 AM, Stephen Warren wrote:
On 02/01/2013 09:51 AM, Rob Herring wrote:
On 02/01/2013 03:01 AM, Srinivas KANDAGATLA wrote:
Hi Stephen,
Not sure if you have already noticed this but,
I did try this patch on my 3.8, and it looks like
$(DTC_FLAGS) $(dtc-tmp)
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Thanks,
srini
On 02/01/13 18:43, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Create cmd_dtc_cpp to run the C pre-processor on *.dts file before
passing them to dtc for final compilation
On 15/11/12 13:11, Grant Likely wrote:
On Fri, 2 Nov 2012 10:46:19 +, Srinivas KANDAGATLA
srinivas.kandaga...@st.com wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch add new code to correctly add resources into platform device.
Issue with the existing code
Hi Alex,
I am looking forward for this feature to be mainlined, but I have
comment on the way the types are tied up to power seq infrastructure.
I know your use case are limited to using type delay, pwm and gpio
and regulator, However there are instances where the devices can be
powered up or
On 16/11/12 08:31, Alex Courbot wrote:
Hi Srinivas,
On Friday 16 November 2012 15:58:29 Srinivas KANDAGATLA wrote:
Hi Alex,
I am looking forward for this feature to be mainlined,
*cough* Ack *cough* :)
:-)
but I have
comment on the way the types are tied up to power seq infrastructure.
I
From: Stephen Gallimore stephen.gallim...@st.com
Clocks implementing the get_parent() op may return an invalid parent
index if the hardware is in an undefined state when the clock is
created. However the calls of get_parent() in clk.c do not check
that the returned index is in range before using
Hi Greg,
Am not sure if you missed this patch.
Can you please consider this for 3.12.
Thanks,
srini
On 15/07/13 12:39, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically
Hi Arnd,
On 09/07/13 22:15, Arnd Bergmann wrote:
For DT case, At the moment I think callbacks at MACH level is one
possible solution. But am open for any discussions.
Ok, so a PHY driver might not be the best place to put this, but it's
one option, since the PHY driver already has to know
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The use case is simple, if any rc device has allowed protocols =
RC_TYPE_LIRC and map_name = RC_MAP_LIRC set, the driver open will be never
called. The reason for this is, all of the key maps except lirc have some
KEYS in there map, so during
Thanks Sean for the comments,
On 12/07/13 13:46, Sean Young wrote:
On Fri, Jul 12, 2013 at 09:55:28AM +0100, Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The use case is simple, if any rc device has allowed protocols =
RC_TYPE_LIRC and map_name = RC_MAP_LIRC
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
of new SOC addition to
multi_v7_defconfig.
I wanted this to be in a seperate patch, as these options are not
related any of the new SOC support.
Already some discussion at:https://patchwork.kernel.org/patch/2696481
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Linus
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
This patch adds stih415 and stih416 support to multi_v7_defconfig.
CONFIG_ARM_ERRATA_754322 is removed as it is selected by the sti
mach level kconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs/multi_v7_defconfig |4 +++-
1 files changed, 3
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Thankyou all for reviewing the v2 patches.
Here is patch-set incorporating all the review comments from v2.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board
a/arch/arm/boot/dts/stih415-b2020.dts
b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000..442b019
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (RD) Limited.
+ * Author: Srinivas Kandagatla srinivas.kandaga
rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
---
.../devicetree/bindings/tty/serial/st-asc.txt | 18
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 38 +++
arch/arm/include/debug/sti.S | 61
the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore
On 20/06/13 19:55, Arnd Bergmann wrote:
On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -11,6 +11,7 @@
#include linux/clocksource.h
#include linux/irq.h
#include asm/hardware/cache-l2x0.h
+#include asm
On 20/06/13 20:02, Arnd Bergmann wrote:
On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
+static u64 gt_counter_read(void)
+{
+ u64 counter;
+ u32 lower;
+ u32 upper, old_upper;
+
+ upper = __raw_readl(gt_base + GT_COUNTER1);
+ do
On 20/06/13 20:01, Arnd Bergmann wrote:
On Thursday 20 June 2013, Srinivas KANDAGATLA wrote:
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Thankyou all for reviewing the v3 patches.
This patch-set adds basic support for STMicroelectronics STi SOCs
which includes STiH415 and STiH416 with B2000 and B2020 board support.
STiH415 and STiH416 are dual-core ARM Cortex-A9 CPU
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch is generated after re-running savedefconfig on top of
multi_v7_defconfig which gets rid of some of the options, as they are
now slected by mach level or other Kconfigs.
The reason to generate this patch is because, it becomes
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with
standard set-top box IPs.
This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds stih415 and stih416 support to multi_v7_defconfig.
CONFIG_ARM_ERRATA_754322 is removed as it is selected by the sti
mach level kconfig.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/configs
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds low level debug uart support to sti based SOCs.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig.debug | 35 +
arch/arm
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Rob Herring robherri...@gmail.com
CC: Linus Walleij linus.wall...@linaro.org
CC: Will Deacon will.dea
=67252287871113deba96adf7e4df1752f3f08688
Thanks,
srini
On 20/06/13 15:05, Srinivas KANDAGATLA wrote:
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through
industry standard baud rates.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men...@st.com
CC: Arnd Bergmann a...@arndb.de
CC: Greg Kroah-Hartman gre...@linuxfoundation.org
From my point of view the series
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
From: Srinivas Kandagatla srinivas.kandaga...@st.com
Thankyou for providing comments on RFC patch.
This patchset adds new members to rc_device structure to open rc device from
code other than rc-main. In the current code rc-device is only opened via input
driver. In cases where rc device
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds user count to rc_dev structure, the reason to add this
new member is to allow other code like lirc to open rc device directly.
In the existing code, rc device is only opened by input subsystem which
works ok if we have any input
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The use case is simple, if any rc device has allowed protocols =
RC_TYPE_LIRC and map_name = RC_MAP_LIRC set, the driver open will be never
called. The reason for this is, all of the key maps except lirc have some
KEYS in there map, so during
On 19/07/13 12:01, Sean Young wrote:
+int rval = 0;
-return rdev-open(rdev);
+if (!rdev-users++)
+rval = rdev-open(rdev);
+
+if (rval)
+rdev-users--;
+
+return rval;
This looks racey. Some locking is needed, I think rc_dev-lock should
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ASC (asynchronous serial controller)
driver, which is basically a standard serial driver. This IP is common
across all the ST parts for settop box platforms.
ASC is embedded in ST COMMS IP block. It supports Rx Tx
))
+ return PTR_ERR(bank-base);
bank-gpio_chip = st_gpio_template;
bank-gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
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*st_pmx_get_fname(struct pinctrl_dev *pctldev,
unsigned selector)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
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On 01/10/13 15:49, Mauro Carvalho Chehab wrote:
Btw, we're even thinking on mapping HDMI-CEC remote controller RX/TX via
the RC subsystem. So, another L1 protocol would be hdmi-cec.
Ok.
Yet, it seems unlikely that the very same remote controller IP would use
a different
Hi Michael.
On 18/09/13 04:23, Michael Opdenacker wrote:
This patch proposes to remove the 'SOC_STIH415' and 'SOC_STIH416'
parameters, which are used nowhere else in the source code
and Makefiles.
Will they be needed in code that hasn't been submitted yet?
Yes, we will be using it in future
On 18/09/13 13:46, Maxime COQUELIN wrote:
On 09/18/2013 02:03 PM, Lee Jones wrote:
This patch supplies I2C configuration to STiH416 SoC.
Cc: Srinivas Kandagatla srinivas.kandaga...@st.com
Signed-off-by: Maxime Coquelin maxime.coque...@st.com
---
arch/arm/boot/dts/stih416-pinctrl.dtsi
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to ST RC driver, which is basically a IR/UHF
receiver and transmitter. This IP (IRB) is common across all the ST
parts for settop box platforms. IRB is embedded in ST COMMS IP block.
It supports both Rx Tx functionality
On 19/09/13 08:16, Maxime COQUELIN wrote:
Hi Srini,
On 09/18/2013 03:17 PM, Srinivas KANDAGATLA wrote:
On 18/09/13 13:46, Maxime COQUELIN wrote:
On 09/18/2013 02:03 PM, Lee Jones wrote:
This patch supplies I2C configuration to STiH416 SoC.
Cc: Srinivas Kandagatla srinivas.kandaga
On 17/10/13 08:27, Maxime COQUELIN wrote:
...
+
+static struct of_device_id st_i2c_match[] = {
+ { .compatible = st,comms-ssc-i2c, },
the rules is to put the first soc that use the ip in the compatible
as st,sti7100-scc-i2c
Ok. There are no plans to upstream the SH4 platforms, it
On 17/10/13 15:19, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 10:33 Thu 17 Oct , srinivas kandagatla wrote:
On 17/10/13 08:27, Maxime COQUELIN wrote:
...
+
+static struct of_device_id st_i2c_match[] = {
+ { .compatible = st,comms-ssc-i2c, },
the rules is to put the first soc
On 17/10/13 15:49, Lucas Stach wrote:
Am Donnerstag, den 17.10.2013, 15:30 +0100 schrieb srinivas kandagatla:
[...]
Sorry to ask this but, Where is this requirement coming from?
I have not spotted any thing as such in ePAPR specs.
All the spec says is.
===
The compatible property value
Thanks Mark,
The blocking issue for st-rc driver is now closed.
On 18/10/13 12:37, Mark Rutland wrote:
Mauro C. had an option that this is not a real use-case and let's not
overdesign the API, thinking on a possible scenario that may never happen.
Do you still think that this use case
: Srinivas Kandagatla srinivas.kandaga...@st.com
Hi Peppe,
During PM_SUSPEND_FREEZE testing, I have noticed that PM support in
STMMAC is
partly broken. I had to re-arrange the code to do PM correctly. There
were lot
of things I did not like personally and some bits did not work in the
first
Hi Maxime,
Thankyou for the comments.
On 29/11/13 19:37, Maxime Ripard wrote:
+
+ethernet0: ethernet0{
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = st,stih415-dwmac;
+ reg = 0x148 0x4;
+ resets = softreset
Hi Lee,
On 29/11/13 12:19, Lee Jones wrote:
+ /* FSM */
+ spifsm: spifsm@fe902000{
+ compatible = st,spi-fsm, simple-bus;
simple-bus is redundant here.
+ reg= 0xfe902000 0x1000;
+
it, can I add your Ack for the remainder of the patch?
Yes,
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
You should be aware that arch/arm/boot/dts/stih416-b2105.dts is not in
mainline yet.
Thanks,
srini
+ reg= 0xfe902000 0x1000
On 29/11/13 12:18, Lee Jones wrote:
This is a new driver. It's used to communicate with a special type of
optimised Serial Flash Controller called the FSM. The FSM uses a subset
of the SPI protocol to communicate with supported NOR-Flash devices.
You might want to expand what is FSM
On 02/12/13 13:43, Lee Jones wrote:
On Mon, 02 Dec 2013, srinivas kandagatla wrote:
On 02/12/13 13:20, Lee Jones wrote:
+ /* FSM */
+ spifsm: spifsm@fe902000{
+ compatible = st,spi-fsm, simple-bus;
simple-bus is redundant here.
Yes I agree, good
On 12/11/13 14:20, Rafael J. Wysocki wrote:
+/* callback for device_child_may_wakeup */
+static int __device_child_may_wakeup(struct device *dev, void *c)
+{
+ return device_may_wakeup(dev);
+}
This doesn't have anything to do with children in principle, so please call
it
This patch fixes a typo for device_type property of phy node.
This can work as of today but once a checks are added in generic code
this typo will stop phy from working.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
.../dts/orion5x-lacie-ethernet-disk-mini-v2.dts|2
This patch fixes a typo for device_type property of phy node.
This can work as of today but once a checks are added in generic code
this typo will stop phy from working.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/boot/dts/dove.dtsi |2 +-
1 files changed, 1
According to Documentation/devicetree/bindings/net/phy.txt device_type
property of PHY nodes is mandatory, which should be set to
ethernet-phy. This patch adds check in scanning phys and only scans
node which have device-type set to ethernet-phy.
Signed-off-by: Srinivas Kandagatla
On 14/11/13 15:36, Andrew Lunn wrote:
Please CC: the Marvell maintainers for patches like this.
I added them in CC:
Acked-by: Andrew Lunn and...@lunn.ch
Thanks for the ack and adding Marvell maintainers in CC.
--srini
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.
Cc: Stuart Menefy stuart.men...@st.com
Cc: Srinivas Kandagatla srinivas.kandaga...@st.com
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
drivers/clocksource/arm_global_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource
2 files changed, 88 insertions(+)
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Thanks,
srini
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On 19/11/13 05:24, Giuseppe CAVALLARO wrote:
So you continue to have my Acked-by for all.
Thanks for the Ack Peppe.
peppe
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On 14/03/14 09:44, Maxime Coquelin wrote:
drivers/pinctrl/pinctrl-st.c- unsigned int*input_delays;
drivers/pinctrl/pinctrl-st.c- unsigned int*output_delays;
It may be better to change these to const unsigned int *
and change
static unsigned int stih416_delays[] = {
to static
Thanks Philipp for your comments,
On 24/02/14 10:33, Philipp Zabel wrote:
Did Srini's explanations convinced you?
If so, could you queue the series for v3.15?
to be honest, I'm not comfortable with this explanation. If the
powerdown bits only gate the clocks to those modules, calling it
On 24/02/14 15:16, Philipp Zabel wrote:
Hi Srinivas,
Am Montag, den 24.02.2014, 14:03 + schrieb srinivas kandagatla:
Thanks Philipp for your comments,
On 24/02/14 10:33, Philipp Zabel wrote:
Did Srini's explanations convinced you?
If so, could you queue the series for v3.15
Thankyou Philipp,
On 25/02/14 09:47, Philipp Zabel wrote:
No, the context is lost, the IP needs re-initialization.
alright then, I'll add them to the queue.
Thats Great..
Can I ask your Ack on these patches so that I can request Arnd/Olof to
take these patches via arm-soc tree.
Hi Arnd/Olof,
I
-by: Maxime Coquelin maxime.coque...@st.com
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
---
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
--srini
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Hi Peppe/Maxime,
I missed a comment... :-)
On 07/03/14 09:41, Maxime COQUELIN wrote:
From: Giuseppe Cavallaro peppe.cavall...@st.com
This patch adds a new logic inside the st pinctrl to manage
an unsupported scenario: some sysconfig are not available!
This is the case of STiH407 where,
should this not be done in this patch itself.
{ /* sentinel */ }
};
Other than that the patch looks Ok to me.
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
Thanks,
srini
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On 07/03/14 11:28, Maxime Coquelin wrote:
Problem is that oe and pu takes -1 in that patch, and these values
will be passed directly to devm_regmap_field_alloc without any check.
I propose to apply this patch before pinctrl: st: add pinctrl support
for the STiH407 SoC, and move
-by: Srinivas Kandagatla srinivas.kandaga...@st.com
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...@st.com
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
Acked-by: Srinivas Kandagatla srinivas.kandaga...@st.com
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Hi Dave/Peppe,
Do you have any plans to take this series?
Peppe already Acked these series.
Please let me know if you want me to rebase these patches to a
particular branch.
Thanks,
srini
On 18/11/13 11:30, srinivas.kandaga...@st.com wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
From: Stephen Gallimore stephen.gallim...@st.com
This patch selects reset controller support for ARCH_STI and
selects the reset controllers for STiH415 and STiH416 SoCs.
Signed-off-by: Stephen Gallimore stephen.gallim...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
From: Stephen Gallimore stephen.gallim...@st.com
This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System
configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/boot/dts/stih416.dtsi |5
drivers/reset/sti/reset-stih416.c
configuration registers based reset controller
that controls the softreset state of the hardware such as Ethernet, IRB.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
.../devicetree/bindings/reset/st,sti-softreset.txt | 45
arch/arm/boot/dts/stih415.dtsi
.
Comments?
Thanks,
srini
Srinivas Kandagatla (2):
drivers: reset: stih415: add softreset controller
drivers: reset: stih416: add softreset controller
Stephen Gallimore (4):
drivers: reset: STi SoC system configuration reset controller support
drivers: reset: Reset controller driver for STiH415
Gallimore stephen.gallim...@st.com
+ * Author: Srinivas Kandagatla srinivas.kandaga...@st.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (RD) Limited
+ * Author: Stephen Gallimore stephen.gallim...@st.com
+ * Author: Srinivas Kandagatla srinivas.kandaga...@st.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms
Thankyou Dave,
I will fix these in next version.
On 10/02/14 22:40, David Miller wrote:
From: srinivas.kandaga...@st.com
Date: Fri, 7 Feb 2014 10:55:25 +
+if (dwmac-interface == PHY_INTERFACE_MODE_MII ||
+dwmac-interface == PHY_INTERFACE_MODE_GMII) {
From: Srinivas Kandagatla srinivas.kandaga...@st.com
If we dump syscon regmap registers via debufs you will notice that the
dump contains lot of values at the end.
An example configuration is:
syscon@fdde{
compatible = syscon;
reg = 0xfdde 0x15c
From: Srinivas Kandagatla srinivas.kandaga...@st.com
If we dump syscon regmap registers via debugfs you will notice that the
dump contains lot of values.
An example configuration is:
syscon@fdde{
compatible = syscon;
reg = 0xfdde 0x15c
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH416 is advanced HD AVC processor with 3D graphics acceleration
and 1.2-GHz ARM Cortex-A9 SMP CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen Gallimore stephen.gallim...@st.com
CC: Stuart Menefy stuart.men
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x
UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with
standard set-top box IPs.
This patch adds initial support to B2020 with STiH415/416 with SBC_UART1
as console
Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: Stuart Menefy stuart.men...@st.com
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
Documentation/devicetree/bindings/arm/gt.txt | 21 ++
arch/arm/Kconfig |6 +
arch/arm/include/asm
From: Srinivas Kandagatla srinivas.kandaga...@st.com
B2000 board is reference board for STIH415/416 SOCs, it has
2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM.
This patch add initial support to b2000 with STiH415/416 with UART2 as
console and a heard beat LED.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch introduces syscon_claim, syscon_read, syscon_write,
syscon_release APIs to help drivers to use syscon registers in much more
flexible way.
With this patch, a driver can claim few/all bits in the syscon registers
and do read/write
From: Srinivas Kandagatla srinivas.kandaga...@st.com
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
CC: Stephen
Thankyou for the comments.
On 08/05/13 16:06, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:11 Wed 08 May , Srinivas KANDAGATLA wrote:
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks
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