On Tue, Sep 18, 2012 at 11:23 PM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120917 23:07]:
On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com
On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com [120913 01:57]:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real
* Shilimkar, Santosh santosh.shilim...@ti.com [120917 23:07]:
On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com [120913 01:57]:
Enable Cortex A15 generic timer support for
* Benoit Cousson b-cous...@ti.com [120913 01:57]:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
Acked-by: Benoit Cousson b-cous...@ti.com
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com [120913 01:57]:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
[...]
Silly question: Don't we have one arch-timer per
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at
On Thu, Sep 13, 2012 at 3:30 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
[...]
Silly question: Don't we have one arch-timer per CPU?
It is per CPU just like A9 TWD
Shouldn't we have two nodes
Benoit,
On Mon, Aug 13, 2012 at 4:37 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |
On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by:
On 09/10/2012 03:01 PM, Shilimkar, Santosh wrote:
On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/10/2012 03:01 PM, Shilimkar, Santosh wrote:
On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson b-cous...@ti.com
wrote:
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |6 ++
arch/arm/mach-omap2/Kconfig |1 +
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