Re: [PATCH] ARM: OMAP2+: omap-usb-host: Fix memory leaks
Hi Tony,
On 05/31/2013 12:00 AM, Tony Lindgren wrote:
Hi Roger,
* Roger Quadros rog...@ti.com [130524 06:12]:
Fix memory leaks in the error path.
Also, use platform_device_register_full() to allocate
the platform devices and set platform data.
If you need this for the v3.10-rc, you should describe why this patch
is needed and ideally have some oops or regression causing commit
listed. Care to update the description for that?
There is no oops or regression happening. Just that there will be a
small memory leak if any of the memory allocations fail or if the
platform device is destroyed.
If it doesn't look that serious to you then it can wait.
But if we move to device tree only boot then this patch and the file
usb-host.c might not be required at all.
cheers,
-roger
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/usb-host.c | 106
+---
1 files changed, 56 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f..609b330 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,6 +28,7 @@
#include linux/io.h
#include linux/gpio.h
#include linux/usb/phy.h
+#include linux/usb/nop-usb-xceiv.h
#include soc.h
#include omap_device.h
@@ -560,7 +561,8 @@ static int usbhs_add_regulator(char *name, char *dev_id,
char *dev_supply,
struct regulator_init_data *reg_data;
struct fixed_voltage_config *config;
struct platform_device *pdev;
-int ret;
+struct platform_device_info pdevinfo;
+int ret = -ENOMEM;
supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
if (!supplies)
@@ -571,7 +573,7 @@ static int usbhs_add_regulator(char *name, char *dev_id,
char *dev_supply,
reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
if (!reg_data)
-return -ENOMEM;
+goto err_data;
reg_data-constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
reg_data-consumer_supplies = supplies;
@@ -580,39 +582,53 @@ static int usbhs_add_regulator(char *name, char
*dev_id, char *dev_supply,
config = kmemdup(hsusb_reg_config, sizeof(hsusb_reg_config),
GFP_KERNEL);
if (!config)
-return -ENOMEM;
+goto err_config;
+
+config-supply_name = kstrdup(name, GFP_KERNEL);
+if (!config-supply_name)
+goto err_supplyname;
-config-supply_name = name;
config-gpio = gpio;
config-enable_high = polarity;
config-init_data = reg_data;
/* create a regulator device */
-pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-if (!pdev)
-return -ENOMEM;
+memset(pdevinfo, 0, sizeof(pdevinfo));
+pdevinfo.name = reg_name;
+pdevinfo.id = PLATFORM_DEVID_AUTO;
+pdevinfo.data = config;
+pdevinfo.size_data = sizeof(*config);
-pdev-id = PLATFORM_DEVID_AUTO;
-pdev-name = reg_name;
-pdev-dev.platform_data = config;
+pdev = platform_device_register_full(pdevinfo);
+if (IS_ERR(pdev)) {
+ret = PTR_ERR(pdev);
+pr_err(%s: Failed registering regulator %s for %s : %d\n,
+__func__, name, dev_id, ret);
+goto err_register;
+}
-ret = platform_device_register(pdev);
-if (ret)
-pr_err(%s: Failed registering regulator %s for %s\n,
-__func__, name, dev_id);
+return 0;
+err_register:
+kfree(config-supply_name);
+err_supplyname:
+kfree(config);
+err_config:
+kfree(reg_data);
+err_data:
+kfree(supplies);
return ret;
}
+#define MAX_STR 20
+
int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
{
-char *rail_name;
-int i, len;
+char rail_name[MAX_STR];
+int i;
struct platform_device *pdev;
char *phy_id;
-
-/* the phy_id will be something like nop_usb_xceiv.1 */
-len = strlen(nop_name) + 3; /* 3 - .1 and NULL terminator */
+struct platform_device_info pdevinfo;
for (i = 0; i num_phys; i++) {
@@ -627,25 +643,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int
num_phys)
!gpio_is_valid(phy-vcc_gpio))
continue;
-/* create a NOP PHY device */
-pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-if (!pdev)
-return -ENOMEM;
-
-pdev-id = phy-port;
-pdev-name = nop_name;
-pdev-dev.platform_data = phy-platform_data;
-
-phy_id = kmalloc(len, GFP_KERNEL);
-if (!phy_id)
+phy_id = kmalloc(MAX_STR, GFP_KERNEL);
+if (!phy_id) {
+pr_err(%s: kmalloc() failed\n, __func__);
return -ENOMEM;
+}
-scnprintf(phy_id, len, nop_usb_xceiv.%d\n,
-
[PATCH 0/3] ARM: OMAP: add corrected DSS regulator supplies
Hi Tony, Here are a few patches adding corrected DSS regulator supplies. The current ones in the board files are not really correct, although the dss driver works ok with them. So these patches add new regulator supply entries. When these are merged, I'll change omapdss driver to use the new ones, instead of the old ones. After that, we can remove the old ones from the board files. Note that these patches were also present in the big DSS series I sent yesterday. There's no reason for these patches to be there, so I'm sending them separately, and will drop these from my DSS series. Tomi Tomi Valkeinen (3): ARM: OMAP: fix dsi regulator names ARM: OMAP: add vdds_dsi supply for omapdss_dpi.0 ARM: OMAP: add vdds_sdi supply for omapdss_sdi.0 arch/arm/mach-omap2/board-cm-t35.c | 3 ++- arch/arm/mach-omap2/board-devkit8000.c | 1 + arch/arm/mach-omap2/board-ldp.c | 3 ++- arch/arm/mach-omap2/board-omap3pandora.c | 1 + arch/arm/mach-omap2/board-rx51-peripherals.c | 1 + arch/arm/mach-omap2/twl-common.c | 1 + 6 files changed, 8 insertions(+), 2 deletions(-) -- 1.8.1.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: OMAP: fix dsi regulator names
board-cm-t35.c and board-ldp.c contain regulator supply entries for
vdds_dsi. However, the given device name is wrong.
This patch fixes the device name from omapdss_dsi1 to omapdss_dsi.0.
Note that as far as I know, DSI driver is not used on these boards, so
this should not have caused any problems. The DSI block can be used to
generate clock for DPI, though, but that's not enabled for omap3 boards
currently.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/board-cm-t35.c | 2 +-
arch/arm/mach-omap2/board-ldp.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c
b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c..ce00968 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,7 +293,7 @@ static struct regulator_consumer_supply
cm_t35_vsim_supply[] = {
static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
REGULATOR_SUPPLY(vcc, spi1.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss),
- REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi1),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc..3dbc881 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,7 +272,7 @@ static struct regulator_init_data ldp_vaux1 = {
static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
REGULATOR_SUPPLY(vdds_dsi, omapdss),
- REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi1),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
static struct regulator_init_data ldp_vpll2 = {
--
1.8.1.2
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[PATCH 2/3] ARM: OMAP: add vdds_dsi supply for omapdss_dpi.0
DPI driver gets currently the vdds_dsi regulator via omapdss device.
This is not correct, and we'll change the DPI driver to get the
regulator directly via omapdss_dpi.0 device.
This patch changes the relevant board files to add vdds_dsi supply for
omapdss_dpi.0 device.
Note that the vdds_dsi supply for omapdss device is still left there, as
the current display driver uses it. When both the board files and the
display driver has been changed, we can remove the unused supply.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/board-cm-t35.c | 1 +
arch/arm/mach-omap2/board-devkit8000.c | 1 +
arch/arm/mach-omap2/board-ldp.c | 1 +
arch/arm/mach-omap2/board-omap3pandora.c | 1 +
arch/arm/mach-omap2/twl-common.c | 1 +
5 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c
b/arch/arm/mach-omap2/board-cm-t35.c
index ce00968..d4622ed 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,6 +293,7 @@ static struct regulator_consumer_supply
cm_t35_vsim_supply[] = {
static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
REGULATOR_SUPPLY(vcc, spi1.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dpi.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
diff --git a/arch/arm/mach-omap2/board-devkit8000.c
b/arch/arm/mach-omap2/board-devkit8000.c
index 5764205..f1d91ba 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data
devkit8000_gpio_data = {
static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
REGULATOR_SUPPLY(vdds_dsi, omapdss),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dpi.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 3dbc881..62e4f70 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,6 +272,7 @@ static struct regulator_init_data ldp_vaux1 = {
static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
REGULATOR_SUPPLY(vdds_dsi, omapdss),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dpi.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c
b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5..b1547a0 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -343,6 +343,7 @@ static struct regulator_consumer_supply
pandora_vmmc3_supply[] = {
static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY(vdds_sdi, omapdss),
REGULATOR_SUPPLY(vdds_dsi, omapdss),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dpi.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 51e138c..c05898f 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = {
static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
REGULATOR_SUPPLY(vdds_dsi, omapdss),
+ REGULATOR_SUPPLY(vdds_dsi, omapdss_dpi.0),
REGULATOR_SUPPLY(vdds_dsi, omapdss_dsi.0),
};
--
1.8.1.2
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[PATCH 3/3] ARM: OMAP: add vdds_sdi supply for omapdss_sdi.0
SDI driver gets currently the vdds_sdi regulator via omapdss device.
This is not correct, and we'll change the SDI driver to get the
regulator directly via omapdss_sdi.0 device.
This patch changes the rx51 board file to add vdds_dsi supply for
omapdss_sdi.0 device.
Note that the vdds_sdi supply for omapdss device is still left there, as
the current display driver uses it. When both the board files and the
display driver has been changed, we can remove the unused supply.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c
b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 18ca61e..9c2dd10 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[]
= {
static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
REGULATOR_SUPPLY(vdds_sdi, omapdss),
+ REGULATOR_SUPPLY(vdds_sdi, omapdss_sdi.0),
/* Si4713 supply */
REGULATOR_SUPPLY(vdd, 2-0063),
/* lis3lv02d */
--
1.8.1.2
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[PATCH v5, 3/3] ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm
From: Philip Avinash avinashphi...@ti.com
GPMC controller on AM335x-EVM has a NAND flash connected to it.
This patch updates following in am335x-evm.dts:
- adds nandflash specific pin-mux configs
- adds nand node as child of GPMC contoller, with information about
NAND flash interface, NAND partition table, ECC scheme, elm handle id.
- updates GPMC node for newer GPMC DT properties added in linux-3.10.
Signed-off-by: Philip Avinash avinashphi...@ti.com
Signed-off-by: Gupta, Pekon pe...@ti.com
---
arch/arm/boot/dts/am335x-evm.dts | 105 +++
1 file changed, 105 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298..7d2be9c 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -44,6 +44,26 @@
0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
;
};
+
+ nandflash_pins_s0: nandflash_pins_s0 {
+ pinctrl-single,pins =
+ 0x0 0x30/* gpmc_ad0.gpmc_ad0, INPUT |
PULLUP | MODE0 */
+ 0x4 0x30/* gpmc_ad1.gpmc_ad1, INPUT |
PULLUP | MODE0 */
+ 0x8 0x30/* gpmc_ad2.gpmc_ad2, INPUT |
PULLUP | MODE0 */
+ 0xc 0x30/* gpmc_ad3.gpmc_ad3, INPUT |
PULLUP | MODE0 */
+ 0x10 0x30 /* gpmc_ad4.gpmc_ad4, INPUT |
PULLUP | MODE0 */
+ 0x14 0x30 /* gpmc_ad5.gpmc_ad5, INPUT |
PULLUP | MODE0 */
+ 0x18 0x30 /* gpmc_ad6.gpmc_ad6, INPUT |
PULLUP | MODE0 */
+ 0x1c 0x30 /* gpmc_ad7.gpmc_ad7, INPUT |
PULLUP | MODE0 */
+ 0x70 0x30 /* gpmc_wait0.gpmc_wait0, INPUT
| PULLUP | MODE0 */
+ 0x74 0x37 /* gpmc_wpn.gpio0_30, INPUT |
PULLUP | MODE7 */
+ 0x7c 0x8/* gpmc_csn0.gpmc_csn0, PULL
DISA */
+ 0x90 0x8/* gpmc_advn_ale.gpmc_advn_ale,
PULL DISA */
+ 0x94 0x8/* gpmc_oen_ren.gpmc_oen_ren,
PULL DISA */
+ 0x98 0x8/* gpmc_wen.gpmc_wen, PULL DISA
*/
+ 0x9c 0x8/* gpmc_be0n_cle.gpmc_be0n_cle,
PULL DISA */
+ ;
+ };
};
ocp {
@@ -102,6 +122,91 @@
reg = 0x48;
};
};
+
+ elm: elm@4808 {
+ status = okay;
+ };
+
+ gpmc: gpmc@5000 {
+ status = okay;
+ pinctrl-names = default;
+ pinctrl-0 = nandflash_pins_s0;
+ ranges = 0 0 0x0800 0x1000; /* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0; /* CS0, offset 0 */
+ nand-bus-width = 8;
+ ti,nand-ecc-opt = bch8;
+ gpmc,device-nand = true;
+ gpmc,device-width = 1;
+ gpmc,sync-clk-ps = 0;
+ gpmc,cs-on-ns = 0;
+ gpmc,cs-rd-off-ns = 44;
+ gpmc,cs-wr-off-ns = 44;
+ gpmc,adv-on-ns = 6;
+ gpmc,adv-rd-off-ns = 34;
+ gpmc,adv-wr-off-ns = 44;
+ gpmc,we-on-ns = 0;
+ gpmc,we-off-ns = 40;
+ gpmc,oe-on-ns = 0;
+ gpmc,oe-off-ns = 54;
+ gpmc,access-ns = 64;
+ gpmc,rd-cycle-ns = 82;
+ gpmc,wr-cycle-ns = 82;
+ gpmc,wait-on-read = true;
+ gpmc,wait-on-write = true;
+ gpmc,bus-turnaround-ns = 0;
+ gpmc,cycle2cycle-delay-ns = 0;
+ gpmc,clk-activation-ns = 0;
+ gpmc,wait-monitoring-ns = 0;
+ gpmc,wr-access-ns = 40;
+ gpmc,wr-data-mux-bus-ns = 0;
+
+ #address-cells = 1;
+ #size-cells = 1;
+ elm_id = elm;
+
+ /* MTD partition table */
+ partition@0 {
+ label = SPL1;
+ reg = 0x 0x2;
+ };
+
+
[PATCH v5, 2/3] dts: am33xx: Correct properties on gpmc node
From: Lars Poeschel poesc...@lemonage.de The gpmc driver is actually looking for gpmc,num-cs and gpmc,num-waitpins properties in DT. The binding doc also states this. Correct the properties in the dts to provide the right values for the gpmc driver. Signed-off-by: Lars Poeschel poesc...@lemonage.de Acked-by: Peter Korsgaard jac...@sunsite.dk Acked-by: Pekon Gupta pe...@ti.com --- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0425af8..5f80f84 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -417,8 +417,8 @@ ti,hwmods = gpmc; reg = 0x5000 0x2000; interrupts = 100; - num-cs = 7; - num-waitpins = 2; + gpmc,num-cs = 7; + gpmc,num-waitpins = 2; #address-cells = 2; #size-cells = 1; status = disabled; -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v5, 1/3] ARM: dts: AM33XX: Add ELM node
From: Philip, Avinash avinashphi...@ti.com
ELM hardware engine is used for locating bit-flips in NAND data
This patch is required for working of hardware based NAND ECC schemes
with DT support.
Signed-off-by: Philip Avinash avinashphi...@ti.com
Acked-by: Peter Korsgaard jac...@sunsite.dk
Signed-off-by: Pekon Gupta pe...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b..0425af8 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -404,6 +404,14 @@
ti,hwmods = wkup_m3;
};
+ elm: elm@4808 {
+ compatible = ti,am3352-elm;
+ reg = 0x4808 0x2000;
+ interrupts = 4;
+ ti,hwmods = elm;
+ status = disabled;
+ };
+
gpmc: gpmc@5000 {
compatible = ti,am3352-gpmc;
ti,hwmods = gpmc;
--
1.8.1
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[PATCH v5, 0/3] DT support for NAND on OMAP2
From: Gupta, Pekon pe...@ti.com Changes v4-v5 - updated commit descriptions. - included patch by Lars Poeschel instead of [Patch 2/3] Changes v3-v4 - rebased to linux-3.10-rc3 - updated newly supported DT properties based on following commits [d36b4cd] jon-hun...@ti.com ARM: OMAP2+: Add additional GPMC timing ... [8c8a777] jon-hun...@ti.com ARM: OMAP2+: Add function to read GPMC ... [9f83315] jon-hun...@ti.com ARM: OMAP2+: Add variable to store number Changes v2-v3 - rebased to linux-3.9-rc8 - AM335x-evm.dts: moved GPMC pin-mux config to nand node Changes v1-v2 - Change number of chip select to 7 - Replace xx literals to 52 - remove tab Lars Poeschel (1): dts: am33xx: Correct properties on gpmc node Philip Avinash (1): ARM: dts: AM33XX: Add NAND flash device tree data to am335x-evm Philip, Avinash (1): ARM: dts: AM33XX: Add ELM node arch/arm/boot/dts/am335x-evm.dts | 105 +++ arch/arm/boot/dts/am33xx.dtsi| 12 - 2 files changed, 115 insertions(+), 2 deletions(-) -- 1.8.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH v2 1/3] mmc: omap_hsmmc: Enable SDIO IRQ using a GPIO in idle mode.
Hi,
this email adress will soon expire,
my alternate email adress is
afenkart at gmail.com
On Mon, May 20, 2013 at 01:58:16PM -0700, Tony Lindgren wrote:
* Andreas Fenkart andreas.fenk...@streamunlimited.com [130515 01:51]:
Without functional clock the omap_hsmmc module can't forward SDIO IRQs to
the system. This patch reconfigures dat1 line as a gpio while the fclk is
off. When the fclk is present it uses the standard SDIO IRQ detection of
the module.
The gpio irq is managed via the 'disable_depth' ref counter of the irq
subsystem, this driver simply calls enable_irq/disable_irq when needed.
sdio irqsdio irq
unmasked masked
-
runtime default |1 | 2
runtime suspend |0 | 1
irq disable depth
only when sdio irq is enabled AND the module is idle, the reference
count drops to zero and the gpio irq is effectively armed.
Patch was tested on AM335x/Stream800. Test setup was two modules
with sdio wifi cards. Modules where connected to a dual-band AP, each
module using a different band. One of module was running iperf as server
the other as client connecting to the server in a while true loop. Test
was running for 4+ weeks. There were about 60 Mio. suspend/resume
transitions. Test was shut down regularly.
Looks like this somehow breaks detecting of eMMC on mmc2 for me at least
with the non-dt legacyboot. For a removable mmc1 still keeps working.
For mmc2 I have .nonremovable = true and no gpio_cd or gpio_wp.
Also few comments below.
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
+ host-pinctrl = devm_pinctrl_get(pdev-dev);
+ if (IS_ERR(host-pinctrl)) {
+ ret = PTR_ERR(host-pinctrl);
+ goto err_pinctrl;
+ }
+
+ host-active = pinctrl_lookup_state(host-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(host-active)) {
+ dev_warn(mmc_dev(host-mmc), Unable to lookup active
pinmux\n);
+ ret = PTR_ERR(host-active);
+ goto err_pinctrl_state;
+ }
This should be checked, we have systems with all muxing done statically
in the bootloader. And we also have systems that provide the default
pinctrl state only as they don't need remuxing. So at most a warning should
be printed.
static int omap_hsmmc_runtime_resume(struct device *dev)
{
struct omap_hsmmc_host *host;
+ unsigned long flags;
+ int ret = 0;
host = platform_get_drvdata(to_platform_device(dev));
omap_hsmmc_context_restore(host);
dev_dbg(dev, enabled\n);
- return 0;
+ if (mmc_slot(host).sdio_irq host-pinctrl) {
+ disable_irq(mmc_slot(host).sdio_irq);
+
+ ret = pinctrl_select_state(host-pinctrl, host-active);
+ if (ret 0) {
+ dev_warn(mmc_dev(host-mmc), Unable to select active
pinmux\n);
+ return ret;
+ }
+
+ spin_lock_irqsave(host-irq_lock, flags);
+ host-active_pinmux = true;
+
+ if (host-sdio_irq_en) {
+ OMAP_HSMMC_WRITE(host-base, STAT, STAT_CLEAR);
+ OMAP_HSMMC_WRITE(host-base, ISE, CIRQ_EN);
+ OMAP_HSMMC_WRITE(host-base, IE, CIRQ_EN);
+ }
+ spin_unlock_irqrestore(host-irq_lock, flags);
+ }
+ return ret;
}
The check for sdio_irq host-pinctrl looks broken too as we may
have not dynamic muxing via pinctrl needed for let's say omap3 based
systems.
Other than that, looks good to me.
Regards,
Tony
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Re: [PATCH v3 1/3] gpio/omap: replace open coded read-modify-write with _gpio_rmw function.
FYI,
this email adress will soon expire,
this is my alternate adress: afenkart at gmail.com
On Tue, May 14, 2013 at 10:54:25PM +0200, Andreas Fenkart wrote:
By also making it return the modified value, we save the readl
needed to update the context.
Signed-off-by: Andreas Fenkart andreas.fenk...@streamunlimited.com
---
drivers/gpio/gpio-omap.c | 162
++
1 file changed, 50 insertions(+), 112 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 159f5c5..082919e 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -87,6 +87,19 @@ struct gpio_bank {
#define GPIO_BIT(bank, gpio) (1 GPIO_INDEX(bank, gpio))
#define GPIO_MOD_CTRL_BITBIT(0)
+static inline u32 _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
+{
+ u32 l = __raw_readl(base + reg);
+
+ if (set)
+ l |= mask;
+ else
+ l = ~mask;
+
+ __raw_writel(l, base + reg);
+ return l;
+}
+
static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
{
return gpio_irq - bank-irq_base + bank-chip.base;
@@ -94,20 +107,10 @@ static int irq_to_gpio(struct gpio_bank *bank, unsigned
int gpio_irq)
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int
is_input)
{
- void __iomem *reg = bank-base;
- u32 l;
-
- reg += bank-regs-direction;
- l = __raw_readl(reg);
- if (is_input)
- l |= 1 gpio;
- else
- l = ~(1 gpio);
- __raw_writel(l, reg);
- bank-context.oe = l;
+ bank-context.oe = _gpio_rmw(bank-base, bank-regs-direction, 1
+ gpio, is_input);
}
-
/* set data out value using dedicate set/clear register */
static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int
enable)
{
@@ -128,17 +131,8 @@ static void _set_gpio_dataout_reg(struct gpio_bank
*bank, int gpio, int enable)
/* set data out value using mask register */
static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int
enable)
{
- void __iomem *reg = bank-base + bank-regs-dataout;
- u32 gpio_bit = GPIO_BIT(bank, gpio);
- u32 l;
-
- l = __raw_readl(reg);
- if (enable)
- l |= gpio_bit;
- else
- l = ~gpio_bit;
- __raw_writel(l, reg);
- bank-context.dataout = l;
+ bank-context.dataout = _gpio_rmw(bank-base, bank-regs-dataout,
+ GPIO_BIT(bank, gpio), enable);
}
static int _get_gpio_datain(struct gpio_bank *bank, int offset)
@@ -155,18 +149,6 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int
offset)
return (__raw_readl(reg) (1 offset)) != 0;
}
-static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
-{
- int l = __raw_readl(base + reg);
-
- if (set)
- l |= mask;
- else
- l = ~mask;
-
- __raw_writel(l, base + reg);
-}
-
static inline void _gpio_dbck_enable(struct gpio_bank *bank)
{
if (bank-dbck_enable_mask !bank-dbck_enabled) {
@@ -291,28 +273,24 @@ static inline void set_gpio_trigger(struct gpio_bank
*bank, int gpio,
void __iomem *base = bank-base;
u32 gpio_bit = 1 gpio;
- _gpio_rmw(base, bank-regs-leveldetect0, gpio_bit,
- trigger IRQ_TYPE_LEVEL_LOW);
- _gpio_rmw(base, bank-regs-leveldetect1, gpio_bit,
- trigger IRQ_TYPE_LEVEL_HIGH);
- _gpio_rmw(base, bank-regs-risingdetect, gpio_bit,
- trigger IRQ_TYPE_EDGE_RISING);
- _gpio_rmw(base, bank-regs-fallingdetect, gpio_bit,
- trigger IRQ_TYPE_EDGE_FALLING);
bank-context.leveldetect0 =
- __raw_readl(bank-base + bank-regs-leveldetect0);
+ _gpio_rmw(base, bank-regs-leveldetect0,
+ gpio_bit, trigger IRQ_TYPE_LEVEL_LOW);
bank-context.leveldetect1 =
- __raw_readl(bank-base + bank-regs-leveldetect1);
+ _gpio_rmw(base, bank-regs-leveldetect1,
+ gpio_bit, trigger IRQ_TYPE_LEVEL_HIGH);
bank-context.risingdetect =
- __raw_readl(bank-base + bank-regs-risingdetect);
+ _gpio_rmw(base, bank-regs-risingdetect,
+ gpio_bit, trigger IRQ_TYPE_EDGE_RISING);
bank-context.fallingdetect =
- __raw_readl(bank-base + bank-regs-fallingdetect);
+ _gpio_rmw(base, bank-regs-fallingdetect,
+ gpio_bit, trigger IRQ_TYPE_EDGE_FALLING);
if (likely(!(bank-non_wakeup_gpios gpio_bit))) {
- _gpio_rmw(base, bank-regs-wkup_en, gpio_bit, trigger != 0);
bank-context.wake_en =
- __raw_readl(bank-base + bank-regs-wkup_en);
+ _gpio_rmw(base, bank-regs-wkup_en,
Re: [PATCH] usb: dwc3: Addition of dr_mode dt property.
Hi,
On Thu, May 30, 2013 at 03:14:54PM -0500, Ruchika Kharwar wrote:
This patch adds an optional parameter dr_mode to the dwc3 core device node.
In the case the compile flag for the DWC3 controller is set to
USB_DWC3_DUAL_ROLE a device tree could restrain to either functionality of
host or gadget. In the case the device tree does not use this optional flag or
specifies it superfluously to drd the functionality will be that
of a dual role device.
Signed-off-by: Ruchika Kharwar ruch...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |3 ++-
drivers/usb/dwc3/core.c| 21 +
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7a95c65..2f5d584 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -10,7 +10,8 @@ Required properties:
Optional properties:
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
-
+ - dr_mode: determines the mode of core. Supported modes are gadget, host
+ and drd.
This is usually a subnode to DWC3 glue to which it is connected.
dwc3@4a03 {
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index c35d49d..e11660a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -378,7 +378,7 @@ static int dwc3_probe(struct platform_device *pdev)
void*mem;
u8 mode;
-
+ char*dr_mode;
mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
if (!mem) {
dev_err(dev, not enough memory\n);
@@ -520,9 +520,22 @@ static int dwc3_probe(struct platform_device *pdev)
mode = DWC3_MODE_HOST;
else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
mode = DWC3_MODE_DEVICE;
- else
- mode = DWC3_MODE_DRD;
-
+ else {
+ if (of_property_read_string(node, dr_mode, dr_mode))
+ mode = DWC3_MODE_DRD;
+ else {
+ if (strcmp(dr_mode, host) == 0)
+ mode = DWC3_MODE_HOST;
+ else if (strcmp(dr_mode, gadget) == 0)
+ mode = DWC3_MODE_DEVICE;
+ else if (strcmp(dr_mode, drd) == 0)
+ mode = DWC3_MODE_DRD;
+ else {
+ dev_err(dev, invalid dr_mode property
value\n);
+ goto err2;
+ }
+ }
+ }
switch (mode) {
case DWC3_MODE_DEVICE:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
--
Why not help to make use of that code?
https://patchwork.kernel.org/patch/2193321/
We currently stuck in the discussion about all possible dr_mode
properties. There came up a device that is host and device capable,
but not otg.
What does the property drd stand for?
Thanks,
Michael
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Re: [PATCH v2 1/1] i2c: omap: correct usage of the interrupt enable register
On 05/30/2013 07:46 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
addresses, the interrupt enabling procedure is unchanged.
Signed-off-by: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
Much better, but still doesn't explain how/why this has been working up
until now. Have we just been lucky?
Yes, this has been working up until now because we've just been lucky.
---
drivers/i2c/busses/i2c-omap.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..2419899 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
#define I2C_OMAP_ERRATA_I207 (1 0)
#define I2C_OMAP_ERRATA_I462 (1 1)
+#define OMAP_I2C_INTERRUPTS_MASK 0x6FFF
To be more clear, this should probably have v2 in the name.
I'll rename this mask in the patch-set v3
Kevin
--
Best regards,
Oleksandr Dmytryshyn | OMAP4 Platform
GlobalLogic Inc. | Innovation by Design
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[PATCH v3 1/1] i2c: omap: correct usage of the interrupt enable register
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
addresses, the interrupt enabling procedure is unchanged.
Change-Id: Ie49165990a4e7c67a4ccf2e4a66cd3b78f2e2b70
Signed-off-by: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..64c26f9 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
#define I2C_OMAP_ERRATA_I207 (1 0)
#define I2C_OMAP_ERRATA_I462 (1 1)
+#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
+
struct omap_i2c_dev {
spinlock_t lock; /* IRQ synchronization */
struct device *dev;
@@ -193,6 +195,7 @@ struct omap_i2c_dev {
long latency);
u32 speed; /* Speed of bus in kHz */
u32 flags;
+ u16 scheme;
u16 cmd_err;
u8 *buf;
u8 *regs;
@@ -1082,7 +1085,7 @@ omap_i2c_probe(struct platform_device *pdev)
int irq;
int r;
u32 rev;
- u16 minor, major, scheme;
+ u16 minor, major;
/* NOTE: driver uses the static register mapping */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1159,8 +1162,8 @@ omap_i2c_probe(struct platform_device *pdev)
*/
rev = __raw_readw(dev-base + 0x04);
- scheme = OMAP_I2C_SCHEME(rev);
- switch (scheme) {
+ dev-scheme = OMAP_I2C_SCHEME(rev);
+ switch (dev-scheme) {
case OMAP_I2C_SCHEME_0:
dev-regs = (u8 *)reg_map_ip_v1;
dev-rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
@@ -1289,7 +1292,11 @@ static int omap_i2c_runtime_suspend(struct device *dev)
_dev-iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
- omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ if (_dev-scheme == OMAP_I2C_SCHEME_0)
+ omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ else
+ omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
+ OMAP_I2C_IP_V2_INTERRUPTS_MASK);
if (_dev-rev OMAP_I2C_OMAP1_REV_2) {
omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
--
1.8.2.rc2
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[PATCH v3 0/1] i2c: omap: correct usage of the interrupt enable register
I've just renamed OMAP_I2C_INTERRUPTS_MASK to the OMAP_I2C_IP_V2_INTERRUPTS_MASK. If the i2c controller during suspend will generate an interrupt, it can lead to unpredictable behaviour in the kernel. Based on the logic of the kernel code interrupts from i2c should be prohibited during suspend. Kernel writes 0 to the I2C_IE register in the omap_i2c_runtime_suspend() function. In the other side kernel writes saved interrupt flags to the I2C_IE register in omap_i2c_runtime_resume() function. I.e. interrupts should be disabled during suspend. This works for chips with version1 registers scheme. Interrupts are disabled during suspend. For chips with version2 scheme registers writting 0 to the I2C_IE register does nothing (because now the I2C_IRQENABLE_SET register is located at this address). This register is used to enable interrupts. For disabling interrupts I2C_IRQENABLE_CLR register should be used. Because the registers I2C_IRQENABLE_SET and I2C_IE have the same addresses, the interrupt enabling procedure is unchanged. I've checked that interrupts in the i2c controller are still enabled after writting 0 to the I2C_IE register. But with my patch interrupts are disabled in the omap_i2c_runtime_suspend() function. This has been working up until now because we've just been lucky. Next patch fixes it. Patch is based on: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag: v3.10-rc2 Verified on OMAP4430. Oleksandr Dmytryshyn (1): i2c: omap: correct usage of the interrupt enable register drivers/i2c/busses/i2c-omap.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) -- 1.8.2.rc2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/11] i2c: omap: enhance pinctrl support
Amend the I2C omap pin controller to optionally take a pin control
handle and set the state of the pins to:
- default on boot, resume and before performing an i2c transfer
- idle after initial default, after resume default, and after each
i2c xfer
- sleep on suspend()
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.
Note:
A .suspend .resume callback is added which simply puts the pins to sleep
state upon suspend are moved to default idle state upon resume.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
(Changes based on i2c-nomadik.c)
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Wolfram Sang w...@the-dreams.de
Cc: linux-omap@vger.kernel.org
Cc: linux-...@vger.kernel.org
---
:100644 100644 e02f9e3... 588ba28... M drivers/i2c/busses/i2c-omap.c
drivers/i2c/busses/i2c-omap.c | 112 ++---
1 file changed, 105 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..588ba28 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -214,7 +214,11 @@ struct omap_i2c_dev {
u16 westate;
u16 errata;
- struct pinctrl *pins;
+ /* Three pin states - default, idle sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_idle;
+ struct pinctrl_state*pins_sleep;
};
static const u8 reg_map_ip_v1[] = {
@@ -641,6 +645,11 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (IS_ERR_VALUE(r))
goto out;
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(dev-pins_default))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_default))
+ dev_err(dev-dev, could not set default pins\n);
+
r = omap_i2c_wait_for_bb(dev);
if (r 0)
goto out;
@@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
out:
pm_runtime_mark_last_busy(dev-dev);
+
pm_runtime_put_autosuspend(dev-dev);
+ /* Optionally let pins go into idle state */
+ if (!IS_ERR(dev-pins_idle))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_idle))
+ dev_err(dev-dev, could not set pins to idle state\n);
+
return r;
}
@@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
dev-set_mpu_wkup_lat = pdata-set_mpu_wkup_lat;
}
- dev-pins = devm_pinctrl_get_select_default(pdev-dev);
- if (IS_ERR(dev-pins)) {
- if (PTR_ERR(dev-pins) == -EPROBE_DEFER)
+ dev-pinctrl = devm_pinctrl_get(pdev-dev);
+ if (!IS_ERR(dev-pinctrl)) {
+ dev-pins_default = pinctrl_lookup_state(dev-pinctrl,
+PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(dev-pins_default))
+ dev_dbg(pdev-dev, could not get default pinstate\n);
+ else
+ if (pinctrl_select_state(dev-pinctrl,
+dev-pins_default))
+ dev_err(pdev-dev,
+ could not set default pinstate\n);
+
+ dev-pins_idle = pinctrl_lookup_state(dev-pinctrl,
+ PINCTRL_STATE_IDLE);
+ if (IS_ERR(dev-pins_idle))
+ dev_dbg(pdev-dev, could not get idle pinstate\n);
+ else
+ /* If possible, let's idle until the first transfer */
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_idle))
+ dev_err(pdev-dev,
+ could not set idle pinstate\n);
+
+ dev-pins_sleep = pinctrl_lookup_state(dev-pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(dev-pins_sleep))
+ dev_dbg(pdev-dev, could not get sleep pinstate\n);
+ } else {
+ if (PTR_ERR(dev-pinctrl) == -EPROBE_DEFER)
return -EPROBE_DEFER;
- dev_warn(pdev-dev, did not get pins for i2c error: %li\n,
-PTR_ERR(dev-pins));
-
[PATCH 09/11] mmc: omap_hsmmc: enhance pinctrl support
Amend the hsmmc controller to optionally take a pin control handle and
set the state of the pins to:
- default on boot, resume and before performing a mmc transfer
- idle after initial default, after resume default, and after each
mmc/sd card access
- sleep on suspend()
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Cc: Balaji T K balaj...@ti.com
Cc: Chris Ball c...@laptop.org
Cc: linux-...@vger.kernel.org
Cc: linux-omap@vger.kernel.org
---
:100644 100644 6e44025... a2d69aa... M drivers/mmc/host/omap_hsmmc.c
drivers/mmc/host/omap_hsmmc.c | 79 ++---
1 file changed, 74 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6e44025..a2d69aa 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -183,6 +183,12 @@ struct omap_hsmmc_host {
struct omap_hsmmc_next next_data;
struct omap_mmc_platform_data *pdata;
+
+ /* Three pin states - default, idle sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_idle;
+ struct pinctrl_state*pins_sleep;
};
static int omap_hsmmc_card_detect(struct device *dev, int slot)
@@ -1775,7 +1781,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
const struct of_device_id *match;
dma_cap_mask_t mask;
unsigned tx_req, rx_req;
- struct pinctrl *pinctrl;
match = of_match_device(of_match_ptr(omap_mmc_of_match), pdev-dev);
if (match) {
@@ -1982,10 +1987,46 @@ static int omap_hsmmc_probe(struct platform_device
*pdev)
omap_hsmmc_disable_irq(host);
- pinctrl = devm_pinctrl_get_select_default(pdev-dev);
- if (IS_ERR(pinctrl))
- dev_warn(pdev-dev,
- pins are not configured from the driver\n);
+ host-pinctrl = devm_pinctrl_get(pdev-dev);
+ if (!IS_ERR(host-pinctrl)) {
+ host-pins_default = pinctrl_lookup_state(host-pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(host-pins_default))
+ dev_dbg(pdev-dev, could not get default pinstate\n);
+ else
+ if (pinctrl_select_state(host-pinctrl,
+host-pins_default))
+ dev_err(pdev-dev,
+ could not set default pinstate\n);
+
+ host-pins_idle = pinctrl_lookup_state(host-pinctrl,
+ PINCTRL_STATE_IDLE);
+ if (IS_ERR(host-pins_idle))
+ dev_dbg(pdev-dev, could not get idle pinstate\n);
+ else
+ /* If possible, let's idle until the first transfer */
+ if (pinctrl_select_state(host-pinctrl,
+host-pins_idle))
+ dev_err(pdev-dev,
+ could not set idle pinstate\n);
+
+ host-pins_sleep = pinctrl_lookup_state(host-pinctrl,
+ PINCTRL_STATE_SLEEP);
+ if (IS_ERR(host-pins_sleep))
+ dev_dbg(pdev-dev, could not get sleep pinstate\n);
+ } else {
+ /*
+ * Since we continue even when pinctrl node is not found,
+ * Invalidate pins as not available. This is to make sure that
+ * IS_ERR(pins_xxx) results in failure when used.
+ */
+ host-pins_default = ERR_PTR(-ENODATA);
+ host-pins_idle = ERR_PTR(-ENODATA);
+ host-pins_sleep = ERR_PTR(-ENODATA);
+
+ dev_dbg(pdev-dev, did not get pins for mmc error: %li\n,
+ PTR_ERR(host-pinctrl));
+ }
omap_hsmmc_protect_card(host);
@@ -2135,6 +2176,12 @@ static int omap_hsmmc_suspend(struct device *dev)
clk_disable_unprepare(host-dbclk);
err:
pm_runtime_put_sync(host-dev);
+
+ /* Optionally let pins go into sleep states */
+ if (!IS_ERR(host-pins_sleep))
+ if (pinctrl_select_state(host-pinctrl, host-pins_sleep))
+ dev_err(dev,
[PATCH v2 2/2] USB: ehci-omap: select NOP_USB_XCEIV PHY driver
ehci-omap needs NOP_USB_XCEIV PHY driver to function properly, so select it. As the USB PHY drivers no longer depend on USB_PHY, it is safe to select the PHY drivers. Signed-off-by: Roger Quadros rog...@ti.com Tested-by: Adrien Vergé adrienve...@gmail.com --- drivers/usb/host/Kconfig |4 +--- 1 files changed, 1 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 7ded784..48e1b70 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -150,13 +150,11 @@ config USB_EHCI_MXC config USB_EHCI_HCD_OMAP tristate EHCI support for OMAP3 and later chips depends on ARCH_OMAP + select NOP_USB_XCEIV default y ---help--- Enables support for the on-chip EHCI controller on OMAP3 and later chips. - If your system uses a PHY on the USB port, you will need to - enable USB_PHY and the appropriate PHY driver as well. Most - boards need the NOP_USB_XCEIV PHY driver. config USB_EHCI_HCD_ORION tristate Support for Marvell EBU on-chip EHCI USB controller -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/2] USB: PHY: Improve PHY selection logic
Hi, Improve Kconfig so that the relevant PHY driver can be explicitely selected by the controller driver instead of relying on the user to do so. Detailed description in patch 1. v2: - Merge patches 3-5 into the first patch to prevent circular dependency between the Kconfig options during bisection. cheers, -roger Roger Quadros (2): USB: PHY: Make PHY driver selection possible by controller drivers USB: ehci-omap: select NOP_USB_XCEIV PHY driver drivers/usb/Makefile |3 +-- drivers/usb/gadget/Kconfig |2 -- drivers/usb/host/Kconfig |5 + drivers/usb/phy/Kconfig| 31 +-- 4 files changed, 23 insertions(+), 18 deletions(-) -- 1.7.4.1 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/2] USB: PHY: Make PHY driver selection possible by controller drivers
Convert PHY Drivers from menuconfig to menu so that the PHY drivers can be explicitely selected by the controller drivers. USB_PHY is no longer a user visible option. It is upto to the PHY drivers to select it if needed. This patch does so for the existing PHY drivers that use the USB_PHY library. Doing so moves the USB_PHY and PHY driver selection problem from the end user to the PHY and controller driver developer. e.g. Earlier, a controller driver (e.g. EHCI_OMAP) that needs to select a PHY driver (e.g. NOP_PHY) couldn't do so because the PHY driver depended on USB_PHY. Making the controller driver depend on USB_PHY has a negative effect i.e. it becomes invisible to the user till USB_PHY is enabled. Most end users will not familiar with this. With this patch, the end user just needs to select the controller driver needed for his/her platform without worrying about which PHY driver to select. Also update USB_EHCI_MSM, USB_LPC32XX and USB_OMAP to not depend on USB_PHY any more. They can safely select the necessary PHY drivers. CC: Pavankumar Kondeti pkond...@codeaurora.org CC: Roland Stigge sti...@antcom.de Signed-off-by: Roger Quadros rog...@ti.com [USB_LPC32XX part] Acked-by: Roland Stigge sti...@antcom.de --- drivers/usb/Makefile |3 +-- drivers/usb/gadget/Kconfig |2 -- drivers/usb/host/Kconfig |1 - drivers/usb/phy/Kconfig| 31 +-- 4 files changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index c41feba..411c34c 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -43,8 +43,7 @@ obj-$(CONFIG_USB_MICROTEK)+= image/ obj-$(CONFIG_USB_SERIAL) += serial/ -obj-$(CONFIG_USB) += misc/ -obj-$(CONFIG_USB_PHY) += phy/ +obj-$(CONFIG_USB) += misc/ phy/ obj-$(CONFIG_EARLY_PRINTK_DBGP)+= early/ obj-$(CONFIG_USB_ATM) += atm/ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index f41aa0d..86d5d80 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -144,7 +144,6 @@ config USB_AT91 config USB_LPC32XX tristate LPC32XX USB Peripheral Controller depends on ARCH_LPC32XX - depends on USB_PHY select USB_ISP1301 help This option selects the USB device controller in the LPC32xx SoC. @@ -195,7 +194,6 @@ config USB_FUSB300 config USB_OMAP tristate OMAP USB Device Controller depends on ARCH_OMAP1 - depends on USB_PHY select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_H4_OTG help Many Texas Instruments OMAP processors have flexible full diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 344d5e2..7ded784 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -188,7 +188,6 @@ config USB_EHCI_HCD_AT91 config USB_EHCI_MSM tristate Support for Qualcomm QSD/MSM on-chip EHCI USB controller depends on ARCH_MSM - depends on USB_PHY select USB_EHCI_ROOT_HUB_TT select USB_MSM_OTG ---help--- diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 7ef3eb8..b57f7f0 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -1,16 +1,11 @@ # # Physical Layer USB driver configuration # -menuconfig USB_PHY - bool USB Physical Layer drivers - help - USB controllers (those which are host, device or DRD) need a - device to handle the physical layer signalling, commonly called - a PHY. - - The following drivers add support for such PHY devices. +menu USB Physical Layer drivers -if USB_PHY +config USB_PHY + bool + default n # # USB Transceiver Drivers @@ -18,6 +13,7 @@ if USB_PHY config AB8500_USB tristate AB8500 USB Transceiver Driver depends on AB8500_CORE + select USB_PHY help Enable this to support the USB OTG transceiver in AB8500 chip. This transceiver supports high and full speed devices plus, @@ -27,12 +23,14 @@ config FSL_USB2_OTG bool Freescale USB OTG Transceiver Driver depends on USB_EHCI_FSL USB_FSL_USB2 PM_RUNTIME select USB_OTG + select USB_PHY help Enable this to support Freescale USB OTG transceiver. config ISP1301_OMAP tristate Philips ISP1301 with OMAP OTG depends on I2C ARCH_OMAP_OTG + select USB_PHY help If you say yes here you get support for the Philips ISP1301 USB-On-The-Go transceiver working with the OMAP OTG controller. @@ -46,12 +44,14 @@ config ISP1301_OMAP config MV_U3D_PHY bool Marvell USB 3.0 PHY controller Driver depends on CPU_MMP3 + select USB_PHY help Enable this to support Marvell USB 3.0 phy controller for Marvell SoC. config NOP_USB_XCEIV tristate NOP USB Transceiver Driver +
[PATCH 2/2] ARM: OMAP2+: gpmc: removed 'gpmc,device-nand'. type determined from node-name
From: Gupta, Pekon pe...@ti.com
GPMC supports multiple types of child devices like NAND, NOR, OneNand, Ethernet
This patch removes 'gpmc,device-nand', used explicitely to specify NAND type
gpmc-child. Instead gpmc-child type can be inferred from gpmc-child-name.
Signed-off-by: Gupta, Pekon pe...@ti.com
---
Documentation/devicetree/bindings/bus/ti-gpmc.txt | 1 -
arch/arm/boot/dts/am335x-evm.dts | 1 -
arch/arm/mach-omap2/gpmc-nand.c | 3 +--
arch/arm/mach-omap2/gpmc-onenand.c| 2 ++
arch/arm/mach-omap2/gpmc.c| 1 -
5 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 4b87ea1..704be93 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -95,7 +95,6 @@ GPMC chip-select settings properties for child nodes. All are
optional.
- gpmc,burst-wrap Enables wrap bursting
- gpmc,burst-read Enables read page/burst mode
- gpmc,burst-write Enables write page/burst mode
-- gpmc,device-nand Device is NAND
- gpmc,device-widthTotal width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 7d2be9c..c71bb77 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -136,7 +136,6 @@
reg = 0 0 0; /* CS0, offset 0 */
nand-bus-width = 8;
ti,nand-ecc-opt = bch8;
- gpmc,device-nand = true;
gpmc,device-width = 1;
gpmc,sync-clk-ps = 0;
gpmc,cs-on-ns = 0;
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c2719..dc50391 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -140,14 +140,13 @@ int gpmc_nand_init(struct omap_nand_platform_data
*gpmc_nand_data,
if (gpmc_nand_data-of_node) {
gpmc_read_settings_dt(gpmc_nand_data-of_node, s);
} else {
- s.device_nand = true;
-
/* Enable RD PIN Monitoring Reg */
if (gpmc_nand_data-dev_ready) {
s.wait_on_read = true;
s.wait_on_write = true;
}
}
+ s.device_nand = true;
if (gpmc_nand_data-devsize == NAND_BUSWIDTH_16)
s.device_width = GPMC_DEVWIDTH_16BIT;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c
b/arch/arm/mach-omap2/gpmc-onenand.c
index 64b5a83..cea4b6d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -275,6 +275,7 @@ static int omap2_onenand_setup_async(void __iomem
*onenand_base)
if (gpmc_onenand_data-of_node)
gpmc_read_settings_dt(gpmc_onenand_data-of_node,
onenand_async);
+ onenand_async.device_nand = false;
omap2_onenand_set_async_mode(onenand_base);
@@ -315,6 +316,7 @@ static int omap2_onenand_setup_sync(void __iomem
*onenand_base, int *freq_ptr)
if (!cpu_is_omap34xx())
onenand_sync.wait_on_read = true;
}
+ onenand_sync.device_nand = false;
omap2_onenand_calc_sync_timings(t, gpmc_onenand_data-flags, freq);
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 490bca8..fb6f241 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1249,7 +1249,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct
gpmc_settings *p)
p-sync_read = of_property_read_bool(np, gpmc,sync-read);
p-sync_write = of_property_read_bool(np, gpmc,sync-write);
- p-device_nand = of_property_read_bool(np, gpmc,device-nand);
of_property_read_u32(np, gpmc,device-width, p-device_width);
of_property_read_u32(np, gpmc,mux-add-data, p-mux_add_data);
--
1.8.1
--
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[PATCH 1/2] ARM: OMAP2+: gpmc: get number of useable GPMC chip-selects via DT
From: Gupta, Pekon pe...@ti.com
This patch enables usage of DT property 'gpmc,num-cs' as already documented in
Documentation/devicetree/bindings/bus/ti-gpmc.txt
Though GPMC hardware supports upto 8 chip-selects, but all chip-selects may
not be available for use because:
- chip-select pin may not be bonded out at SoC device boundary.
- chip-select pin-mux may conflict with other pins usage.
- board level constrains.
gpmc,num-cs allows user to configure maximum number of GPMC chip-selects
available for use on any given platform. This ensures:
- GPMC child nodes having chip-selects within allowed range are only probed.
- And un-used GPMC chip-selects remain blocked.(may be for security reasons).
Signed-off-by: Gupta, Pekon pe...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da12..490bca8 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -155,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
static DEFINE_SPINLOCK(gpmc_mem_lock);
/* Define chip-selects as reserved by default until probe completes */
static unsigned int gpmc_cs_map = ((1 GPMC_CS_NUM) - 1);
+static unsigned int gpmc_cs_num = GPMC_CS_NUM;
static unsigned int gpmc_nr_waitpins;
static struct device *gpmc_dev;
static int gpmc_irq;
@@ -521,8 +522,10 @@ static int gpmc_cs_remap(int cs, u32 base)
int ret;
u32 old_base, size;
- if (cs GPMC_CS_NUM)
+ if (cs gpmc_cs_num) {
+ pr_err(%s: requested chip-select is disabled\n, __func__);
return -ENODEV;
+ }
gpmc_cs_get_memconf(cs, old_base, size);
if (base == old_base)
return 0;
@@ -545,9 +548,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned
long *base)
struct resource *res = gpmc_cs_mem[cs];
int r = -1;
- if (cs GPMC_CS_NUM)
+ if (cs gpmc_cs_num) {
+ pr_err(%s: requested chip-select is disabled\n, __func__);
return -ENODEV;
-
+ }
size = gpmc_mem_align(size);
if (size (1 GPMC_SECTION_SHIFT))
return -ENOMEM;
@@ -582,7 +586,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
void gpmc_cs_free(int cs)
{
spin_lock(gpmc_mem_lock);
- if (cs = GPMC_CS_NUM || cs 0 || !gpmc_cs_reserved(cs)) {
+ if (cs = gpmc_cs_num || cs 0 || !gpmc_cs_reserved(cs)) {
printk(KERN_ERR Trying to free non-reserved GPMC CS%d\n, cs);
BUG();
spin_unlock(gpmc_mem_lock);
@@ -777,7 +781,7 @@ static void gpmc_mem_exit(void)
{
int cs;
- for (cs = 0; cs GPMC_CS_NUM; cs++) {
+ for (cs = 0; cs gpmc_cs_num; cs++) {
if (!gpmc_cs_mem_enabled(cs))
continue;
gpmc_cs_delete_mem(cs);
@@ -798,7 +802,7 @@ static void gpmc_mem_init(void)
gpmc_mem_root.end = GPMC_MEM_END;
/* Reserve all regions that has been set up by bootloader */
- for (cs = 0; cs GPMC_CS_NUM; cs++) {
+ for (cs = 0; cs gpmc_cs_num; cs++) {
u32 base, size;
if (!gpmc_cs_mem_enabled(cs))
@@ -1513,6 +1517,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
if (!of_id)
return 0;
+ ret = of_property_read_u32(pdev-dev.of_node, gpmc,num-cs,
+ gpmc_cs_num);
+ if (ret 0) {
+ pr_err(%s: number of chip-selects not defined\n, __func__);
+ return ret;
+ } else if (gpmc_cs_num 1) {
+ pr_err(%s: all chip-selects are disabled\n, __func__);
+ return -EINVAL;
+ } else if (gpmc_cs_num GPMC_CS_NUM) {
+ pr_err(%s: number of supported chip-selects cannot be %d\n,
+__func__, GPMC_CS_NUM);
+ return -EINVAL;
+ }
+
ret = of_property_read_u32(pdev-dev.of_node, gpmc,num-waitpins,
gpmc_nr_waitpins);
if (ret 0) {
@@ -1610,8 +1628,10 @@ static int gpmc_probe(struct platform_device *pdev)
/* Now the GPMC is initialised, unreserve the chip-selects */
gpmc_cs_map = 0;
- if (!pdev-dev.of_node)
+ if (!pdev-dev.of_node) {
+ gpmc_cs_num = GPMC_CS_NUM;
gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+ }
rc = gpmc_probe_dt(pdev);
if (rc 0) {
@@ -1715,7 +1735,7 @@ void omap3_gpmc_save_context(void)
gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
- for (i = 0; i GPMC_CS_NUM; i++) {
+ for (i = 0; i gpmc_cs_num; i++) {
Re: [PATCH v3 1/1] i2c: omap: correct usage of the interrupt enable register
On 05/31/2013 03:26 AM, Oleksandr Dmytryshyn wrote:
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
addresses, the interrupt enabling procedure is unchanged.
Change-Id: Ie49165990a4e7c67a4ccf2e4a66cd3b78f2e2b70
Remove this.
Signed-off-by: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..64c26f9 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
#define I2C_OMAP_ERRATA_I207 (1 0)
#define I2C_OMAP_ERRATA_I462 (1 1)
+#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
+
struct omap_i2c_dev {
spinlock_t lock; /* IRQ synchronization */
struct device *dev;
@@ -193,6 +195,7 @@ struct omap_i2c_dev {
long latency);
u32 speed; /* Speed of bus in kHz */
u32 flags;
+ u16 scheme;
u16 cmd_err;
u8 *buf;
u8 *regs;
@@ -1082,7 +1085,7 @@ omap_i2c_probe(struct platform_device *pdev)
int irq;
int r;
u32 rev;
- u16 minor, major, scheme;
+ u16 minor, major;
/* NOTE: driver uses the static register mapping */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1159,8 +1162,8 @@ omap_i2c_probe(struct platform_device *pdev)
*/
rev = __raw_readw(dev-base + 0x04);
- scheme = OMAP_I2C_SCHEME(rev);
- switch (scheme) {
+ dev-scheme = OMAP_I2C_SCHEME(rev);
+ switch (dev-scheme) {
case OMAP_I2C_SCHEME_0:
dev-regs = (u8 *)reg_map_ip_v1;
dev-rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
@@ -1289,7 +1292,11 @@ static int omap_i2c_runtime_suspend(struct device *dev)
_dev-iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
- omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ if (_dev-scheme == OMAP_I2C_SCHEME_0)
+ omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ else
+ omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
+OMAP_I2C_IP_V2_INTERRUPTS_MASK);
if (_dev-rev OMAP_I2C_OMAP1_REV_2) {
omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
--
--
Dan Murphy
--
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[PATCH v4 0/5] ARM: dts: OMAP2+: Use preprocessor for device trees
Hello, Following a similar proposal by Stephen Warren for tegra [1], this series makes use of the C preprocessor when compiling OMAP DT files, and accomplishes some improvements to improve overall readability. Patch 1 is a preparation for the rest of the series. Patch 2 uses existing constants for GPIOs. Patch 3 does the same for IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses it to simplify pinctrl DT. As for previous versions, the .dtb files were diff-tested before and after applying the series to guarantee identity for all targets. The same series for AM3XXX will follow shortly. Best regards, Florian From v3: - Rebased on Benoit's for_3.11/dts branch From v2: - Address Tony's comments (standardize comments, remove OMAP_ prefix) From v1: - Remove duplicated fix - Remove OMAP_GPIO macro - Add pinctrl constants Florian Vaussard (5): ARM: dts: OMAP2+: Use #include for all device trees ARM: dts: OMAP2+: Use existing constants for GPIOs ARM: dts: OMAP4/5: Use existing constants for IRQs ARM: dts: OMAP2+: Header file for pinctrl constants ARM: dts: OMAP2+: Use pinctrl constants arch/arm/boot/dts/omap2.dtsi |5 +- arch/arm/boot/dts/omap2420-h4.dts |2 +- arch/arm/boot/dts/omap2420.dtsi |2 +- arch/arm/boot/dts/omap2430.dtsi |2 +- arch/arm/boot/dts/omap3-beagle-xm.dts |8 +- arch/arm/boot/dts/omap3-beagle.dts| 34 arch/arm/boot/dts/omap3-devkit8000.dts| 10 +- arch/arm/boot/dts/omap3-evm.dts |6 +- arch/arm/boot/dts/omap3-igep.dtsi | 38 arch/arm/boot/dts/omap3-igep0020.dts | 10 +- arch/arm/boot/dts/omap3-igep0030.dts | 10 +- arch/arm/boot/dts/omap3-overo.dtsi|4 +- arch/arm/boot/dts/omap3-tobi.dts |4 +- arch/arm/boot/dts/omap3.dtsi |5 +- arch/arm/boot/dts/omap3430-sdp.dts|4 +- arch/arm/boot/dts/omap34xx.dtsi |2 +- arch/arm/boot/dts/omap36xx.dtsi |2 +- arch/arm/boot/dts/omap4-panda-a4.dts | 10 +- arch/arm/boot/dts/omap4-panda-common.dtsi | 70 arch/arm/boot/dts/omap4-panda-es.dts | 10 +- arch/arm/boot/dts/omap4-panda.dts |4 +- arch/arm/boot/dts/omap4-sdp-es23plus.dts |8 +- arch/arm/boot/dts/omap4-sdp.dts | 126 ++-- arch/arm/boot/dts/omap4-var-som.dts |8 +- arch/arm/boot/dts/omap4.dtsi | 118 ++- arch/arm/boot/dts/omap443x.dtsi |2 +- arch/arm/boot/dts/omap4460.dtsi |6 +- arch/arm/boot/dts/omap5-evm.dts | 92 ++-- arch/arm/boot/dts/omap5.dtsi | 128 +++-- include/dt-bindings/pinctrl/omap.h| 50 +++ 30 files changed, 422 insertions(+), 358 deletions(-) create mode 100644 include/dt-bindings/pinctrl/omap.h -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 3/5] ARM: dts: OMAP4/5: Use existing constants for IRQs
Use the constants defined in include/dt-bindings/interrupt-controller/
to enhance readability.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/omap4-panda-common.dtsi |8 +-
arch/arm/boot/dts/omap4-sdp.dts |6 +-
arch/arm/boot/dts/omap4-var-som.dts |4 +-
arch/arm/boot/dts/omap4.dtsi | 113 +-
arch/arm/boot/dts/omap4460.dtsi |4 +-
arch/arm/boot/dts/omap5.dtsi | 123 +++--
6 files changed, 130 insertions(+), 128 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index f5bec4d..8d09cf5 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -165,16 +165,16 @@
twl: twl@48 {
reg = 0x48;
- /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
- interrupts = 0 7 4; /* IRQ_SYS_1N cascaded to gic */
+ /* IRQ# = 7 */
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to gic */
interrupt-parent = gic;
};
twl6040: twl@4b {
compatible = ti,twl6040;
reg = 0x4b;
- /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
- interrupts = 0 119 4; /* IRQ_SYS_2N cascaded to gic */
+ /* IRQ# = 119 */
+ interrupts = GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_2N
cascaded to gic */
interrupt-parent = gic;
ti,audpwron-gpio = gpio4 31 0; /* gpio line 127 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 7a26194..e9df3ea 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -306,7 +306,7 @@
twl: twl@48 {
reg = 0x48;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
- interrupts = 0 7 4; /* IRQ_SYS_1N cascaded to gic */
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to gic */
interrupt-parent = gic;
};
@@ -314,7 +314,7 @@
compatible = ti,twl6040;
reg = 0x4b;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
- interrupts = 0 119 4; /* IRQ_SYS_2N cascaded to gic */
+ interrupts = GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_2N
cascaded to gic */
interrupt-parent = gic;
ti,audpwron-gpio = gpio4 31 0; /* gpio line 127 */
@@ -395,7 +395,7 @@
spi-max-frequency = 2400;
reg = 0;
interrupt-parent = gpio2;
- interrupts = 2 8; /* gpio line 34, low triggered */
+ interrupts = 2 IRQ_TYPE_LEVEL_LOW; /* gpio line 34 */
vdd-supply = vdd_eth;
};
};
diff --git a/arch/arm/boot/dts/omap4-var-som.dts
b/arch/arm/boot/dts/omap4-var-som.dts
index 6593607..b41269e 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -34,7 +34,7 @@
twl: twl@48 {
reg = 0x48;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
- interrupts = 0 7 4; /* IRQ_SYS_1N cascaded to gic */
+ interrupts = GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_1N
cascaded to gic */
interrupt-parent = gic;
};
};
@@ -68,7 +68,7 @@
spi-max-frequency = 2400;
reg = 0;
interrupt-parent = gpio6;
- interrupts = 11 8; /* gpio line 171, low triggered */
+ interrupts = 11 IRQ_TYPE_LEVEL_LOW; /* gpio line 171 */
vdd-supply = vdd_eth;
};
};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4160d7d..6137aff 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -7,6 +7,7 @@
*/
#include dt-bindings/gpio/gpio.h
+#include dt-bindings/interrupt-controller/arm-gic.h
#include skeleton.dtsi
@@ -50,7 +51,7 @@
local-timer@0x48240600 {
compatible = arm,cortex-a9-twd-timer;
reg = 0x48240600 0x20;
- interrupts = 1 13 0x304;
+ interrupts = GIC_PPI 13 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_HIGH);
};
/*
@@ -91,8 +92,8 @@
reg = 0x4400 0x1000,
0x4480 0x2000,
0x4500 0x1000;
- interrupts = 0 9 0x4,
-0 10 0x4;
+ interrupts = GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH,
+GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH;
counter32k: counter@4a304000 {
[PATCH v4 1/5] ARM: dts: OMAP2+: Use #include for all device trees
Replace /include/ by #include for OMAP2+ DT, in order to use the
C pre-processor, making use of #define features possible.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/omap2.dtsi |2 +-
arch/arm/boot/dts/omap2420-h4.dts |2 +-
arch/arm/boot/dts/omap2420.dtsi |2 +-
arch/arm/boot/dts/omap2430.dtsi |2 +-
arch/arm/boot/dts/omap3-beagle-xm.dts |4 ++--
arch/arm/boot/dts/omap3-beagle.dts|4 ++--
arch/arm/boot/dts/omap3-devkit8000.dts|4 ++--
arch/arm/boot/dts/omap3-evm.dts |4 ++--
arch/arm/boot/dts/omap3-igep.dtsi |4 ++--
arch/arm/boot/dts/omap3-igep0020.dts |2 +-
arch/arm/boot/dts/omap3-igep0030.dts |2 +-
arch/arm/boot/dts/omap3-overo.dtsi|4 ++--
arch/arm/boot/dts/omap3-tobi.dts |2 +-
arch/arm/boot/dts/omap3.dtsi |2 +-
arch/arm/boot/dts/omap3430-sdp.dts|4 ++--
arch/arm/boot/dts/omap34xx.dtsi |2 +-
arch/arm/boot/dts/omap36xx.dtsi |2 +-
arch/arm/boot/dts/omap4-panda-a4.dts |4 ++--
arch/arm/boot/dts/omap4-panda-common.dtsi |4 ++--
arch/arm/boot/dts/omap4-panda-es.dts |4 ++--
arch/arm/boot/dts/omap4-panda.dts |4 ++--
arch/arm/boot/dts/omap4-sdp-es23plus.dts |2 +-
arch/arm/boot/dts/omap4-sdp.dts |6 +++---
arch/arm/boot/dts/omap4-var-som.dts |4 ++--
arch/arm/boot/dts/omap4.dtsi |2 +-
arch/arm/boot/dts/omap443x.dtsi |2 +-
arch/arm/boot/dts/omap4460.dtsi |2 +-
arch/arm/boot/dts/omap5-evm.dts |4 ++--
arch/arm/boot/dts/omap5.dtsi |2 +-
29 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa748..e6e4587 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,7 @@
* kind, whether express or implied.
*/
-/include/ skeleton.dtsi
+#include skeleton.dtsi
/ {
compatible = ti,omap2430, ti,omap2420, ti,omap2;
diff --git a/arch/arm/boot/dts/omap2420-h4.dts
b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee..224c08f 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ omap2420.dtsi
+#include omap2420.dtsi
/ {
model = TI OMAP2420 H4 board;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285..c8f9c55 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
* kind, whether express or implied.
*/
-/include/ omap2.dtsi
+#include omap2.dtsi
/ {
compatible = ti,omap2420, ti,omap2;
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc44..c535a5a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
* kind, whether express or implied.
*/
-/include/ omap2.dtsi
+#include omap2.dtsi
/ {
compatible = ti,omap2430, ti,omap2;
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..e0ce823 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ omap36xx.dtsi
+#include omap36xx.dtsi
/ {
model = TI OMAP3 BeagleBoard xM;
@@ -75,7 +75,7 @@
};
};
-/include/ twl4030.dtsi
+#include twl4030.dtsi
i2c2 {
clock-frequency = 40;
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..fcac96a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ omap34xx.dtsi
+#include omap34xx.dtsi
/ {
model = TI OMAP3 BeagleBoard;
@@ -107,7 +107,7 @@
};
};
-/include/ twl4030.dtsi
+#include twl4030.dtsi
mmc1 {
vmmc-supply = vmmc1;
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts
b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc..8d0f5e4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ omap34xx.dtsi
+#include omap34xx.dtsi
/ {
model = TimLL OMAP3 Devkit8000;
compatible = timll,omap3-devkit8000, ti,omap3;
@@ -80,7 +80,7 @@
status = disabled;
};
-/include/ twl4030.dtsi
+#include twl4030.dtsi
mmc1 {
vmmc-supply = vmmc1;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c20..d75759b 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
*/
/dts-v1/;
-/include/ omap34xx.dtsi
+#include omap34xx.dtsi
/ {
model = TI
[PATCH v4 4/5] ARM: dts: OMAP2+: Header file for pinctrl constants
Most of the constants are taken from arch/arm/mach-omap2/mux.h. Define some others for the PIN_OUTPUT_* flavours. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch Acked-by: Santosh Shilimkar santosh.shilim...@ti.com Reviewed-by: Stephen Warren swar...@nvidia.com --- include/dt-bindings/pinctrl/omap.h | 50 1 files changed, 50 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/omap.h diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h new file mode 100644 index 000..370df3f --- /dev/null +++ b/include/dt-bindings/pinctrl/omap.h @@ -0,0 +1,50 @@ +/* + * This header provides constants for OMAP pinctrl bindings. + * + * Copyright (C) 2009 Nokia + * Copyright (C) 2009-2010 Texas Instruments + */ + +/* 34xx mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 + +/* 24xx/34xx mux bit defines */ +#define PULL_ENA (1 3) +#define PULL_UP(1 4) +#define ALTELECTRICALSEL (1 5) + +/* 34xx specific mux bit defines */ +#define INPUT_EN (1 8) +#define OFF_EN (1 9) +#define OFFOUT_EN (1 10) +#define OFFOUT_VAL (1 11) +#define OFF_PULL_EN(1 12) +#define OFF_PULL_UP(1 13) +#define WAKEUP_EN (1 14) + +/* 44xx specific mux bit defines */ +#define WAKEUP_EVENT (1 15) + +/* Active pin states */ +#define PIN_OUTPUT 0 +#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) +#define PIN_OUTPUT_PULLDOWN(PIN_OUTPUT | PULL_ENA) +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + +/* Off mode states */ +#define PIN_OFF_NONE 0 +#define PIN_OFF_OUTPUT_HIGH(OFF_EN | OFFOUT_EN | OFFOUT_VAL) +#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) +#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) +#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) +#define PIN_OFF_WAKEUPENABLE WAKEUP_EN + -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 5/5] ARM: dts: OMAP2+: Use pinctrl constants
Using constants for pinctrl allows a better readability, and removes
redundancy with comments.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/omap2.dtsi |1 +
arch/arm/boot/dts/omap3-beagle.dts| 24
arch/arm/boot/dts/omap3-igep.dtsi | 34 +-
arch/arm/boot/dts/omap3.dtsi |1 +
arch/arm/boot/dts/omap4-panda-a4.dts |6 +-
arch/arm/boot/dts/omap4-panda-common.dtsi | 54
arch/arm/boot/dts/omap4-panda-es.dts |6 +-
arch/arm/boot/dts/omap4-sdp-es23plus.dts |6 +-
arch/arm/boot/dts/omap4-sdp.dts | 98 ++--
arch/arm/boot/dts/omap4.dtsi |1 +
arch/arm/boot/dts/omap5-evm.dts | 88 +-
arch/arm/boot/dts/omap5.dtsi |1 +
12 files changed, 162 insertions(+), 158 deletions(-)
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f39b237..b3cc896 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -9,6 +9,7 @@
*/
#include dt-bindings/gpio/gpio.h
+#include dt-bindings/pinctrl/omap.h
#include skeleton.dtsi
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 434288f..6d47c4b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -81,18 +81,18 @@
hsusbb2_pins: pinmux_hsusbb2_pins {
pinctrl-single,pins =
- 0x5c0 0x3 /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
- 0x5c2 0x3 /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
- 0x5c4 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
- 0x5c6 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
- 0x5c8 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
- 0x5cA 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
- 0x1a4 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
- 0x1a6 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
- 0x1a8 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
- 0x1aa 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
- 0x1ac 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
- 0x1ae 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+ 0x5c0 (PIN_OUTPUT | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
+ 0x5c2 (PIN_OUTPUT | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
+ 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
+ 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
+ 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
+ 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
+ 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
+ 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
+ 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
+ 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
+ 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
+ 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /*
usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
;
};
};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi
b/arch/arm/boot/dts/omap3-igep.dtsi
index d1d2ba7..5224c29 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -29,43 +29,43 @@
omap3_pmx_core {
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins =
- 0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */
- 0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */
+ 0x152 (PIN_INPUT | MUX_MODE0) /*
uart1_rx.uart1_rx */
+ 0x14c (PIN_OUTPUT |MUX_MODE0) /*
uart1_tx.uart1_tx */
;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins =
- 0x14a 0x100 /*
[PATCH v4 2/5] ARM: dts: OMAP2+: Use existing constants for GPIOs
Use standard GPIO constants to enhance the readability of DT GPIOs.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---
arch/arm/boot/dts/omap2.dtsi |2 ++
arch/arm/boot/dts/omap3-beagle-xm.dts |4 ++--
arch/arm/boot/dts/omap3-beagle.dts|6 +++---
arch/arm/boot/dts/omap3-devkit8000.dts|6 +++---
arch/arm/boot/dts/omap3-evm.dts |2 +-
arch/arm/boot/dts/omap3-igep0020.dts |8
arch/arm/boot/dts/omap3-igep0030.dts |8
arch/arm/boot/dts/omap3-tobi.dts |2 +-
arch/arm/boot/dts/omap3.dtsi |2 ++
arch/arm/boot/dts/omap4-panda-common.dtsi |4 ++--
arch/arm/boot/dts/omap4-sdp.dts | 16
arch/arm/boot/dts/omap4.dtsi |2 ++
arch/arm/boot/dts/omap5.dtsi |2 ++
13 files changed, 36 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index e6e4587..f39b237 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,6 +8,8 @@
* kind, whether express or implied.
*/
+#include dt-bindings/gpio/gpio.h
+
#include skeleton.dtsi
/ {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index e0ce823..1e580d9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -29,13 +29,13 @@
heartbeat {
label = beagleboard::usr0;
- gpios = gpio5 22 0; /* 150 - D6 LED */
+ gpios = gpio5 22 GPIO_ACTIVE_HIGH; /* 150 - D6 LED
*/
linux,default-trigger = heartbeat;
};
mmc {
label = beagleboard::usr1;
- gpios = gpio5 21 0; /* 149 - D7 LED */
+ gpios = gpio5 21 GPIO_ACTIVE_HIGH; /* 149 - D7 LED
*/
linux,default-trigger = mmc0;
};
};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index fcac96a..434288f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -28,18 +28,18 @@
compatible = gpio-leds;
pmu_stat {
label = beagleboard::pmu_stat;
- gpios = twl_gpio 19 0; /* LEDB */
+ gpios = twl_gpio 19 GPIO_ACTIVE_HIGH; /* LEDB */
};
heartbeat {
label = beagleboard::usr0;
- gpios = gpio5 22 0; /* 150 - D6 LED */
+ gpios = gpio5 22 GPIO_ACTIVE_HIGH; /* 150 - D6 LED
*/
linux,default-trigger = heartbeat;
};
mmc {
label = beagleboard::usr1;
- gpios = gpio5 21 0; /* 149 - D7 LED */
+ gpios = gpio5 21 GPIO_ACTIVE_HIGH; /* 149 - D7 LED
*/
linux,default-trigger = mmc0;
};
};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts
b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8d0f5e4..5be71b1 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -22,21 +22,21 @@
heartbeat {
label = devkit8000::led1;
- gpios = gpio6 26 0; /* 186 - LED1 */
+ gpios = gpio6 26 GPIO_ACTIVE_HIGH; /* 186 - LED1
*/
default-state = on;
linux,default-trigger = heartbeat;
};
mmc {
label = devkit8000::led2;
- gpios = gpio6 3 0; /* 163 - LED2 */
+ gpios = gpio6 3 GPIO_ACTIVE_HIGH;/* 163 - LED2
*/
default-state = on;
linux,default-trigger = none;
};
usr {
label = devkit8000::led3;
- gpios = gpio6 4 0; /* 164 - LED3 */
+ gpios = gpio6 4 GPIO_ACTIVE_HIGH;/* 164 - LED3
*/
default-state = on;
linux,default-trigger = usr;
};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index d75759b..baa24bb 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -28,7 +28,7 @@
compatible = gpio-leds;
ledb {
label = omap3evm::ledb;
- gpios = twl_gpio 19 0; /* LEDB */
+ gpios = twl_gpio 19 GPIO_ACTIVE_HIGH; /* LEDB */
linux,default-trigger = default-on;
[PATCH 4/4] ARM: dts: AM33XX: Use pinctrl constants
Using constants for pinctrl allows a better readability, and removes
redundancy with comments.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
---
arch/arm/boot/dts/am335x-bone.dts | 18 +-
arch/arm/boot/dts/am335x-evm.dts | 28 ++--
arch/arm/boot/dts/am335x-evmsk.dts | 26 +-
arch/arm/boot/dts/am33xx.dtsi |1 +
4 files changed, 37 insertions(+), 36 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 5bfb7dd..61d0793 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -30,30 +30,30 @@
user_leds_s0: user_leds_s0 {
pinctrl-single,pins =
- 0x54 0x7/* gpmc_a5.gpio1_21, OUTPUT |
MODE7 */
- 0x58 0x17 /* gpmc_a6.gpio1_22,
OUTPUT_PULLUP | MODE7 */
- 0x5c 0x7/* gpmc_a7.gpio1_23, OUTPUT |
MODE7 */
- 0x60 0x17 /* gpmc_a8.gpio1_24,
OUTPUT_PULLUP | MODE7 */
+ 0x54 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT | PULL_UP | MUX_MODE7) /*
gpmc_a6.gpio1_22 */
+ 0x5c (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a7.gpio1_23 */
+ 0x60 (PIN_OUTPUT | PULL_UP | MUX_MODE7) /*
gpmc_a8.gpio1_24 */
;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins =
- 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
- 0x18c 0x30 /* i2c0_scl.i2c0_scl PULLUP |
INPUTENABLE | MODE0 */
+ 0x188 (PIN_INPUT | PULL_UP | MUX_MODE0) /*
i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT | PULL_UP | MUX_MODE0) /*
i2c0_scl.i2c0_scl */
;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins =
- 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |
INPUTENABLE | MODE0 */
- 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN
| MODE0 */
+ 0x170 (PIN_INPUT | PULL_UP | MUX_MODE0) /*
uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT | MUX_MODE0) /*
uart0_txd.uart0_txd */
;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins =
- 0x1b4 0x03 /* xdma_event_intr1.clkout2
OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ 0x1b4 (PIN_OUTPUT | MUX_MODE3) /*
xdma_event_intr1.clkout2 */
;
};
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0fbecfd..0ee69ec 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -30,45 +30,45 @@
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins =
- 0x54 0x7/* gpmc_a5.gpio1_21, OUTPUT |
MODE7 */
- 0x58 0x7/* gpmc_a6.gpio1_22, OUTPUT |
MODE7 */
- 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT |
MODE7 */
- 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT |
MODE7 */
- 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT |
MODE7 */
+ 0x54 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT | MUX_MODE7) /*
gpmc_a6.gpio1_22 */
+ 0x64 (PIN_INPUT | MUX_MODE7)/*
gpmc_a9.gpio1_25 */
+ 0x68 (PIN_INPUT | MUX_MODE7)/*
gpmc_a10.gpio1_26 */
+ 0x6c (PIN_INPUT | MUX_MODE7)/*
gpmc_a11.gpio1_27 */
;
};
volume_keys_s0: volume_keys_s0 {
pinctrl-single,pins =
- 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT |
MODE7 */
- 0x154 0x27 /* spi0_d0.gpio0_3, INPUT |
MODE7 */
+ 0x150 (PIN_INPUT | MUX_MODE7) /*
spi0_sclk.gpio0_2 */
+ 0x154 (PIN_INPUT | MUX_MODE7) /*
spi0_d0.gpio0_3 */
;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins =
- 0x188 0x30 /* i2c0_sda.i2c0_sda PULLUP |
INPUTENABLE | MODE0 */
- 0x18c 0x30 /*
[PATCH 3/4] ARM: dts: AM33XX: Specific pinctrl header
The pinctrl IP inside the AM33XX family differs slightly from what is found on OMAP2+. Define a specific header to take account of the differences. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch --- include/dt-bindings/pinctrl/am33xx.h | 19 +++ 1 files changed, 19 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/am33xx.h diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h new file mode 100644 index 000..9ffb6c2 --- /dev/null +++ b/include/dt-bindings/pinctrl/am33xx.h @@ -0,0 +1,19 @@ +/* + * This header provides constants specific to AM33XX pinctrl bindings. + */ + +#include include/dt-bindings/pinctrl/omap.h + +/* am33xx specific mux bit defines */ +#undef INPUT_EN +#define INPUT_EN (1 5) +#define SLEWCTRL_FAST (1 6) + +/* update macro depending on INPUT_EN */ +#undef PIN_INPUT +#undef PIN_INPUT_PULLUP +#undef PIN_INPUT_PULLDOWN +#define PIN_INPUT INPUT_EN +#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) + -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4] ARM: dts: AM33XX: Use existing constants for GPIOs
Use standard GPIO constants to enhance the readability of DT GPIOs.
Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch
---
arch/arm/boot/dts/am335x-bone.dts |8
arch/arm/boot/dts/am335x-evm.dts | 14 +++---
arch/arm/boot/dts/am335x-evmsk.dts | 16
arch/arm/boot/dts/am33xx.dtsi |2 ++
4 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-bone.dts
b/arch/arm/boot/dts/am335x-bone.dts
index 0365e56..5bfb7dd 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -88,27 +88,27 @@
led@2 {
label = beaglebone:green:heartbeat;
- gpios = gpio1 21 0;
+ gpios = gpio1 21 GPIO_ACTIVE_HIGH;
linux,default-trigger = heartbeat;
default-state = off;
};
led@3 {
label = beaglebone:green:mmc0;
- gpios = gpio1 22 0;
+ gpios = gpio1 22 GPIO_ACTIVE_HIGH;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = beaglebone:green:usr2;
- gpios = gpio1 23 0;
+ gpios = gpio1 23 GPIO_ACTIVE_HIGH;
default-state = off;
};
led@5 {
label = beaglebone:green:usr3;
- gpios = gpio1 24 0;
+ gpios = gpio1 24 GPIO_ACTIVE_HIGH;
default-state = off;
};
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 629476e..0fbecfd 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -159,12 +159,12 @@
debounce-delay-ms = 5;
col-scan-delay-us = 2;
- row-gpios = gpio1 25 0/* Bank1, pin25 */
-gpio1 26 0/* Bank1, pin26 */
-gpio1 27 0; /* Bank1, pin27 */
+ row-gpios = gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25
*/
+gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26
*/
+gpio1 27 GPIO_ACTIVE_HIGH; /* Bank1, pin27
*/
- col-gpios = gpio1 21 0/* Bank1, pin21 */
-gpio1 22 0; /* Bank1, pin22 */
+ col-gpios = gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21
*/
+gpio1 22 GPIO_ACTIVE_HIGH; /* Bank1, pin22
*/
linux,keymap = 0x008b /* MENU */
0x019e /* BACK */
@@ -183,14 +183,14 @@
switch@9 {
label = volume-up;
linux,code = 115;
- gpios = gpio0 2 1;
+ gpios = gpio0 2 GPIO_ACTIVE_LOW;
gpio-key,wakeup;
};
switch@10 {
label = volume-down;
linux,code = 114;
- gpios = gpio0 3 1;
+ gpios = gpio0 3 GPIO_ACTIVE_LOW;
gpio-key,wakeup;
};
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts
b/arch/arm/boot/dts/am335x-evmsk.dts
index a339a76..289ba2c 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -144,26 +144,26 @@
led@1 {
label = evmsk:green:usr0;
- gpios = gpio1 4 0;
+ gpios = gpio1 4 GPIO_ACTIVE_HIGH;
default-state = off;
};
led@2 {
label = evmsk:green:usr1;
- gpios = gpio1 5 0;
+ gpios = gpio1 5 GPIO_ACTIVE_HIGH;
default-state = off;
};
led@3 {
label = evmsk:green:mmc0;
- gpios = gpio1 6 0;
+ gpios = gpio1 6 GPIO_ACTIVE_HIGH;
linux,default-trigger = mmc0;
default-state = off;
};
led@4 {
label = evmsk:green:heartbeat;
- gpios = gpio1 7 0;
+ gpios = gpio1 7 GPIO_ACTIVE_HIGH;
linux,default-trigger = heartbeat;
default-state = off;
};
@@ -177,26 +177,26 @@
switch@1 {
label = button0;
linux,code = 0x100;
- gpios = gpio2 3 0;
+ gpios = gpio2 3
Re: [PATCH v4 0/5] ARM: dts: OMAP2+: Use preprocessor for device trees
Hi Florian, On 05/31/2013 02:32 PM, Florian Vaussard wrote: Hello, Following a similar proposal by Stephen Warren for tegra [1], this series makes use of the C preprocessor when compiling OMAP DT files, and accomplishes some improvements to improve overall readability. Patch 1 is a preparation for the rest of the series. Patch 2 uses existing constants for GPIOs. Patch 3 does the same for IRQs. Patch 4 creates a new header for OMAP's padmux, and patch 5 uses it to simplify pinctrl DT. As for previous versions, the .dtb files were diff-tested before and after applying the series to guarantee identity for all targets. The same series for AM3XXX will follow shortly. Best regards, Florian Thanks for the series. I've just applied it and will push the update for_3.11/dts branch ASAP. Regards, Benoit -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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[GIT PULL] ARM: OMAP: dts fixes for 3.10-rc4
Hi Tony, Please pull two DTS fixes for the next -rc. Thanks, Benoit The following changes since commit e4aa937ec75df0eea0bee03bffa3303ad36c986b: Linus Torvalds (1): Linux 3.10-rc3 are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git dts-fixes-for-3.10 Kevin Hilman (1): ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line Lars Poeschel (1): ARM: dts: AM33xx: Fix properties on gpmc node arch/arm/boot/dts/am33xx.dtsi |4 ++-- arch/arm/boot/dts/omap4-panda-common.dtsi | 20 arch/arm/boot/dts/omap4-sdp.dts | 20 3 files changed, 42 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/1] i2c: omap: correct usage of the interrupt enable register
I've just removed unnecessary Change-Id line. If the i2c controller during suspend will generate an interrupt, it can lead to unpredictable behaviour in the kernel. Based on the logic of the kernel code interrupts from i2c should be prohibited during suspend. Kernel writes 0 to the I2C_IE register in the omap_i2c_runtime_suspend() function. In the other side kernel writes saved interrupt flags to the I2C_IE register in omap_i2c_runtime_resume() function. I.e. interrupts should be disabled during suspend. This works for chips with version1 registers scheme. Interrupts are disabled during suspend. For chips with version2 scheme registers writting 0 to the I2C_IE register does nothing (because now the I2C_IRQENABLE_SET register is located at this address). This register is used to enable interrupts. For disabling interrupts I2C_IRQENABLE_CLR register should be used. Because the registers I2C_IRQENABLE_SET and I2C_IE have the same addresses, the interrupt enabling procedure is unchanged. I've checked that interrupts in the i2c controller are still enabled after writting 0 to the I2C_IE register. But with my patch interrupts are disabled in the omap_i2c_runtime_suspend() function. This has been working up until now because we've just been lucky. Next patch fixes it. Patch is based on: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag: v3.10-rc2 Verified on OMAP4430. Oleksandr Dmytryshyn (1): i2c: omap: correct usage of the interrupt enable register drivers/i2c/busses/i2c-omap.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) -- 1.8.2.rc2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/1] i2c: omap: correct usage of the interrupt enable register
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
addresses, the interrupt enabling procedure is unchanged.
Signed-off-by: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
---
drivers/i2c/busses/i2c-omap.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..64c26f9 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
#define I2C_OMAP_ERRATA_I207 (1 0)
#define I2C_OMAP_ERRATA_I462 (1 1)
+#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
+
struct omap_i2c_dev {
spinlock_t lock; /* IRQ synchronization */
struct device *dev;
@@ -193,6 +195,7 @@ struct omap_i2c_dev {
long latency);
u32 speed; /* Speed of bus in kHz */
u32 flags;
+ u16 scheme;
u16 cmd_err;
u8 *buf;
u8 *regs;
@@ -1082,7 +1085,7 @@ omap_i2c_probe(struct platform_device *pdev)
int irq;
int r;
u32 rev;
- u16 minor, major, scheme;
+ u16 minor, major;
/* NOTE: driver uses the static register mapping */
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1159,8 +1162,8 @@ omap_i2c_probe(struct platform_device *pdev)
*/
rev = __raw_readw(dev-base + 0x04);
- scheme = OMAP_I2C_SCHEME(rev);
- switch (scheme) {
+ dev-scheme = OMAP_I2C_SCHEME(rev);
+ switch (dev-scheme) {
case OMAP_I2C_SCHEME_0:
dev-regs = (u8 *)reg_map_ip_v1;
dev-rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
@@ -1289,7 +1292,11 @@ static int omap_i2c_runtime_suspend(struct device *dev)
_dev-iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
- omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ if (_dev-scheme == OMAP_I2C_SCHEME_0)
+ omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
+ else
+ omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
+ OMAP_I2C_IP_V2_INTERRUPTS_MASK);
if (_dev-rev OMAP_I2C_OMAP1_REV_2) {
omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
--
1.8.2.rc2
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Re: [PATCH] ARM: dts: omap3-devkit8000: fix NAND memory binding
Hello, Gentle ping. Does someone has any comments on this fix? Can someone tests on the real hardware? Regards, Florian On 05/23/2013 10:11 AM, Florian Vaussard wrote: Commit d36b4cd 'ARM: OMAP2+: Add additional GPMC timing parameters' updated GPMC binding, but omap3-devkit8000 was not updated accordingly, resulting in a broken configuration. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch --- arch/arm/boot/dts/omap3-devkit8000.dts | 29 +++-- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 8a5cdcc..e5b35f5 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -123,20 +123,21 @@ reg = 0 0 0; /* CS0, offset 0 */ nand-bus-width = 16; - gpmc,sync-clk = 0; - gpmc,cs-on = 0; - gpmc,cs-rd-off = 44; - gpmc,cs-wr-off = 44; - gpmc,adv-on = 6; - gpmc,adv-rd-off = 34; - gpmc,adv-wr-off = 44; - gpmc,we-off = 40; - gpmc,oe-off = 54; - gpmc,access = 64; - gpmc,rd-cycle = 82; - gpmc,wr-cycle = 82; - gpmc,wr-access = 40; - gpmc,wr-data-mux-bus = 0; + gpmc,device-nand; + gpmc,sync-clki-ps = 0; + gpmc,cs-on-ns = 0; + gpmc,cs-rd-off-ns = 44; + gpmc,cs-wr-off-ns = 44; + gpmc,adv-on-ns = 6; + gpmc,adv-rd-off-ns = 34; + gpmc,adv-wr-off-ns = 44; + gpmc,we-off-ns = 40; + gpmc,oe-off-ns = 54; + gpmc,access-ns = 64; + gpmc,rd-cycle-ns = 82; + gpmc,wr-cycle-ns = 82; + gpmc,wr-access-ns = 40; + gpmc,wr-data-mux-bus-ns = 0; #address-cells = 1; #size-cells = 1; -- Florian Vaussard EPFL - STI - IMT - LSRO1 MEB330 - Station 9 1015 Lausanne / Switzerland tel: +41 21 693 78 39 fax: +41 21 693 78 07 http://lsro.epfl.ch -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/1] ARM: dts: OMAP4/AM35xx: Fix missing dtb in the dtbs target
When making the dtbs target on OMAP/AM35xx, some trees are not built. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch --- arch/arm/boot/dts/Makefile |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121..8eadd4e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -149,10 +149,13 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-panda-es.dtb \ omap4-var-som.dtb \ omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb \ omap5-evm.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ - am335x-bone.dtb + am335x-bone.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/1] ARM: dts: OMAP4/AM35xx: Fix missing dtb in the dtbs target
Hello, When testing the OMAP/AM35xx DTS, I noticed that some platforms were missing from the dtbs target, forcing the user to build them manually. This patch corrects this. Regards, Florian Since v1: - Added AM35xx missing platforms Florian Vaussard (1): ARM: dts: OMAP4/AM35xx: Fix missing dtb in the dtbs target arch/arm/boot/dts/Makefile |5 - 1 files changed, 4 insertions(+), 1 deletions(-) -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7] ARM: dts: omap4-panda: Update the LED support for the panda DTS
Hi Dan,
On 05/29/2013 01:20 PM, Dan Murphy wrote:
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7clean
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
That patch was good... until Florian introduces some new constant to
improve the readability of the DTS [1].
Could you rebase on the lastest for_3.11/dts and use the macros for the
GPIO and pinctrl nodes?
Thanks,
Benoit
[1] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg89684.html
---
v7 - Update headline to add spaces -
https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60d..5fd59b3 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 0;
@@ -137,6 +142,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a 0x3/* gpio_wk7 OUTPUT | MODE 3 */
+ 0x1c 0x3/* gpio_wk8 OUTPUT | MODE 3 */
+ ;
+ };
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts
b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c21..c968a3b 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
;
};
+
+omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins =
+ 0xb6 0x3/* gpio_110 OUTPUT | MODE 3 */
+ ;
+ };
+};
+
+led_wkgpio_pins {
+ pinctrl-single,pins =
+ 0x1c 0x3/* gpio_wk8 OUTPUT | MODE 3 */
+ ;
+};
+
+leds {
+ pinctrl-0 =
+ led_gpio_pins
+ led_wkgpio_pins
+ ;
+
+ heartbeat {
+ gpios = gpio4 14 0;
+ };
+ mmc {
+ gpios = gpio1 8 0;
+ };
+};
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Re: [PATCH v7] ARM: dts: omap4-panda: Update the LED support for the panda DTS
Hi On 05/31/2013 09:06 AM, Benoit Cousson wrote: Hi Dan, On 05/29/2013 01:20 PM, Dan Murphy wrote: The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es are different. A1-A3 = gpio_wk7clean ES = gpio_110 There is no change to LED D2 Abstract away the pinmux and the LED definitions for the two boards into the respective DTS files. Signed-off-by: Dan Murphy dmur...@ti.com That patch was good... until Florian introduces some new constant to improve the readability of the DTS [1]. Could you rebase on the lastest for_3.11/dts and use the macros for the GPIO and pinctrl nodes? N/P working on it now Thanks Thanks, Benoit [1] http://www.mail-archive.com/linux-omap@vger.kernel.org/msg89684.html -- -- Dan Murphy -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] ARM: dts: OMAP4/AM35xx: Fix missing dtb in the dtbs target
On 05/31/2013 04:05 PM, Florian Vaussard wrote: When making the dtbs target on OMAP/AM35xx, some trees are not built. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch Thanks for the fix Florian. I need to applied your AM series first to take that one otherwise the am3517-evm will fail since it depends on omap3.dtsi. BTW, I applied some more AM patches in my branch, and I cannot apply ARM: dts: AM33XX: Use pinctrl constants anymore. Just wait for some review from AM folks before updating the whole series. Regards, Benoit --- arch/arm/boot/dts/Makefile |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9f7121..8eadd4e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -149,10 +149,13 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ omap4-panda-es.dtb \ omap4-var-som.dtb \ omap4-sdp.dtb \ + omap4-sdp-es23plus.dtb \ omap5-evm.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ - am335x-bone.dtb + am335x-bone.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8] ARM: dts: omap4-panda: Update the LED support for the panda DTS
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..523a800 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 OUTPUT |
MODE 3 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 OUTPUT |
MODE 3 */
+ ;
+ };
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts
b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..5551ec6 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
0x5e (PIN_INPUT | MUX_MODE0)/* hdmi_sda.hdmi_sda */
;
};
+
+omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins =
+ 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 OUTPUT |
MODE 3 */
+ ;
+ };
+};
+
+led_wkgpio_pins {
+ pinctrl-single,pins =
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 OUTPUT | MODE 3 */
+ ;
+};
+
+leds {
+ pinctrl-0 =
+ led_gpio_pins
+ led_wkgpio_pins
+ ;
+
+ heartbeat {
+ gpios = gpio4 14 0;
+ };
+ mmc {
+ gpios = gpio1 8 0;
+ };
+};
--
1.7.5.4
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Re: [PATCH 11/11] i2c: omap: enhance pinctrl support
On 05/31/2013 01:13 PM, Hebbar Gururaja wrote:
Amend the I2C omap pin controller to optionally take a pin control
handle and set the state of the pins to:
- default on boot, resume and before performing an i2c transfer
- idle after initial default, after resume default, and after each
i2c xfer
- sleep on suspend()
By optionally putting the pins into sleep state in the suspend callback
we can accomplish two things.
- One is to minimize current leakage from pins and thus save power,
- second, we can prevent the IP from driving pins output in an
uncontrolled manner, which may happen if the power domain drops the
domain regulator.
Note:
A .suspend .resume callback is added which simply puts the pins to sleep
state upon suspend are moved to default idle state upon resume.
If any of the above pin states are missing in dt, a warning message
about the missing state is displayed.
If certain pin-states are not available, to remove this warning message
pass respective state name with null phandler.
(Changes based on i2c-nomadik.c)
Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Wolfram Sang w...@the-dreams.de
Cc: linux-omap@vger.kernel.org
Cc: linux-...@vger.kernel.org
---
:100644 100644 e02f9e3... 588ba28... M drivers/i2c/busses/i2c-omap.c
drivers/i2c/busses/i2c-omap.c | 112 ++---
1 file changed, 105 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..588ba28 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -214,7 +214,11 @@ struct omap_i2c_dev {
u16 westate;
u16 errata;
- struct pinctrl *pins;
+ /* Three pin states - default, idle sleep */
+ struct pinctrl *pinctrl;
+ struct pinctrl_state*pins_default;
+ struct pinctrl_state*pins_idle;
+ struct pinctrl_state*pins_sleep;
};
static const u8 reg_map_ip_v1[] = {
@@ -641,6 +645,11 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
if (IS_ERR_VALUE(r))
goto out;
The current HWMOD framework configures PINs to enable state before
enabling the device and
switch PINs to idle state after disabling the device. Why here its done
in different order?
+ /* Optionaly enable pins to be muxed in and configured */
+ if (!IS_ERR(dev-pins_default))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_default))
+ dev_err(dev-dev, could not set default pins\n);
+
r = omap_i2c_wait_for_bb(dev);
if (r 0)
goto out;
@@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg
msgs[], int num)
out:
pm_runtime_mark_last_busy(dev-dev);
+
pm_runtime_put_autosuspend(dev-dev);
+ /* Optionally let pins go into idle state */
+ if (!IS_ERR(dev-pins_idle))
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_idle))
+ dev_err(dev-dev, could not set pins to idle state\n);
+
return r;
}
@@ -1123,14 +1138,47 @@ omap_i2c_probe(struct platform_device *pdev)
dev-set_mpu_wkup_lat = pdata-set_mpu_wkup_lat;
}
- dev-pins = devm_pinctrl_get_select_default(pdev-dev);
- if (IS_ERR(dev-pins)) {
- if (PTR_ERR(dev-pins) == -EPROBE_DEFER)
+ dev-pinctrl = devm_pinctrl_get(pdev-dev);
May be struct device -pins-p can be used instead of dev-pinctrl?
+ if (!IS_ERR(dev-pinctrl)) {
+ dev-pins_default = pinctrl_lookup_state(dev-pinctrl,
+PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(dev-pins_default))
+ dev_dbg(pdev-dev, could not get default pinstate\n);
+ else
+ if (pinctrl_select_state(dev-pinctrl,
+dev-pins_default))
+ dev_err(pdev-dev,
+ could not set default pinstate\n);
Don't need to set Default pin state
Default pins state is applied by DD framework automatically before
device probing
and stored in struct device -pins-default_state
+
+ dev-pins_idle = pinctrl_lookup_state(dev-pinctrl,
+ PINCTRL_STATE_IDLE);
+ if (IS_ERR(dev-pins_idle))
+ dev_dbg(pdev-dev, could not get idle pinstate\n);
+ else
+ /* If possible, let's idle until the first transfer */
+ if (pinctrl_select_state(dev-pinctrl, dev-pins_idle))
+ dev_err(pdev-dev,
+ could not set idle pinstate\n);
+
+ dev-pins_sleep =
Re: [PATCHv2 1/3] arm: introduce config HAS_BANDGAP
Tony, Russell, On 15-05-2013 10:58, Eduardo Valentin wrote: Introduce HAS_BANDGAP config entry. This config is a boolean value so that arch code can flag is they feature a bandgap device. This config entry follows the same idea behind ARCH_HAS_CPUFREQ. Cc: Russell King li...@arm.linux.org.uk Cc: Tony Lindgren t...@atomide.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-omap@vger.kernel.org Cc: linux-ker...@vger.kernel.org Signed-off-by: Eduardo Valentin eduardo.valen...@ti.com Gentle reminder on this one. --- arch/arm/Kconfig| 3 +++ arch/arm/mach-omap2/Kconfig | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d423d58..bcbdec9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -174,6 +174,9 @@ config ARCH_HAS_CPUFREQ and that the relevant menu configurations are displayed for it. +config ARCH_HAS_BANDGAP + bool + config GENERIC_HWEIGHT bool default y diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index f49cd51..8620ab5 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -4,6 +4,7 @@ config ARCH_OMAP config ARCH_OMAP2PLUS bool TI OMAP2/3/4/5 SoCs with device tree support if (ARCH_MULTI_V6 || ARCH_MULTI_V7) select ARCH_HAS_CPUFREQ + select ARCH_HAS_BANDGAP select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_OMAP select ARCH_REQUIRE_GPIOLIB -- You have got to be excited about what you are doing. (L. Lamport) Eduardo Valentin signature.asc Description: OpenPGP digital signature
Re: [PATCH v8] ARM: dts: omap4-panda: Update the LED support for the panda DTS
On Fri, May 31, 2013 at 4:48 PM, Dan Murphy dmur...@ti.com wrote:
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces -
https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..523a800 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 OUTPUT |
MODE 3 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 OUTPUT |
MODE 3 */
Hello Dan,
The OUTPUT | MODE 3 in the comments were added so people shouldn't
have to look at the TRM to find what each constant number meant. But
now using the macros this is not needed anymore, so I don't think is
necessary to keep that on the comments.
Best regards,
Javier
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Re: [PATCHv2 1/3] arm: introduce config HAS_BANDGAP
On Wed, May 15, 2013 at 11:58 AM, Eduardo Valentin eduardo.valen...@ti.com wrote: Introduce HAS_BANDGAP config entry. This config is a boolean value so that arch code can flag is they feature a bandgap device. This config entry follows the same idea behind ARCH_HAS_CPUFREQ. It would be nice if you explain what BANDGAP means here, since you introduce this option in this patch. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v8] ARM: dts: omap4-panda: Update the LED support for the panda DTS
On 05/31/2013 10:05 AM, Javier Martinez Canillas wrote:
On Fri, May 31, 2013 at 4:48 PM, Dan Murphy dmur...@ti.com wrote:
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces -
https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..523a800 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 OUTPUT |
MODE 3 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 OUTPUT |
MODE 3 */
Hello Dan,
The OUTPUT | MODE 3 in the comments were added so people shouldn't
have to look at the TRM to find what each constant number meant. But
now using the macros this is not needed anymore, so I don't think is
necessary to keep that on the comments.
Best regards,
Javier
Yes you are correct sending update to remove the comments
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Re: [PATCH 05/32] OMAPDSS: fix dss_get_ctx_loss_count for DT
On 05/30/2013 07:36 PM, Kevin Hilman wrote:
Tomi Valkeinen tomi.valkei...@ti.com writes:
When using DT, dss device does not have platform data. However,
dss_get_ctx_loss_count() uses dss device's platform data to find the
get_ctx_loss_count function pointer.
To fix this, dss_get_ctx_loss_count() needs to be changed to get the
platform data from the omapdss device, which is a virtual device and
always has platform data.
Dumb question (since the DSS device model has always been beyond my
grasp): how/why does the virtual device still have platform_data on a DT
boot?
Also, this context_loss_count and DT boot is starting to get cumbersome,
and there's currently no (good) way of handling the context loss in a
generic way without pdata function pointers.
I'm starting to think we should move towards dropping this OMAP-specific
context loss counting, and just assume context is always lost. If there
are performance problems, runtime PM autosuspend timeouts can be used to
avoid the transitions.
Or, on some devices, I suspect comparing a few registers against their
power-on reset values might be a quicker way of detecting lost context
and would avoid having to call into platform code all together.
Hi Kevin,
I've a question:
Why don't add API in Kernel/Base PM framework for context lost detection?
Like pm_was_ctx_lost().
If this topic has been discussed already (many times)) - sorry for the
noise.
And I'll be very appreciate if you can point me on corresponding
discussions.
Kevin
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dss.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 94f66f9..bd01608 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -157,7 +157,8 @@ static void dss_restore_context(void)
int dss_get_ctx_loss_count(void)
{
- struct omap_dss_board_info *board_data = dss.pdev-dev.platform_data;
+ struct platform_device *core_pdev = dss_get_core_pdev();
+ struct omap_dss_board_info *board_data = core_pdev-dev.platform_data;
int cnt;
if (!board_data-get_context_loss_count)
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[PATCH v9] ARM: dts: omap4-panda: Update the LED support for the panda DTS
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v9 - Removed comments for mux config -
https://patchwork.kernel.org/patch/2644391/
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..800fa4e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+ };
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts
b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..0a7812f 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
0x5e (PIN_INPUT | MUX_MODE0)/* hdmi_sda.hdmi_sda */
;
};
+
+omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins =
+ 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
+ ;
+ };
+};
+
+led_wkgpio_pins {
+ pinctrl-single,pins =
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+};
+
+leds {
+ pinctrl-0 =
+ led_gpio_pins
+ led_wkgpio_pins
+ ;
+
+ heartbeat {
+ gpios = gpio4 14 0;
+ };
+ mmc {
+ gpios = gpio1 8 0;
+ };
+};
--
1.7.5.4
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Re: [PATCHv2 3/3] arm: dts: add bandgap entry for OMAP4460 devices
On 08:29 Thu 16 May , Eduardo Valentin wrote:
On 15-05-2013 12:57, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 12:36 Wed 15 May , Eduardo Valentin wrote:
On 15-05-2013 11:23, Benoit Cousson wrote:
Hi Eduardo,
On 05/15/2013 04:58 PM, Eduardo Valentin wrote:
Include bandgap devices for OMAP4460 devices.
Cc: Benoît Cousson b-cous...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Russell King li...@arm.linux.org.uk
Cc: linux-omap@vger.kernel.org
Cc: devicetree-disc...@lists.ozlabs.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Eduardo Valentin eduardo.valen...@ti.com
---
arch/arm/boot/dts/omap4460.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/omap4460.dtsi
b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c..e5bfbfe 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -29,4 +29,13 @@
0 55 0x4;
ti,hwmods = debugss;
};
+
+bandgap {
+reg = 0x4a002260 0x4
+0x4a00232C 0x4
+0x4a002378 0x18;
+compatible = ti,omap4460-bandgap;
+interrupts = 0 126 4; /* talert */
+ti,tshut-gpio = 86;
Why do you need a custom attribute for GPIO? Cannot you use the standard
one?
I believe it was by your suggestion :-), during the first attempts to
send this driver. But could not find the thread link :-( sorry.
I guess the reasoning to mark it as a ti specific is because it will be
used as IRQ line to treat thermal shutdown (in SW).
so use interrup-parent
Jean-Christophe,
That will change the controller and break the configuration for the
other IRQ line, coming from GIC.
put this on hold I'm preparing a fix for this
I've discuss with Grant already.
This way for me is buggy
Best Regards,
J.
Where is the gpio controller phandle?
Usually it looks like this:
gpios = gpio1 8 0;
Regards,
Benoit
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Re: [PATCH v9] ARM: dts: omap4-panda: Update the LED support for the panda DTS
Hello Dan,
On 05/31/2013 05:19 PM, Dan Murphy wrote:
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v9 - Removed comments for mux config -
https://patchwork.kernel.org/patch/2644391/
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..800fa4e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+ };
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts
b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..0a7812f 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
0x5e (PIN_INPUT | MUX_MODE0)/* hdmi_sda.hdmi_sda */
;
};
+
+omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins =
+ 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
+ ;
+ };
+};
+
+led_wkgpio_pins {
+ pinctrl-single,pins =
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+};
+
+leds {
+ pinctrl-0 =
+ led_gpio_pins
+ led_wkgpio_pins
+ ;
+
+ heartbeat {
+ gpios = gpio4 14 0;
And here you could use the GPIO defines:
gpios = gpio4 14 GPIO_ACTIVE_HIGH;
+ };
+ mmc {
+ gpios = gpio1 8 0;
Same here.
+ };
+};
Regards,
Florian
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[PATCH v10 1/2] ARM: dts: omap4-panda: Update the LED support for the panda DTS
The GPIO for LED D1 on the omap4-panda a1-a3 rev and the omap4-panda-es
are different.
A1-A3 = gpio_wk7
ES = gpio_110
There is no change to LED D2
Abstract away the pinmux and the LED definitions for the two boards into
the respective DTS files.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v10 - Update gpio entries to use gpio macros -
https://patchwork.kernel.org/patch/2644561/
v9 - Removed comments for mux config -
https://patchwork.kernel.org/patch/2644391/
v8 - Rebase to latest and use pinctrl macros -
https://patchwork.kernel.org/patch/2629351/
v7 - Update headline to add spaces - https://patchwork.kernel.org/patch/2583661/
v6 - Review comments updated - https://patchwork.kernel.org/patch/2582771/
v5 - Provide pincrtl phandle to the gpio-led driver -
https://patchwork.kernel.org/patch/2573981/
arch/arm/boot/dts/omap4-panda-common.dtsi | 16 +++-
arch/arm/boot/dts/omap4-panda-es.dts | 28
2 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d5d144a..800fa4e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -16,8 +16,13 @@
reg = 0x8000 0x4000; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 =
+ led_wkgpio_pins
+ ;
+
heartbeat {
label = pandaboard::status1;
gpios = gpio1 7 GPIO_ACTIVE_HIGH;
@@ -157,6 +162,15 @@
};
};
+omap4_pmx_wkup {
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins =
+ 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+ };
+};
+
i2c1 {
pinctrl-names = default;
pinctrl-0 = i2c1_pins;
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts
b/arch/arm/boot/dts/omap4-panda-es.dts
index 5cfdf19..56c4354 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -34,3 +34,31 @@
0x5e (PIN_INPUT | MUX_MODE0)/* hdmi_sda.hdmi_sda */
;
};
+
+omap4_pmx_core {
+ led_gpio_pins: gpio_led_pmx {
+ pinctrl-single,pins =
+ 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
+ ;
+ };
+};
+
+led_wkgpio_pins {
+ pinctrl-single,pins =
+ 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
+ ;
+};
+
+leds {
+ pinctrl-0 =
+ led_gpio_pins
+ led_wkgpio_pins
+ ;
+
+ heartbeat {
+ gpios = gpio4 14 GPIO_ACTIVE_HIGH;
+ };
+ mmc {
+ gpios = gpio1 8 GPIO_ACTIVE_HIGH;
+ };
+};
--
1.7.5.4
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[PATCH v1] ARM: dts: omap4-panda: Update the twl6040 gpio to macro definition
Update the dt property ti,audpwron-gpio to use the gpio macro definition for GPIO_ACTIVE_HIGH. Signed-off-by: Dan Murphy dmur...@ti.com --- arch/arm/boot/dts/omap4-panda-common.dtsi |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 800fa4e..00cbaa5 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -190,7 +190,7 @@ /* IRQ# = 119 */ interrupts = GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = gic; - ti,audpwron-gpio = gpio4 31 0; /* gpio line 127 */ + ti,audpwron-gpio = gpio4 31 GPIO_ACTIVE_HIGH; /* gpio line 127 */ vio-supply = v1v8; v2v1-supply = v2v1; -- 1.7.5.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] gpio/omap: omap_gpio_init_context stub must be inline
The bug fix 352a2d5bf gpio/omap: ensure gpio context is initialised
has caused a new warning for omap1_defconfig:
drivers/gpio/gpio-omap.c:1465:13: warning: 'omap_gpio_init_context' defined but
not used [-Wunused-function]
static void omap_gpio_init_context(struct gpio_bank *p) {}
^
The solution is to mark the stub function as 'static inline' so
it gets left out of the build when unused.
Signed-off-by: Arnd Bergmann a...@arndb.de
---
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index d3f7d2d..e5fba65 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1462,7 +1462,7 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
#else
#define omap_gpio_runtime_suspend NULL
#define omap_gpio_runtime_resume NULL
-static void omap_gpio_init_context(struct gpio_bank *p) {}
+static inline void omap_gpio_init_context(struct gpio_bank *p) {}
#endif
static const struct dev_pm_ops gpio_pm_ops = {
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Re: [PATCH v1] ARM: dts: omap4-panda: Update the twl6040 gpio to macro definition
Hello Dan, On 05/31/2013 05:45 PM, Dan Murphy wrote: Update the dt property ti,audpwron-gpio to use the gpio macro definition for GPIO_ACTIVE_HIGH. Signed-off-by: Dan Murphy dmur...@ti.com --- arch/arm/boot/dts/omap4-panda-common.dtsi |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 800fa4e..00cbaa5 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -190,7 +190,7 @@ /* IRQ# = 119 */ interrupts = GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH; /* IRQ_SYS_2N cascaded to gic */ interrupt-parent = gic; - ti,audpwron-gpio = gpio4 31 0; /* gpio line 127 */ + ti,audpwron-gpio = gpio4 31 GPIO_ACTIVE_HIGH; /* gpio line 127 */ vio-supply = v1v8; v2v1-supply = v2v1; I missed it during the conversion, thank you. Reviewed-by: Florian Vaussard florian.vauss...@epfl.ch -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] ARM: dts: OMAP4/AM35xx: Fix missing dtb in the dtbs target
Hello Benoit, On 05/31/2013 04:45 PM, Benoit Cousson wrote: On 05/31/2013 04:05 PM, Florian Vaussard wrote: When making the dtbs target on OMAP/AM35xx, some trees are not built. Signed-off-by: Florian Vaussard florian.vauss...@epfl.ch Thanks for the fix Florian. I need to applied your AM series first to take that one otherwise the am3517-evm will fail since it depends on omap3.dtsi. Right. It was a bad idea to split in two series, sorry. BTW, I applied some more AM patches in my branch, and I cannot apply ARM: dts: AM33XX: Use pinctrl constants anymore. Just wait for some review from AM folks before updating the whole series. Ok, I will rebase on your branch in the coming days. Regards, Florian -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] i2c: omap: correct usage of the interrupt enable register
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
On 05/30/2013 07:46 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
If the i2c controller during suspend will generate an interrupt, it
can lead to unpredictable behaviour in the kernel.
Based on the logic of the kernel code interrupts from i2c should be
prohibited during suspend. Kernel writes 0 to the I2C_IE register in
the omap_i2c_runtime_suspend() function. In the other side kernel
writes saved interrupt flags to the I2C_IE register in
omap_i2c_runtime_resume() function. I.e. interrupts should be disabled
during suspend.
This works for chips with version1 registers scheme. Interrupts are
disabled during suspend. For chips with version2 scheme registers
writting 0 to the I2C_IE register does nothing (because now the
I2C_IRQENABLE_SET register is located at this address). This register
is used to enable interrupts. For disabling interrupts
I2C_IRQENABLE_CLR register should be used.
Because the registers I2C_IRQENABLE_SET and I2C_IE have the same
addresses, the interrupt enabling procedure is unchanged.
Signed-off-by: Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com
Much better, but still doesn't explain how/why this has been working up
until now. Have we just been lucky?
Yes, this has been working up until now because we've just been lucky.
What I'm trying to say is you need to describe that in the changelog,
with more details. e.g. we've been lucky not to have any interrupts
fire during the suspend path, otherwise we would have
Kevin
---
drivers/i2c/busses/i2c-omap.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e3..2419899 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
#define I2C_OMAP_ERRATA_I207 (1 0)
#define I2C_OMAP_ERRATA_I462 (1 1)
+#define OMAP_I2C_INTERRUPTS_MASK 0x6FFF
To be more clear, this should probably have v2 in the name.
I'll rename this mask in the patch-set v3
Kevin
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Re: [PATCH 11/11] i2c: omap: enhance pinctrl support
Hebbar Gururaja gururaja.heb...@ti.com writes: Amend the I2C omap pin controller to optionally take a pin control handle and set the state of the pins to: - default on boot, resume and before performing an i2c transfer - idle after initial default, after resume default, and after each i2c xfer - sleep on suspend() By optionally putting the pins into sleep state in the suspend callback we can accomplish two things. - One is to minimize current leakage from pins and thus save power, - second, we can prevent the IP from driving pins output in an uncontrolled manner, which may happen if the power domain drops the domain regulator. Note: A .suspend .resume callback is added which simply puts the pins to sleep state upon suspend are moved to default idle state upon resume. If any of the above pin states are missing in dt, a warning message about the missing state is displayed. If certain pin-states are not available, to remove this warning message pass respective state name with null phandler. (Changes based on i2c-nomadik.c) Signed-off-by: Hebbar Gururaja gururaja.heb...@ti.com Cc: Tony Lindgren t...@atomide.com Cc: Wolfram Sang w...@the-dreams.de Cc: linux-omap@vger.kernel.org Cc: linux-...@vger.kernel.org [...] @@ -664,7 +673,13 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) out: pm_runtime_mark_last_busy(dev-dev); + pm_runtime_put_autosuspend(dev-dev); + /* Optionally let pins go into idle state */ + if (!IS_ERR(dev-pins_idle)) + if (pinctrl_select_state(dev-pinctrl, dev-pins_idle)) + dev_err(dev-dev, could not set pins to idle state\n); This is wrong. You're changing the muxing before the device actually goes idle. Anything you want to happen when the device actually idles for real has to be in runtime PM callbacks. Looking below, I see it's already in the callbacks, so why is it here also? [...] @@ -1300,6 +1348,10 @@ static int omap_i2c_runtime_suspend(struct device *dev) omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); } + if (!IS_ERR(_dev-pins_idle)) + if (pinctrl_select_state(_dev-pinctrl, _dev-pins_idle)) + dev_err(dev, could not set pins to idle state\n); + return 0; } Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/1] i2c: omap: correct usage of the interrupt enable register
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes: I've just removed unnecessary Change-Id line. If the i2c controller during suspend will generate an interrupt, it can lead to unpredictable behaviour in the kernel. Based on the logic of the kernel code interrupts from i2c should be prohibited during suspend. Kernel writes 0 to the I2C_IE register in the omap_i2c_runtime_suspend() function. In the other side kernel writes saved interrupt flags to the I2C_IE register in omap_i2c_runtime_resume() function. I.e. interrupts should be disabled during suspend. This works for chips with version1 registers scheme. Interrupts are disabled during suspend. For chips with version2 scheme registers writting 0 to the I2C_IE register does nothing (because now the I2C_IRQENABLE_SET register is located at this address). This register is used to enable interrupts. For disabling interrupts I2C_IRQENABLE_CLR register should be used. Because the registers I2C_IRQENABLE_SET and I2C_IE have the same addresses, the interrupt enabling procedure is unchanged. I've checked that interrupts in the i2c controller are still enabled after writting 0 to the I2C_IE register. But with my patch interrupts are disabled in the omap_i2c_runtime_suspend() function. This has been working up until now because we've just been lucky. This belongs in the changelog of the patch, not the cover letter and needs more detail. Also, you don't need a cover letter on a 1-patch series. Kevin Next patch fixes it. Patch is based on: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git tag: v3.10-rc2 Verified on OMAP4430. Oleksandr Dmytryshyn (1): i2c: omap: correct usage of the interrupt enable register drivers/i2c/busses/i2c-omap.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/32] OMAPDSS: fix dss_get_ctx_loss_count for DT
Hi Grygorii, Grygorii Strashko grygorii.stras...@ti.com writes: [...] I've a question: Why don't add API in Kernel/Base PM framework for context lost detection? Like pm_was_ctx_lost(). I'm not aware of any proposals to do this in a generic way. Feel free to propose one if you're so moved. One complexity is that such a call is not needed on platforms that use generic power domains (not OMAP). With gen_pd, the runtime PM callbacks do not get called unless the power domains actually lose power. So for gen_pd, you assume context has been lost when your runtime PM callbacks are called. This is a bit different than how we've done it on OMAP, and there's been some work in exploring how to adapt OMAP to gen_pd, but there's not anyone actively working on it at the moment. That being said, I'm still leaning towards simply removing the context loss logic from all the OMAP drivers. This feature adds a relatively minor optimization, and a more configurable optimization could be done using runtime PM autosuspend timeouts (configurable from userspace.) Combined with the fact that adoption of gen_pd means we don't need it, I'm included to drop it all together. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 1/1] ARM : omap3 : fix wrong container_of in clock36xx.c
Quoting Jean-Philippe Francois (2013-05-30 01:50:27)
omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the
clock
to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned
clock
have parent defined as clk_divider. Instead of using container_of to
eventually get
to the register and directly mess with the divider, change freq via
clk_set_rate,
and let the clock framework toggle the divider value.
Tested with 3.9 on dm3730.
Signed-off-by: Jean-Philippe Fran��ois jp.franc...@cynove.com
Did you use git-format-patch to create this patch? Its a bit nicer to
use that or if you just use diff then use diff -up or diff -uprN
(taken from Documentation/SubmittingPatches.txt).
Also did you test this to make sure it works? I don't mean a boot test,
but actually disabling/re-enabling an HSDIVIDER on 3630? The previous
code just programmed the clksel field to 1, and this code divides the
rate by 2, then restores it. I just used that as an example in my
previous email and it needs to be verified that it works (though it
should if I remember this errata correctly).
If that testing is done and everything looks good then please add:
Acked-by: Mike Turquette mturque...@linaro.org
Index: b/arch/arm/mach-omap2/clock36xx.c
===
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -39,30 +39,25 @@
*/
int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
{
- struct clk_hw_omap *parent;
- struct clk_hw *parent_hw;
- u32 dummy_v, orig_v, clksel_shift;
int ret;
/* Clear PWRDN bit of HSDIVIDER */
ret = omap2_dflt_clk_enable(clk);
- parent_hw = __clk_get_hw(__clk_get_parent(clk-clk));
- parent = to_clk_hw_omap(parent_hw);
-
- /* Restore the dividers */
+ /* kick parent's clksel register after toggling PWRDN bit */
if (!ret) {
- clksel_shift = __ffs(parent-clksel_mask);
- orig_v = __raw_readl(parent-clksel_reg);
- dummy_v = orig_v;
-
- /* Write any other value different from the Read value */
- dummy_v ^= (1 clksel_shift);
- __raw_writel(dummy_v, parent-clksel_reg);
-
- /* Write the original divider */
- __raw_writel(orig_v, parent-clksel_reg);
+ struct clk *parent = clk_get_parent(clk-clk);
+ unsigned long parent_rate = clk_get_rate(parent);
+ ret = clk_set_rate(parent, parent_rate/2);
+ if(ret)
+ goto badfreq;
+ ret = clk_set_rate(parent, parent_rate);
+ if(ret)
+ goto badfreq;
}
+ return ret;
+ badfreq :
+ omap2_dflt_clk_disable(clk);
return ret;
}
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[PATCH] mfd: twl-core: convert to module_init()
There's no reason for twl-core to be subsys_inicall anymore. Anything
using twl that early needs a rethink, or deferred probe changes.
Boot tested and RTC wake tested (via TWL RTC) on OMAP platforms:
3530/Beagle, 3730/Beagle-xM, 3530/Overo, 3730/Overo-STORM, 4430/Panda,
4460/Panda-ES.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
drivers/mfd/twl-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 89ab4d9..7749b9e 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1309,7 +1309,7 @@ static int __init twl_init(void)
{
return i2c_add_driver(twl_driver);
}
-subsys_initcall(twl_init);
+module_init(twl_init);
static void __exit twl_exit(void)
{
--
1.8.2
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Re: [PATCH] mfd: twl-core: convert to module_init()
* Kevin Hilman khil...@linaro.org [130531 14:02]:
There's no reason for twl-core to be subsys_inicall anymore. Anything
using twl that early needs a rethink, or deferred probe changes.
Boot tested and RTC wake tested (via TWL RTC) on OMAP platforms:
3530/Beagle, 3730/Beagle-xM, 3530/Overo, 3730/Overo-STORM, 4430/Panda,
4460/Panda-ES.
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kevin Hilman khil...@linaro.org
Totally agree:
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mfd/twl-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 89ab4d9..7749b9e 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1309,7 +1309,7 @@ static int __init twl_init(void)
{
return i2c_add_driver(twl_driver);
}
-subsys_initcall(twl_init);
+module_init(twl_init);
static void __exit twl_exit(void)
{
--
1.8.2
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[PATCH] mfd: twl4030: allow IRQ wake enable to succeed on subchip IRQs
The genirq IRQ wake method will default to failure if the irq_chip
does not provide a set_wake method. However, for TWL4030 sub-chip
IRQs, we want the wake enable to succeed even though we don't provide
a set_wake method. This allows sub-chip IRQs to still be flagged as
wakeup capable, and allow them to wakeup from suspend (or abort
suspend if they fire during suspend.)
To fix, use the IRQCHIP_SKIP_SET_WAKE flag in the irq_chip.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
drivers/mfd/twl4030-irq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index a5f9888..3fa7df2 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -573,6 +573,7 @@ static struct irq_chip twl4030_sih_irq_chip = {
.irq_set_type = twl4030_sih_set_type,
.irq_bus_lock = twl4030_sih_bus_lock,
.irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock,
+ .flags = IRQCHIP_SKIP_SET_WAKE,
};
/*--*/
--
1.8.2
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RE: [PATCH 1/2] ARM: dts: OMAP5: add PWM capability to timer nodes missing it
Benoit, Tony,
On 04/17/2013 06:23 PM, Suman Anna wrote:
OMAP5 has 6 timers (GPTimers 5, 6, 8 to 11) that are capable of PWM.
The PWM capability property is missing from the node definitions of
couple of timers, and this has been fixed.
Signed-off-by: Suman Anna s-a...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 790bb2a..0d155f5 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -422,6 +422,7 @@
interrupts = 0 41 0x4;
ti,hwmods = timer5;
ti,timer-dsp;
+ ti,timer-pwm;
};
timer6: timer@4013a000 {
@@ -458,6 +459,7 @@
reg = 0x4803e000 0x80;
interrupts = 0 45 0x4;
ti,hwmods = timer9;
+ ti,timer-pwm;
};
timer10: timer@48086000 {
@@ -465,6 +467,7 @@
reg = 0x48086000 0x80;
interrupts = 0 46 0x4;
ti,hwmods = timer10;
+ ti,timer-pwm;
};
timer11: timer@48088000 {
Make sure you copy the linux-arm and device-tree mailing lists.
Acked-by: Jon Hunter jon-hun...@ti.com
Can you include this patch in your next fixes pull request (if you haven't
already done so)? The other patch in the series is a feature change, but
this is a fix, and can go into 3.10 itself.
Regards
Suman
[PATCH] rtc: rtc-twl: ensure IRQ is wakeup enabled
Currently, the RTC IRQ is never wakeup-enabled so is not capable of
bringing the system out of suspend.
On OMAP platforms, we have gotten by without this because the TWL RTC
is on an I2C-connected chip which is capable of waking up the OMAP via
the IO ring when the OMAP is in low-power states.
However, if the OMAP suspends without hitting the low-power states
(and the IO ring is not enabled), RTC wakeups will not work because
the IRQ is not wakeup enabled.
To fix, ensure the RTC IRQ is wakeup enabled whenever the RTC alarm is
set.
Cc: Alessandro Zummo a.zu...@towertech.it
Cc: Andrew Morton a...@linux-foundation.org
Cc: Tony Lindgren t...@atomide.com
Signed-off-by: Kevin Hilman khil...@linaro.org
---
drivers/rtc/rtc-twl.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a52..bbda0fd 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -213,12 +213,24 @@ static int mask_rtc_irq_bit(unsigned char bit)
static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
+ struct platform_device *pdev = to_platform_device(dev);
+ int irq = platform_get_irq(pdev, 0);
+ static bool twl_rtc_wake_enabled;
int ret;
- if (enabled)
+ if (enabled) {
ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
- else
+ if (device_can_wakeup(dev) !twl_rtc_wake_enabled) {
+ enable_irq_wake(irq);
+ twl_rtc_wake_enabled = true;
+ }
+ } else {
ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
+ if (twl_rtc_wake_enabled) {
+ disable_irq_wake(irq);
+ twl_rtc_wake_enabled = false;
+ }
+ }
return ret;
}
--
1.8.2
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[PATCH 1/3] ARM: DTS: OMAP3: beagle/overo: mux console UART, enable wakeup
Ensure the console uart (UART3) on these boards is mux'd correctly, and
IO ring wakeup is enabled.
This is needed for serial console wakeups when using DT boot.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 14 ++
arch/arm/boot/dts/omap3-beagle.dts| 12
arch/arm/boot/dts/omap3-overo.dtsi| 14 ++
3 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f..ca067b0 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -126,3 +126,17 @@
mode = 3;
power = 50;
};
+
+omap3_pmx_core {
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins =
+ 0x16e 0x4100/* uart3_rx_irrx.uart3_rx_irrx WAKEUP |
INPUT | MODE0 */
+ 0x170 0x0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT |
MODE0 */
+ ;
+ };
+};
+
+uart3 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_pins;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec699..b004372 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -95,6 +95,13 @@
0x1ae 0x10b /*
USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
;
};
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins =
+ 0x16e 0x4100/* uart3_rx_irrx.uart3_rx_irrx WAKEUP |
INPUT | MODE0 */
+ 0x170 0x0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT |
MODE0 */
+ ;
+ };
};
i2c1 {
@@ -142,3 +149,8 @@
*/
ti,pulldowns = 0x03a1c4;
};
+
+uart3 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_pins;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi
b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50..d63ed39 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -77,3 +77,17 @@
mode = 3;
power = 50;
};
+
+omap3_pmx_core {
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins =
+ 0x16e 0x4100/* uart3_rx_irrx.uart3_rx_irrx WAKEUP |
INPUT | MODE0 */
+ 0x170 0x0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT |
MODE0 */
+ ;
+ };
+};
+
+uart3 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_pins;
+};
--
1.8.2
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[PATCH 3/3] ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line
On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP. Therefore, configure the defaults for the
SYS_NIRQ pin in the twl4030 DTS file.
Boards that hook up the twl4030 differently can easily override this
in their board-specific DTS file.
This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030. Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/twl4030.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index b3034da..c7fe9f6 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -13,6 +13,8 @@
compatible = ti,twl4030;
interrupt-controller;
#interrupt-cells = 1;
+ pinctrl-names = default;
+ pinctrl-0 = twl4030_pins;
rtc {
compatible = ti,twl4030-rtc;
@@ -92,3 +94,18 @@
#pwm-cells = 2;
};
};
+
+omap3_pmx_core {
+ /*
+* On most OMAP3 platforms, the twl4030 IRQ line is connected
+ * to the SYS_NIRQ line on OMAP. Therefore, configure the
+ * defaults for the SYS_NIRQ pin here. Boards that hook up
+ * the twl4030 differently can easily override this in their
+ * board-specific DTS file.
+*/
+ twl4030_pins: pinmux_twl4030_pins {
+ pinctrl-single,pins =
+ 0x1b0 0x4118 /* sys_nirq.sys_nirq WAKEUP | INPUT_PULLUP
| MODE 0 */
+ ;
+ };
+};
--
1.8.2
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[PATCH 0/3] ARM: DTS: misc. OMAP3 fixes for proper wakeup
Benoit, Here are handful of DT updates while working on getting PM functionality working for DT boot on OMAP3. Kevin Kevin Hilman (3): ARM: DTS: OMAP3: beagle/overo: mux console UART, enable wakeup ARM: DTS: OMAP3: beagle: enable user button via gpio_keys, enable wakeup ARM: DTS: TWL4030: fix mux and wakeup for SYS_NIRQ line arch/arm/boot/dts/omap3-beagle-xm.dts | 39 +++ arch/arm/boot/dts/omap3-beagle.dts| 37 + arch/arm/boot/dts/omap3-overo.dtsi| 14 + arch/arm/boot/dts/twl4030.dtsi| 17 +++ 4 files changed, 107 insertions(+) -- 1.8.2 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] ARM: DTS: OMAP3: beagle: enable user button via gpio_keys, enable wakeup
Using the gpio-keys bindings, configure the user button on Beagle
boards. Since the user button is enabled as a wakeup source, also
ensure the GPIO pin is mux'd correctly and has IO ring wakeups enabled,
so it can also wakeup from off mode.
Signed-off-by: Kevin Hilman khil...@linaro.org
---
arch/arm/boot/dts/omap3-beagle-xm.dts | 25 +
arch/arm/boot/dts/omap3-beagle.dts| 25 +
2 files changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index ca067b0..c93c36f 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -57,6 +57,26 @@
ti,mcbsp = mcbsp2;
ti,codec = twl_audio;
};
+
+ gpio_keys {
+ compatible = gpio-keys;
+
+ user {
+ label = user;
+ gpios = gpio1 4 0;
+ linux,code = 0x114;
+ gpio-key,wakeup;
+ };
+
+ };
+};
+
+omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins =
+ 0x0e 0x4104 /* sys_boot2.gpio_4 WAKEUP | INPUT |
MODE4 */
+ ;
+ };
};
i2c1 {
@@ -140,3 +160,8 @@
pinctrl-names = default;
pinctrl-0 = uart3_pins;
};
+
+gpio1 {
+ pinctrl-names = default;
+ pinctrl-0 = gpio1_pins;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts
b/arch/arm/boot/dts/omap3-beagle.dts
index b004372..c9794cb 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -71,6 +71,26 @@
reset-supply = hsusb2_reset;
vcc-supply = hsusb2_power;
};
+
+ gpio_keys {
+ compatible = gpio-keys;
+
+ user {
+ label = user;
+ gpios = gpio1 7 0;
+ linux,code = 0x114;
+ gpio-key,wakeup;
+ };
+
+ };
+};
+
+omap3_pmx_wkup {
+ gpio1_pins: pinmux_gpio1_pins {
+ pinctrl-single,pins =
+ 0x14 0x4104 /* sys_boot5.gpio_7 WAKEUP | INPUT |
MODE4 */
+ ;
+ };
};
omap3_pmx_core {
@@ -154,3 +174,8 @@
pinctrl-names = default;
pinctrl-0 = uart3_pins;
};
+
+gpio1 {
+ pinctrl-names = default;
+ pinctrl-0 = gpio1_pins;
+};
--
1.8.2
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Re: [PATCH v3 2/3] gpio/omap: modify wake-up register with interrupt enable.
Andreas Fenkart andreas.fenk...@streamunlimited.com writes: OMAP4430 TRM chap. 25.4.5.2 To reduce dynamic consumption, an efficient idle scheme is based on the following: • An efficient local autoclock gating for each module • The implementation of control sideband signals between the PRCM module and each module This enhanced idle control allows clocks to be activated and deactivated safely without requiring complex software management. The idle mode request, idle acknowledge, and wake-up request are sideband signals between the PRCM module and the general-purpose interface OMAP4430 TRM chap. 25.4.6.2 There must be a correlation between the wake-up enable and interrupt enable register. If a GPIO pin has a wake-up configured on it, it must also have the corresponding interrupt enabled. Otherwise, it is possible there is a wake-up event, but after exiting the IDLE state, no interrupt is generated; the corresponding bit from the interrupt status register is not cleared, and the module does not acknowledge a future idle request. Up to now _set_gpio_triggering() is also handling the wake-up enable register. According the TRM this should be in sync with the interrupt enable. Wakeup is still enabled by default, since the module would not wake from idle otherwise. The enabled_wakeup_gpios was introduced to remember an explicit _set_gpio_wakeup beyond a mask/unmask cycle. Calling the flag flag disabled_wakeup_gpios would spare the problem of initializing it, but feels very unnatural to read. There's a lot of description here, but it still fails to describe the problem that is being solved and the motiviation for this change. Wakeup functionality is completely untested, since the AM335x lacks a IRQWAKEN register. So in addtion to a better description of the problem, and the changes, this needs much broader testing, including on platforms with off-mode. Kevin -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
McSPI Problem on the DM3703
Linux OMAP Kernel community, I've ran into a bit of a pickle when using McSPI on the DM3703. Lets say that the spi-test (spidev/userspace) program can successfully generate CLK, SIMO, and CS signals on every SPI (1,2,3) channel you test it on, but when you go ahead and use a kernel module (like ENC28J60) through either SPI2 or SPI3, no clock is generated, but you can still see the SIMO and CS signals. The signs look great when you use SPI1. I'm using a 3.0.0 Kernel, and hope that someone can please help me out with this one. Thanks -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [net-next PATCH 1/1] drivers: net: davinci_cpdma: remove CRC bytes from skb added by CPDMA
From: Mugunthan V N mugunthan...@ti.com Date: Thu, 30 May 2013 11:52:01 +0530 Additional 4 bytes found in the skb is the CRC calculated by the CPDMA hardware, check the CRC bit in CPDMA status field of Descriptor and remove the CRC length from the skb. This extra 4 byte can be seen when capturing packets using tcpdump. This has been tested in TI816x platform. Signed-off-by: Mugunthan V N mugunthan...@ti.com Applied. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
McSPI Problem on the DM3703
Linux OMAP Kernel community, I've ran into a bit of a pickle when using McSPI on the DM3703. Lets say that the spi-test (spidev/userspace) program can successfully generate CLK, SIMO, and CS signals on every SPI (1,2,3) channel you test it on, but when you go ahead and use a kernel module (like ENC28J60) through either SPI2 or SPI3, no clock is generated, but you can still see the SIMO and CS signals. The signs look great when you use SPI1. I'm using a 3.0.0 Kernel, and hope that someone can please help me out with this one. Thanks -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
