On Wed, Nov 23, 2011 at 10:28 PM, Saravana Kannan
skan...@codeaurora.org wrote:
remoteproc would probably be the best fit since it's already used in the
code and people are used to discussing about it.
Guys you realize that 'amp' isn't really being used in the code
itself; this discussion boils
Hi,
On Tue, Nov 22, 2011 at 05:18:24PM -0800, Kevin Hilman wrote:
Currently the driver tries to save context in the suspend path, but
will cause an abort if the device is already runtime suspended. This
happens, for example, if MUSB loaded/compiled-in, in host mode, but no
USB devices are
Hi,
On Tue, Nov 22, 2011 at 05:18:24PM -0800, Kevin Hilman wrote:
Currently the driver tries to save context in the suspend path, but
will cause an abort if the device is already runtime suspended. This
happens, for example, if MUSB loaded/compiled-in, in host mode, but no
USB devices are
On Tue, Nov 22, 2011 at 6:54 PM, Tony Lindgren t...@atomide.com wrote:
Note that with device tree things get simpler for muxing as we can
get rid of the hardcoded grouping of pins in mux drivers. Instead of
hardcoded pingroups, the groups can be created dynamically based on
what the driver DT
On Wed, Nov 23, 2011 at 1:28 AM, Stephen Warren swar...@nvidia.com wrote:
Describing the HW doesn't necessarily
mean that each device needs to describe what pinmux pins it uses; one
could quite easily have the pinmux describe what settings the various
pins should have and which drivers will
Add some basic regulator support for the power pins, as needed
by the ST-Ericsson Snowball platform that powers up the SMSC911
chip using an external regulator.
Platforms that use regulators and the smsc911x and have no defined
regulator for the smsc911x and claim complete regulator
constraints
Hello,
On Friday, November 11, 2011 2:17 PM Joerg Roedel wrote:
Okay, seperate thread for this one.
If possible, I would like to be CCed: in the next mails in this topic.
For a last few months I've been working on DMA-mapping changes on ARM
architecture in order to add support for
Flush posted write between writing the ULPS enable bits and waiting for
the interrupt.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c
Flush posted write after setting the bit to send the BTA to ensure the
BTA is sent right away, as the code in dsi_vc_send_bta_sync() waits for
an interrupt caused indirectly by sending the BTA.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c |3 +++
1
First a few patches to flush posted writes, and then DSI patches related to the
DSI lane handling. I'm not sure if the lane handling is still as clean as it
could be, but at least it feels cleaner than currently.
Tested entering ULPS on display disable on blaze tablet, and it seems to work.
Flush posted write in _enable_lcd_out() and _enable_digit_out(). This
ensures the the lcd/digit bit is written before the code starts waiting
for interrupts about enabling/disabling the output.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dispc.c | 10
DSI driver currently counts used lanes and number of supported lanes by
using the number of data lanes (i.e. excluding clock lane). This patch
changes this to use the number of all lanes so that the following lane
config patches are cleaner.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
Parse the lane configuration from the device data into internal lane
config format. This will be used in the following patches to clean up
the lane handling.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 83 +
1
Use the new lane config in dsi_set_lane_config().
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 84 +++-
1 files changed, 40 insertions(+), 44 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c
Use the new lane config in dsi_get_lane_mask().
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 22 ++
1 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
Use the new lane config in dsi_cio_wait_tx_clk_esc_reset(). This also
extends the function to support 5 lanes on OMAP4, instead of 3 lanes.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 47 +++-
1 files changed, 18
Use the new lane config in dsi_cio_enable_lane_override(). The function
parameters are also slightly changed.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 85 +
1 files changed, 27 insertions(+), 58 deletions(-)
The current code always enters ULPS for 3 lanes. This is not right, as
there could be only 2 lanes used, and on OMAP4 we have 5 lanes.
Fix the code to put all used lanes into ULPS.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 16 +++-
1
We sometimes get timeout when disabling the DSI interface with video
mode. It looks like the disable will stall until the current frame has
been finished, and this can take multiple milliseconds.
wait_for_bit_change() currently uses a busyloop to wait for a bit to
change. This is used in multiple
ULPS cannot be entered if the DDR clk is enabled. Thus disable the DDR
clk before entering ULPS.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/video/omap2/dss/dsi.c
There's no longer need for the dsi_get_num_lanes_used function, so it
can be removed. The lane check in dsi_init_display() can be removed as
the validity of the config will be verified when parsing it.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
drivers/video/omap2/dss/dsi.c | 27
Hello,
The following series will add support for OMAP4 DMIC interface, and enable them
on sdp4430/Blaze boards.
Changes since v1:
- 192KHz rate support fixed (need to use different divider)
- Hold reference for dmic_fclk over the lifetime of the driver
- Removed the clkdiv callback, and replaced
To be able to get the memory resources by name from
the DMIC driver (for MPU and for DMA).
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
Add support for OMAP4 Digital Microphone interface.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/Kconfig |3 +
sound/soc/omap/Makefile|2 +
sound/soc/omap/omap-dmic.c | 509
sound/soc/omap/omap-dmic.h | 73
Add platform device registration for OMAP4 DMIC.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/devices.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
OMAP4 SDP/Blaze boards have digital microphones.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
sound/soc/omap/Kconfig |2 +
sound/soc/omap/sdp4430.c | 84 --
2 files changed, 75 insertions(+), 11 deletions(-)
diff --git
OMAP4 SDP/Blaze boards have onboard digital microphones.
Register the platform device for the dmic-codec to be
able to use the microphones.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/mach-omap2/board-4430sdp.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
1. Please replace RATE_IN_4430 = RATE_IN_44XX
2. Please replace CK_443X = CK_44XX
3. Please add initialization of field speculate in struct clk:
.speculate = omap2_clksel_speculate,
4. Set ops field to clkops_omap4_dflt_wait instead of
clkops_omap2_dflt in appropriate places
5.
In ancient times it was necessary to manually initialize the bus field of an
spi_driver to spi_bus_type. These days this is done in spi_driver_register(),
so we can drop the manual assignment.
The patch was generated using the following coccinelle semantic patch:
// smpl
@@
identifier _driver;
@@
On Thu, Nov 24, 2011 at 01:52:33PM +0100, Marek Szyprowski wrote:
In my DMA-mapping IOMMU integration I've used a dma_iommu_mapping structure,
which contains a pointer to iommu domain, a bitmap and a lock. Maybe we
should consider extending iommu domain with allocation bitmap (or other
On Wednesday 23 November 2011, Tony Lindgren wrote:
This one has the DSS patches left out, some patches sent to
stable, and based on -rc2.
Excellent, pulled into fixes now! Thanks for the quick update,
Arnd
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the
On Wednesday 23 November 2011, Tony Lindgren wrote:
Hi Arnd,
This one has been separated out from the rest of the fixes.
Pulled into the fixes branch now. I'll send out the branch
after testing it on tomorrow's linux-next.
If some of these need to go to stable, then Tomi should
do the
On Thu, Nov 24, 2011 at 03:54:46PM +0200, Peter Ujfalusi wrote:
+ /*
+ * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
+ * configuration. Fix the dmic clock divider for 192KHz
+ */
+ if (params_rate(params) == 192000) {
+ if (dmic-fclk_freq ==
* Arnd Bergmann a...@arndb.de [24 07:31]:
On Wednesday 23 November 2011, Tony Lindgren wrote:
Hi Arnd,
This one has been separated out from the rest of the fixes.
Pulled into the fixes branch now. I'll send out the branch
after testing it on tomorrow's linux-next.
If some of
Hi,
* Linus Walleij linus.wall...@linaro.org [24 01:29]:
On Tue, Nov 22, 2011 at 6:54 PM, Tony Lindgren t...@atomide.com wrote:
Note that with device tree things get simpler for muxing as we can
get rid of the hardcoded grouping of pins in mux drivers. Instead of
hardcoded pingroups,
On Tue, 18 Oct 2011, Kyle Manna wrote:
Add hwmod support to enable access to UART4 of the AM35xx series of
chips. The UART4 device referenced from the TRM will show up as ttyO3.
This was tested on an AM3505.
Signed-off-by: Kyle Manna kyle.ma...@fuel7.com
Thanks, provisionally queued for
On Thu, Nov 24, 2011 at 03:54:45PM +0200, Peter Ujfalusi wrote:
To be able to get the memory resources by name from
the DMIC driver (for MPU and for DMA).
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
There doesn't appear to be any direct dependency between the arch/arm
side and the
Hi,
On Thu, Nov 24, 2011 at 1:47 AM, Rabin Vincent ra...@rab.in wrote:
On Mon, Oct 24, 2011 at 20:15, ming@canonical.com wrote:
static struct platform_device* __init omap4_init_pmu(void)
{
int id = -1;
@@ -420,6 +472,10 @@ static struct platform_device* __init
Changes in dmtimer framework have introduced scheduling-while-atomic
and other lock state BUGs, these are related to the usage of clk_get
(internal path holds a mutex_lock) while holding a spin_lock_irqsave.
The other inconsistent lock state BUGs are caused when calling
omap_dm_timer_request* on
omap_dm_timer_request* holds a spin_lock_irqsave while inner routines call
clk_get_sys which holds a mutex_lock, given that mutex can be put to sleep
a BUG message is triggered. This occurs in 2 ocassions.
1. When the fck is gotten at the beginning of omap_dm_timer_prepare by using
clk_get
omap_dm_timer_request and omap_dm_timer_request_specific have almost
the same code except for a conditional check and the parameters they
receive.
omap_dm_timer_request_specific can be sent a -1 parameter to contain
the behavior of omap_dm_timer_request and thus get rid of some lines
of code.
Hi,
On Thu, Nov 17, 2011 at 21:58:23, Bedia, Vaibhav wrote:
TI processors in TI81x and AM33x family work with PMICs like
TPS65910/1 which are not part of the TWL series. These processors
also do not have a voltage controller/processor module.
In order to invoke the normal regulator calls
42 matches
Mail list logo
