Re: [PATCH v7 RESEND] ARM: omap: edma: add suspend suspend/resume hooks
On Friday 22 August 2014 01:16 PM, Dave Gerlach wrote:
From: Daniel Mack zon...@gmail.com
This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.
All information can be reconstructed by already known runtime
information.
As we now use some functions that were previously only used from __init
context, annotations had to be dropped.
[n...@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Daniel Mack zon...@gmail.com
Tested-by: Joel Fernandes jo...@ti.com
Acked-by: Joel Fernandes jo...@ti.com
[d-gerl...@ti.com: updated to remove queue_tc_mapping use]
Signed-off-by: Dave Gerlach d-gerl...@ti.com
---
Needed for am335x suspend, but never got picked up. Previously
sent here: http://marc.info/?l=linux-arm-kernelm=138556067416051w=2
arch/arm/common/edma.c | 86
--
1 file changed, 84 insertions(+), 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 8809917..ece1e3d 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -244,6 +244,8 @@ struct edma {
/* list of channels with no even trigger; terminated by -1 */
const s8*noevent;
+ struct edma_soc_info *info;
+
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -295,7 +297,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
~(0x7 bit), queue_no bit);
}
-static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+static void assign_priority_to_queue(unsigned ctlr, int queue_no,
int priority)
{
int bit = queue_no * 4;
@@ -314,7 +316,7 @@ static void __init assign_priority_to_queue(unsigned
ctlr, int queue_no,
* included in that particular EDMA variant (Eg : dm646x)
*
*/
-static void __init map_dmach_param(unsigned ctlr)
+static void map_dmach_param(unsigned ctlr)
{
int i;
for (i = 0; i EDMA_MAX_DMACH; i++)
@@ -1791,15 +1793,95 @@ static int edma_probe(struct platform_device *pdev)
edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
edma_write_array(j, EDMA_QRAE, i, 0x0);
}
+ edma_cc[j]-info = info[j];
arch_num_cc++;
}
return 0;
}
+static int edma_pm_suspend(struct device *dev)
+{
+ int j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
The driver currently does a pm_runtime_get_sync() once during probe. And
does not do a put(). So this should actually be not required. In fact
looks like this additional get() call will prevent the clock from
getting disabled which is probably not what you intend.
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *ecc = edma_cc[j];
+
+ disable_irq(ecc-irq_res_start);
+ disable_irq(ecc-irq_res_end);
Do we really need to disable these irqs?
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int edma_pm_resume(struct device *dev)
+{
+ int i, j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *cc = edma_cc[j];
+
+ s8 (*queue_priority_mapping)[2];
+
+ queue_priority_mapping = cc-info-queue_priority_mapping;
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(j,
+ queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
+
+ /*
+ * Map the channel to param entry if channel mapping logic
+ * exist
+ */
+ if (edma_read(j, EDMA_CCCFG) CHMAP_EXIST)
+ map_dmach_param(j);
+
+ for (i = 0; i cc-num_channels; i++) {
+ if (test_bit(i, cc-edma_inuse)) {
+ /* ensure access through shadow region 0 */
+ edma_or_array2(j, EDMA_DRAE, 0, i 5,
+BIT(i 0x1f));
+
+ setup_dma_interrupt(i,
+ cc-intr_data[i].callback,
+ cc-intr_data[i].data);
+ }
+ }
+
+ enable_irq(cc-irq_res_start);
+
Re: [PATCH v2] ARM: OMAP2+: fix gpmc_cs_remap: re-allocating chip-select address space based on DT
On 08/25/2014 09:50 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [140825 04:27]:
From: Pekon Gupta pe...@ti.com
Each GPMC chip-select needs to be configured for (base-address,CS-size) so
that
GPMC understands the address-space allocated to device connected externally.
These chip-select configurations (base-address, CS-size) follow some basic
mapping rules like:
- The CS size is programmable from 256 MBytes to 16 MBytes (must be a power
of 2)
and is defined by the mask field. Attached memory smaller than the
programmed
CS region size is accessed through the entire CS region (aliasing).
- The programmed 'base-address' must be aligned to the 'CS-size' boundary and
be a power of 2.
- Valid CS-size values are {256MB(max), 128MB, 64MB, 32MB and 16MB (min)}
Any intermediate values creates holes in the chip-select memory-map.
This patch adds above checks in gpmc_cs_remap() so that any invalid value
passed by DT reg property can be filtered before actually allocating the
address space.
There's now an issue here where it mixes up the configured CS
size and the configured device IO size. With this patch GPMC based
Ethernet devices trigger warning at arch/arm/mach-omap2/gpmc.c:556
as we have the minimal GPMC CS range of 16MB with the smsc IO size
being either 0xf or 0xff depending on the model.
So that check should be done on the CS size, not the device IO size.
Good catch.
This patch does not address the following issues from long term point of view
- The remap should be done not only for NOR/Ethernet devices but for all the
GPMC child nodes.
- The base address/size should be taken from the reg property
of the GPMC node and not of the child node as done in this patch.
Please drop this patch. I will include this in the clean up series which
I will post once ready. Currently I'm caught up with bug fixing and settling on
a stable version of GPMC which works on all boards that I have.
cheers,
-roger
Regards,
Tony
[rog...@ti.com] typo and print message fixes.
Signed-off-by: Pekon Gupta pe...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/gpmc.c | 51
+-
1 file changed, 37 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc1338..793f3a9 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -516,31 +516,54 @@ static int gpmc_cs_delete_mem(int cs)
* gpmc_cs_remap - remaps a chip-select physical base address
* @cs: chip-select to remap
* @base: physical base address to re-map chip-select to
+ * @size: size of the chip select map
*
* Re-maps a chip-select to a new physical base address specified by
* base. Returns 0 on success and appropriate negative error code
- * on failure.
+ * on failure. size of the map must be either 16M, 32M, 64M or 128M.
*/
-static int gpmc_cs_remap(int cs, u32 base)
+static int gpmc_cs_remap(int cs, u32 base, u32 size)
{
int ret;
-u32 old_base, size;
if (cs gpmc_cs_num) {
pr_err(%s: requested chip-select is disabled\n, __func__);
return -ENODEV;
}
-/*
- * Make sure we ignore any device offsets from the GPMC partition
- * allocated for the chip select and that the new base confirms
- * to the GPMC 16MB minimum granularity.
- */
-base = ~(SZ_16M - 1);
-
-gpmc_cs_get_memconf(cs, old_base, size);
-if (base == old_base)
-return 0;
+/* Align size to meet SoC limitations */
+if (size SZ_256M) {
+pr_err(%s: CS memory map 256MB not supported\n, __func__);
+return -ENODEV;
+} else if (size SZ_128M) {
+WARN((size != SZ_256M), %s: cs=%d: allocating 256MB\n,
+ __func__, cs);
+size = SZ_256M;
+} else if (size SZ_64M) {
+WARN((size != SZ_128M), %s: cs=%d: allocating 128MB\n,
+ __func__, cs);
+size = SZ_128M;
+} else if (size SZ_32M) {
+WARN((size != SZ_64M), %s: cs=%d: allocating 64MB\n,
+ __func__, cs);
+size = SZ_64M;
+} else if (size SZ_16M) {
+WARN((size != SZ_32M), %s: cs=%d: allocating 32MB\n,
+ __func__, cs);
+size = SZ_32M;
+} else {
+WARN((size != SZ_16M), %s: cs=%d: allocating 16MB\n,
+ __func__, cs);
+size = SZ_16M;
+}
+
+/* base address should be aligned with address-space size */
+if (base (size - 1)) {
+pr_err(%s: cs base-addr: %x should be aligned to cs size: %x,
+ __func__, base, size);
+return -EINVAL;
+}
+
gpmc_cs_disable_mem(cs);
ret = gpmc_cs_delete_mem(cs);
if (ret 0)
@@ -1551,7 +1574,7 @@ static int gpmc_probe_generic_child(struct
Re: [PATCH v7 RESEND] ARM: omap: edma: add suspend suspend/resume hooks
Hi,
On 08/26/2014 08:36 AM, Sekhar Nori wrote:
On Friday 22 August 2014 01:16 PM, Dave Gerlach wrote:
Thanks for pushing that forward!
+static int edma_pm_suspend(struct device *dev)
+{
+int j, r;
+
+r = pm_runtime_get_sync(dev);
+if (r 0) {
+dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+return r;
+}
The driver currently does a pm_runtime_get_sync() once during probe. And
does not do a put(). So this should actually be not required. In fact
looks like this additional get() call will prevent the clock from
getting disabled which is probably not what you intend.
Well, the pm runtime is put again ...
+
+for (j = 0; j arch_num_cc; j++) {
+struct edma *ecc = edma_cc[j];
+
+disable_irq(ecc-irq_res_start);
+disable_irq(ecc-irq_res_end);
Do we really need to disable these irqs?
+}
+
+pm_runtime_put_sync(dev);
... here, so it's in sync and should be fine.
I was also sure than when I wrote the code, disabling the interrupts
during suspend was necessary, and even the only thing that has to be
done at suspend time. Now that I address this again, my tests show that
in can in fact be omitted.
So I'll send a v9 now that has no edma_pm_suspend() at all anymore.
+static const struct dev_pm_ops edma_pm_ops = {
+.suspend_late = edma_pm_suspend,
+.resume_early = edma_pm_resume,
+};
You can use SET_LATE_SYSTEM_SLEEP_PM_OPS() as some other DMA drivers are
doing too.
Sure, why not.
Thanks,
Daniel
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[PATCH] ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated.
Fixed by using proper divider clock types for the clock nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
Reported-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/boot/dts/omap54xx-clocks.dtsi | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi
b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index e67a23b..58c2746 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -367,10 +367,12 @@
l3_iclk_div: l3_iclk_div {
#clock-cells = 0;
- compatible = fixed-factor-clock;
+ compatible = ti,divider-clock;
+ ti,max-div = 2;
+ ti,bit-shift = 4;
+ reg = 0x100;
clocks = dpll_core_h12x2_ck;
- clock-mult = 1;
- clock-div = 1;
+ ti,index-power-of-two;
};
gpu_l3_iclk: gpu_l3_iclk {
@@ -383,10 +385,12 @@
l4_root_clk_div: l4_root_clk_div {
#clock-cells = 0;
- compatible = fixed-factor-clock;
+ compatible = ti,divider-clock;
+ ti,max-div = 2;
+ ti,bit-shift = 8;
+ reg = 0x100;
clocks = l3_iclk_div;
- clock-mult = 1;
- clock-div = 1;
+ ti,index-power-of-two;
};
slimbus1_slimbus_clk: slimbus1_slimbus_clk {
--
1.7.9.5
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[PATCH v9] ARM: omap: edma: add suspend resume hook
This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.
All information can be reconstructed by already known runtime
information.
As we now use some functions that were previously only used from __init
context, annotations had to be dropped.
[n...@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: Nishanth Menon n...@ti.com
Signed-off-by: Daniel Mack zon...@gmail.com
Tested-by: Joel Fernandes jo...@ti.com
Acked-by: Joel Fernandes jo...@ti.com
---
Changes from v8:
* Drop the edma_suspend hook altogether. Even though back then
when I wrote the code I was sure disabling the interrupts
during suspend is necessary, tests now show it in fact isn't.
My test setup still works if that code is omitted.
* Use SET_LATE_SYSTEM_SLEEP_PM_OPS in the dev_pm_ops
declaration.
Thanks to Sekhar for pointing out the above.
arch/arm/common/edma.c | 60 --
1 file changed, 58 insertions(+), 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 485be42..c623dd0 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -244,6 +244,8 @@ struct edma {
/* list of channels with no even trigger; terminated by -1 */
const s8*noevent;
+ struct edma_soc_info *info;
+
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -295,7 +297,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
~(0x7 bit), queue_no bit);
}
-static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
+static void assign_priority_to_queue(unsigned ctlr, int queue_no,
int priority)
{
int bit = queue_no * 4;
@@ -314,7 +316,7 @@ static void __init assign_priority_to_queue(unsigned ctlr,
int queue_no,
* included in that particular EDMA variant (Eg : dm646x)
*
*/
-static void __init map_dmach_param(unsigned ctlr)
+static void map_dmach_param(unsigned ctlr)
{
int i;
for (i = 0; i EDMA_MAX_DMACH; i++)
@@ -1762,15 +1764,69 @@ static int edma_probe(struct platform_device *pdev)
edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
edma_write_array(j, EDMA_QRAE, i, 0x0);
}
+ edma_cc[j]-info = info[j];
arch_num_cc++;
}
return 0;
}
+static int edma_pm_resume(struct device *dev)
+{
+ int i, j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *cc = edma_cc[j];
+
+ s8 (*queue_priority_mapping)[2];
+
+ queue_priority_mapping = cc-info-queue_priority_mapping;
+
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(j,
+queue_priority_mapping[i][0],
+queue_priority_mapping[i][1]);
+
+ /*
+* Map the channel to param entry if channel mapping logic
+* exist
+*/
+ if (edma_read(j, EDMA_CCCFG) CHMAP_EXIST)
+ map_dmach_param(j);
+
+ for (i = 0; i cc-num_channels; i++) {
+ if (test_bit(i, cc-edma_inuse)) {
+ /* ensure access through shadow region 0 */
+ edma_or_array2(j, EDMA_DRAE, 0, i 5,
+ BIT(i 0x1f));
+
+ setup_dma_interrupt(i,
+ cc-intr_data[i].callback,
+ cc-intr_data[i].data);
+ }
+ }
+ }
+
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops edma_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
+};
+
static struct platform_driver edma_driver = {
.driver = {
.name = edma,
+ .pm = edma_pm_ops,
.of_match_table = edma_of_ids,
},
.probe = edma_probe,
--
2.1.0
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Re: [PATCH v7 RESEND] ARM: omap: edma: add suspend suspend/resume hooks
On Tuesday 26 August 2014 02:16 PM, Daniel Mack wrote:
Hi,
On 08/26/2014 08:36 AM, Sekhar Nori wrote:
On Friday 22 August 2014 01:16 PM, Dave Gerlach wrote:
Thanks for pushing that forward!
+static int edma_pm_suspend(struct device *dev)
+{
+ int j, r;
+
+ r = pm_runtime_get_sync(dev);
+ if (r 0) {
+ dev_err(dev, %s: get_sync returned %d\n, __func__, r);
+ return r;
+ }
The driver currently does a pm_runtime_get_sync() once during probe. And
does not do a put(). So this should actually be not required. In fact
looks like this additional get() call will prevent the clock from
getting disabled which is probably not what you intend.
Well, the pm runtime is put again ...
+
+ for (j = 0; j arch_num_cc; j++) {
+ struct edma *ecc = edma_cc[j];
+
+ disable_irq(ecc-irq_res_start);
+ disable_irq(ecc-irq_res_end);
Do we really need to disable these irqs?
+ }
+
+ pm_runtime_put_sync(dev);
... here, so it's in sync and should be fine.
May be I am missing something but because of the pm_runtime_get_sync()
in probe() usage count is already 1 when suspend() is called. The
pm_runtime_get_sync() in this function makes it 2 and therefore
pm_runtime_put_sync() returns immediately because the usage count is
greater that 0 after decrementing by 1. That means the module's clocks
is not disabled after suspend() is finished.
I was also sure than when I wrote the code, disabling the interrupts
during suspend was necessary, and even the only thing that has to be
done at suspend time. Now that I address this again, my tests show that
in can in fact be omitted.
Thanks!
Regards,
Sekhar
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Re: [PATCH] ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
On 26/08/14 11:51, Tero Kristo wrote: Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated. Fixed by using proper divider clock types for the clock nodes. Signed-off-by: Tero Kristo t-kri...@ti.com Reported-by: Tomi Valkeinen tomi.valkei...@ti.com --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) Tested-by: Tomi Valkeinen tomi.valkei...@ti.com Tomi signature.asc Description: OpenPGP digital signature
[PATCH v2 00/26] genirq: fix use of irq_find_mapping outside of legal RCU context
A number of irqchip drivers are directly calling irq_find_mapping,
which may use a rcu_read_lock call when walking the radix tree.
Turns out that if you hit that point with CONFIG_PROVE_RCU enabled,
the kernel will shout at you, as using RCU in this context may be
illegal (specially if coming from the idle state, where RCU would be
in a quiescent state).
A possible fix would be to wrap calls to irq_find_mapping into a
RCU_NONIDLE macro, but that really looks ugly.
This patch series introduce another generic IRQ entry point
(handle_domain_irq), which has the exact same behaviour as handle_IRQ
(as defined on arm, arm64 and openrisc), except that it also takes a
irq_domain pointer. This allows the logical IRQ lookup to be done
inside the irq_{enter,exit} section, which contains a
rcu_irq_{enter,exit}, making it safe.
A number of irqchips are then converted to this new entry point. I've
converted all the direct users of irq_find_mapping, except for the
cases where it was used as a chained handler (chained_irq_{enter,exit}
makes it safe). Users of irq_linear_revmap are safe as well. I've
given it some light testing on arm64.
The series is also available in my tree:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
handle_domain_irq
From v1 [1]:
- Made handle_domain_irq a generic function
- Added OpenRISC to the list of affected architectures
- Converted more interrupt controllers
- Rebased on v3.17-rc1
[1]: https://lkml.org/lkml/2014/7/8/381
Marc Zyngier (26):
genirq: add irq_domain-aware core IRQ handler
arm64: convert handle_IRQ to use __handle_domain_irq
ARM: convert handle_IRQ to use __handle_domain_irq
openrisc: convert handle_IRQ to use __handle_domain_irq
irqchip: GIC: convert to handle_domain_irq
irqchip: armada-370-xp: convert to handle_domain_irq
irqchip: clps711x: convert to handle_domain_irq
irqchip: mmp: convert to handle_domain_irq
irqchip: mxs: convert to handle_domain_irq
irqchip: orion: convert to handle_domain_irq
irqchip: s3c24xx: convert to handle_domain_irq
irqchip: sirfsoc: convert to handle_domain_irq
irqchip: sun4i: convert to handle_domain_irq
irqchip: versatile-fpga: convert to handle_domain_irq
irqchip: vic: convert to handle_domain_irq
irqchip: vt8500: convert to handle_domain_irq
irqchip: zevio: convert to handle_domain_irq
irqchip: GICv3: convert to handle_domain_irq
irqchip: atmel-aic: convert to handle_domain_irq
irqchip: atmel-aic5: convert to handle_domain_irq
irqchip: or1k-pic: convert to handle_domain_irq
ARM: imx: avic: convert to handle_domain_irq
ARM: imx: tzic: convert to handle_domain_irq
ARM: omap2: irq: convert to handle_domain_irq
arm64: get rid of handle_IRQ
openrisc: get rid of handle_IRQ
arch/arm/Kconfig | 1 +
arch/arm/kernel/irq.c| 19 +---
arch/arm/mach-imx/avic.c | 2 +-
arch/arm/mach-imx/tzic.c | 3 +--
arch/arm/mach-omap2/irq.c| 3 +--
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/hardirq.h | 2 --
arch/arm64/kernel/irq.c | 27 ---
arch/openrisc/Kconfig| 1 +
arch/openrisc/include/asm/irq.h | 1 -
arch/openrisc/kernel/irq.c | 12 ---
drivers/irqchip/irq-armada-370-xp.c | 19
drivers/irqchip/irq-atmel-aic.c | 4 +---
drivers/irqchip/irq-atmel-aic5.c | 4 +---
drivers/irqchip/irq-clps711x.c | 18 ++--
drivers/irqchip/irq-gic-v3.c | 13 ++-
drivers/irqchip/irq-gic.c| 3 +--
drivers/irqchip/irq-mmp.c| 10 -
drivers/irqchip/irq-mxs.c| 3 +--
drivers/irqchip/irq-or1k-pic.c | 4 ++--
drivers/irqchip/irq-orion.c | 5 ++---
drivers/irqchip/irq-s3c24xx.c| 4 +---
drivers/irqchip/irq-sirfsoc.c| 6 ++
drivers/irqchip/irq-sun4i.c | 5 ++---
drivers/irqchip/irq-versatile-fpga.c | 2 +-
drivers/irqchip/irq-vic.c| 2 +-
drivers/irqchip/irq-vt8500.c | 5 ++---
drivers/irqchip/irq-zevio.c | 3 +--
include/linux/irqdesc.h | 19
kernel/irq/Kconfig | 3 +++
kernel/irq/irqdesc.c | 42
31 files changed, 116 insertions(+), 130 deletions(-)
--
2.0.4
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[PATCH v2 03/26] ARM: convert handle_IRQ to use __handle_domain_irq
In order to limit code duplication, convert the architecture specific
handle_IRQ to use the generic __handle_domain_irq function.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/Kconfig | 1 +
arch/arm/kernel/irq.c | 19 +--
2 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775..5918d40 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,6 +24,7 @@ config ARM
select GENERIC_SMP_IDLE_THREAD
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
+ select HANDLE_DOMAIN_IRQ
select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL if (AEABI !OABI_COMPAT)
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c42576..0509d07 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -65,24 +65,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
*/
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- /*
-* Some hardware gives randomly wrong interrupts. Rather
-* than crashing, do something sensible.
-*/
- if (unlikely(irq = nr_irqs)) {
- if (printk_ratelimit())
- printk(KERN_WARNING Bad IRQ%u\n, irq);
- ack_bad_irq(irq);
- } else {
- generic_handle_irq(irq);
- }
-
- irq_exit();
- set_irq_regs(old_regs);
+ __handle_domain_irq(NULL, irq, false, regs);
}
/*
--
2.0.4
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[PATCH v2 13/26] irqchip: sun4i: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-sun4i.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
index 6fcef4a..64155b6 100644
--- a/drivers/irqchip/irq-sun4i.c
+++ b/drivers/irqchip/irq-sun4i.c
@@ -136,7 +136,7 @@ IRQCHIP_DECLARE(allwinner_sun4i_ic,
allwinner,sun4i-a10-ic, sun4i_of_init);
static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
{
- u32 irq, hwirq;
+ u32 hwirq;
/*
* hwirq == 0 can mean one of 3 things:
@@ -154,8 +154,7 @@ static void __exception_irq_entry sun4i_handle_irq(struct
pt_regs *regs)
return;
do {
- irq = irq_find_mapping(sun4i_irq_domain, hwirq);
- handle_IRQ(irq, regs);
+ handle_domain_irq(sun4i_irq_domain, hwirq, regs);
hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) 2;
} while (hwirq != 0);
}
--
2.0.4
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[PATCH v2 26/26] openrisc: get rid of handle_IRQ
The openrisc irqchip driver has been converted to handle_domain_irq,
making it possible to remove the handle_IRQ stub entierely.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/openrisc/include/asm/irq.h | 1 -
arch/openrisc/kernel/irq.c | 5 -
2 files changed, 6 deletions(-)
diff --git a/arch/openrisc/include/asm/irq.h b/arch/openrisc/include/asm/irq.h
index b84634c..d9eee0a 100644
--- a/arch/openrisc/include/asm/irq.h
+++ b/arch/openrisc/include/asm/irq.h
@@ -24,7 +24,6 @@
#define NO_IRQ (-1)
-void handle_IRQ(unsigned int, struct pt_regs *);
extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
#endif /* __ASM_OPENRISC_IRQ_H__ */
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index e9aaf28..35e478a 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -48,11 +48,6 @@ void __init set_handle_irq(void (*handle_irq)(struct pt_regs
*))
handle_arch_irq = handle_irq;
}
-void handle_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- __handle_domain_irq(NULL, irq, false, regs);
-}
-
void __irq_entry do_IRQ(struct pt_regs *regs)
{
handle_arch_irq(regs);
--
2.0.4
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[PATCH v2 25/26] arm64: get rid of handle_IRQ
All the arm64 irqchip drivers have been converted to handle_domain_irq,
making it possible to remove the handle_IRQ stub entierely.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/include/asm/hardirq.h | 2 --
arch/arm64/kernel/irq.c | 11 ---
2 files changed, 13 deletions(-)
diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index 0be6782..e8a3268 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -47,8 +47,6 @@ static inline void ack_bad_irq(unsigned int irq)
irq_err_count++;
}
-extern void handle_IRQ(unsigned int, struct pt_regs *);
-
/*
* No arch-specific IRQ flags.
*/
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 2c0e2a7..67ca197 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -40,17 +40,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
return 0;
}
-/*
- * handle_IRQ handles all hardware IRQ's. Decoded IRQs should
- * not come via this function. Instead, they should provide their
- * own 'handler'. Used by platform code implementing C-based 1st
- * level decoding.
- */
-void handle_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- __handle_domain_irq(NULL, irq, false, regs);
-}
-
void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
{
if (handle_arch_irq)
--
2.0.4
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[PATCH v2 21/26] irqchip: or1k-pic: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/irq-or1k-pic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c index 17ff033..e93d079 100644 --- a/drivers/irqchip/irq-or1k-pic.c +++ b/drivers/irqchip/irq-or1k-pic.c @@ -113,7 +113,7 @@ static inline int pic_get_irq(int first) else hwirq = hwirq + first - 1; - return irq_find_mapping(root_domain, hwirq); + return hwirq; } static void or1k_pic_handle_irq(struct pt_regs *regs) @@ -121,7 +121,7 @@ static void or1k_pic_handle_irq(struct pt_regs *regs) int irq = -1; while ((irq = pic_get_irq(irq + 1)) != NO_IRQ) - handle_IRQ(irq, regs); + handle_domain_irq(root_domain, irq, regs); } static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 19/26] irqchip: atmel-aic: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/irq-atmel-aic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c index a82869e..9a2cf3c 100644 --- a/drivers/irqchip/irq-atmel-aic.c +++ b/drivers/irqchip/irq-atmel-aic.c @@ -68,12 +68,10 @@ aic_handle(struct pt_regs *regs) irqnr = irq_reg_readl(gc-reg_base + AT91_AIC_IVR); irqstat = irq_reg_readl(gc-reg_base + AT91_AIC_ISR); - irqnr = irq_find_mapping(aic_domain, irqnr); - if (!irqstat) irq_reg_writel(0, gc-reg_base + AT91_AIC_EOICR); else - handle_IRQ(irqnr, regs); + handle_domain_irq(aic_domain, irqnr, regs); } static int aic_retrigger(struct irq_data *d) -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 22/26] ARM: imx: avic: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-imx/avic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index 24b103c..1a89323 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -144,7 +144,7 @@ static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) if (nivector == 0x) break; - handle_IRQ(irq_find_mapping(domain, nivector), regs); + handle_domain_irq(domain, nivector, regs); } while (1); } -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 23/26] ARM: imx: tzic: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-imx/tzic.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 1d4f384..4de65ee 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -141,8 +141,7 @@ static void __exception_irq_entry tzic_handle_irq(struct
pt_regs *regs)
while (stat) {
handled = 1;
irqofs = fls(stat) - 1;
- handle_IRQ(irq_find_mapping(domain,
- irqofs + i * 32), regs);
+ handle_domain_irq(domain, irqofs + i * 32,
regs);
stat = ~(1 irqofs);
}
}
--
2.0.4
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[PATCH v2 20/26] irqchip: atmel-aic5: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/irq-atmel-aic5.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index edb2270..04fe2c1 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -78,12 +78,10 @@ aic5_handle(struct pt_regs *regs) irqnr = irq_reg_readl(gc-reg_base + AT91_AIC5_IVR); irqstat = irq_reg_readl(gc-reg_base + AT91_AIC5_ISR); - irqnr = irq_find_mapping(aic5_domain, irqnr); - if (!irqstat) irq_reg_writel(0, gc-reg_base + AT91_AIC5_EOICR); else - handle_IRQ(irqnr, regs); + handle_domain_irq(aic5_domain, irqnr, regs); } static void aic5_mask(struct irq_data *d) -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 18/26] irqchip: GICv3: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic-v3.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 57eaa5a..9e31449 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -274,14 +274,13 @@ static asmlinkage void __exception_irq_entry
gic_handle_irq(struct pt_regs *regs
irqnr = gic_read_iar();
if (likely(irqnr 15 irqnr 1020)) {
- u64 irq = irq_find_mapping(gic_data.domain, irqnr);
- if (likely(irq)) {
- handle_IRQ(irq, regs);
- continue;
+ int err;
+ err = handle_domain_irq(gic_data.domain, irqnr, regs);
+ if (err) {
+ WARN_ONCE(true, Unexpected SPI received!\n);
+ gic_write_eoir(irqnr);
}
-
- WARN_ONCE(true, Unexpected SPI received!\n);
- gic_write_eoir(irqnr);
+ continue;
}
if (irqnr 16) {
gic_write_eoir(irqnr);
--
2.0.4
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[PATCH v2 24/26] ARM: omap2: irq: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-omap2/irq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 35b8590..a62ba5a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -248,8 +248,7 @@ out:
irqnr = ACTIVEIRQ_MASK;
if (irqnr) {
- irqnr = irq_find_mapping(domain, irqnr);
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(domain, irqnr, regs);
handled_irq = 1;
}
} while (irqnr);
--
2.0.4
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[PATCH v2 17/26] irqchip: zevio: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-zevio.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-zevio.c b/drivers/irqchip/irq-zevio.c
index ceb3a43..e4ef74e 100644
--- a/drivers/irqchip/irq-zevio.c
+++ b/drivers/irqchip/irq-zevio.c
@@ -56,8 +56,7 @@ static void __exception_irq_entry zevio_handle_irq(struct
pt_regs *regs)
while (readl(zevio_irq_io + IO_STATUS)) {
irqnr = readl(zevio_irq_io + IO_CURRENT);
- irqnr = irq_find_mapping(zevio_irq_domain, irqnr);
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(zevio_irq_domain, irqnr, regs);
};
}
--
2.0.4
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[PATCH v2 11/26] irqchip: s3c24xx: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-s3c24xx.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
index 78a6acc..c8d373f 100644
--- a/drivers/irqchip/irq-s3c24xx.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -339,7 +339,6 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc
*intc,
{
int pnd;
int offset;
- int irq;
pnd = __raw_readl(intc-reg_intpnd);
if (!pnd)
@@ -365,8 +364,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc
*intc,
if (!(pnd (1 offset)))
offset = __ffs(pnd);
- irq = irq_find_mapping(intc-domain, intc_offset + offset);
- handle_IRQ(irq, regs);
+ handle_domain_irq(intc-domain, intc_offset + offset, regs);
return true;
}
--
2.0.4
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[PATCH v2 12/26] irqchip: sirfsoc: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-sirfsoc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
index 5e54f6d..a469355 100644
--- a/drivers/irqchip/irq-sirfsoc.c
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -50,12 +50,10 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int
irq_start, unsigned int num)
static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
void __iomem *base = sirfsoc_irqdomain-host_data;
- u32 irqstat, irqnr;
+ u32 irqstat;
irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
- irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat 0xff);
-
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(sirfsoc_irqdomain, irqstat 0xff, regs);
}
static int __init sirfsoc_irq_init(struct device_node *np,
--
2.0.4
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[PATCH v2 09/26] irqchip: mxs: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- drivers/irqchip/irq-mxs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c index 4044ff2..e4acf1e 100644 --- a/drivers/irqchip/irq-mxs.c +++ b/drivers/irqchip/irq-mxs.c @@ -78,8 +78,7 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET); __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); - irqnr = irq_find_mapping(icoll_domain, irqnr); - handle_IRQ(irqnr, regs); + handle_domain_irq(icoll_domain, irqnr, regs); } static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 10/26] irqchip: orion: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-orion.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
index 34d18b4..ad0c0f6 100644
--- a/drivers/irqchip/irq-orion.c
+++ b/drivers/irqchip/irq-orion.c
@@ -43,9 +43,8 @@ __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
gc-mask_cache;
while (stat) {
u32 hwirq = __fls(stat);
- u32 irq = irq_find_mapping(orion_irq_domain,
- gc-irq_base + hwirq);
- handle_IRQ(irq, regs);
+ handle_domain_irq(orion_irq_domain,
+ gc-irq_base + hwirq, regs);
stat = ~(1 hwirq);
}
}
--
2.0.4
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[PATCH v2 14/26] irqchip: versatile-fpga: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-versatile-fpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-versatile-fpga.c
b/drivers/irqchip/irq-versatile-fpga.c
index ccf5854..1ab4517 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -96,7 +96,7 @@ static int handle_one_fpga(struct fpga_irq_data *f, struct
pt_regs *regs)
while ((status = readl(f-base + IRQ_STATUS))) {
irq = ffs(status) - 1;
- handle_IRQ(irq_find_mapping(f-domain, irq), regs);
+ handle_domain_irq(f-domain, irq, regs);
handled = 1;
}
--
2.0.4
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[PATCH v2 15/26] irqchip: vic: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-vic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 7d35287..54089de 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -219,7 +219,7 @@ static int handle_one_vic(struct vic_device *vic, struct
pt_regs *regs)
while ((stat = readl_relaxed(vic-base + VIC_IRQ_STATUS))) {
irq = ffs(stat) - 1;
- handle_IRQ(irq_find_mapping(vic-domain, irq), regs);
+ handle_domain_irq(vic-domain, irq, regs);
handled = 1;
}
--
2.0.4
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[PATCH v2 08/26] irqchip: mmp: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-mmp.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 1c3e2c9..c0da57b 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -196,26 +196,24 @@ static struct mmp_intc_conf mmp2_conf = {
static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
{
- int irq, hwirq;
+ int hwirq;
hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
if (!(hwirq SEL_INT_PENDING))
return;
hwirq = SEL_INT_NUM_MASK;
- irq = irq_find_mapping(icu_data[0].domain, hwirq);
- handle_IRQ(irq, regs);
+ handle_domain_irq(icu_data[0].domain, hwirq, regs);
}
static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
{
- int irq, hwirq;
+ int hwirq;
hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
if (!(hwirq SEL_INT_PENDING))
return;
hwirq = SEL_INT_NUM_MASK;
- irq = irq_find_mapping(icu_data[0].domain, hwirq);
- handle_IRQ(irq, regs);
+ handle_domain_irq(icu_data[0].domain, hwirq, regs);
}
/* MMP (ARMv5) */
--
2.0.4
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[PATCH v2 16/26] irqchip: vt8500: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-vt8500.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-vt8500.c b/drivers/irqchip/irq-vt8500.c
index eb6e91e..b7af816 100644
--- a/drivers/irqchip/irq-vt8500.c
+++ b/drivers/irqchip/irq-vt8500.c
@@ -181,7 +181,7 @@ static struct irq_domain_ops vt8500_irq_domain_ops = {
static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
{
u32 stat, i;
- int irqnr, virq;
+ int irqnr;
void __iomem *base;
/* Loop through each active controller */
@@ -198,8 +198,7 @@ static void __exception_irq_entry vt8500_handle_irq(struct
pt_regs *regs)
continue;
}
- virq = irq_find_mapping(intc[i].domain, irqnr);
- handle_IRQ(virq, regs);
+ handle_domain_irq(intc[i].domain, irqnr, regs);
}
}
--
2.0.4
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[PATCH v2 05/26] irqchip: GIC: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 4b959e6..480bae8 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -270,8 +270,7 @@ static void __exception_irq_entry gic_handle_irq(struct
pt_regs *regs)
irqnr = irqstat GICC_IAR_INT_ID_MASK;
if (likely(irqnr 15 irqnr 1021)) {
- irqnr = irq_find_mapping(gic-domain, irqnr);
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(gic-domain, irqnr, regs);
continue;
}
if (irqnr 16) {
--
2.0.4
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[PATCH v2 04/26] openrisc: convert handle_IRQ to use __handle_domain_irq
In order to limit code duplication, convert the architecture specific
handle_IRQ to use the generic __handle_domain_irq function.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/openrisc/Kconfig | 1 +
arch/openrisc/kernel/irq.c | 9 +
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 88e8336..e5a693b 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -8,6 +8,7 @@ config OPENRISC
select OF
select OF_EARLY_FLATTREE
select IRQ_DOMAIN
+ select HANDLE_DOMAIN_IRQ
select HAVE_MEMBLOCK
select ARCH_REQUIRE_GPIOLIB
select HAVE_ARCH_TRACEHOOK
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index 967eb14..e9aaf28 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -50,14 +50,7 @@ void __init set_handle_irq(void (*handle_irq)(struct pt_regs
*))
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- generic_handle_irq(irq);
-
- irq_exit();
- set_irq_regs(old_regs);
+ __handle_domain_irq(NULL, irq, false, regs);
}
void __irq_entry do_IRQ(struct pt_regs *regs)
--
2.0.4
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[PATCH v2 06/26] irqchip: armada-370-xp: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-armada-370-xp.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c
b/drivers/irqchip/irq-armada-370-xp.c
index 574aba0..fa75a29 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -393,13 +393,15 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs
*regs, bool is_chained)
if (!(msimask BIT(msinr)))
continue;
- irq = irq_find_mapping(armada_370_xp_msi_domain,
- msinr - 16);
-
- if (is_chained)
+ if (is_chained) {
+ irq = irq_find_mapping(armada_370_xp_msi_domain,
+ msinr - 16);
generic_handle_irq(irq);
- else
- handle_IRQ(irq, regs);
+ } else {
+ irq = msinr - 16;
+ handle_domain_irq(armada_370_xp_msi_domain,
+ irq, regs);
+ }
}
}
#else
@@ -444,9 +446,8 @@ armada_370_xp_handle_irq(struct pt_regs *regs)
break;
if (irqnr 1) {
- irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
- irqnr);
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(armada_370_xp_mpic_domain,
+ irqnr, regs);
continue;
}
--
2.0.4
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[PATCH v2 01/26] genirq: add irq_domain-aware core IRQ handler
Calling irq_find_mapping from outside a irq_{enter,exit} section is
unsafe and produces ugly messages if CONFIG_PROVE_RCU is enabled:
If coming from the idle state, the rcu_read_lock call in irq_find_mapping
will generate an unpleasant warning:
quote
===
[ INFO: suspicious RCU usage. ]
3.16.0-rc1+ #135 Not tainted
---
include/linux/rcupdate.h:871 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
1 lock held by swapper/0/0:
#0: (rcu_read_lock){..}, at: [ffc00010206c]
irq_find_mapping+0x4c/0x198
/quote
As this issue is fairly widespread and involves at least three
different architectures, a possible solution is to add a new
handle_domain_irq entry point into the generic IRQ code that
the interrupt controller code can call.
This new function takes an irq_domain, and calls into irq_find_domain
inside the irq_{enter,exit} block. An additional lookup parameter is
used to allow non-domain architecture code to be replaced by this as well.
Interrupt controllers can then be updated to use the new mechanism.
This code is sitting behind a new CONFIG_HANDLE_DOMAIN_IRQ, as not all
architectures implement set_irq_regs (yes, mn10300, I'm looking at you...).
Reported-by: Vladimir Murzin vladimir.mur...@arm.com
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irqdesc.h | 19 +++
kernel/irq/Kconfig | 3 +++
kernel/irq/irqdesc.c| 42 ++
3 files changed, 64 insertions(+)
diff --git a/include/linux/irqdesc.h b/include/linux/irqdesc.h
index 472c021..ff24667 100644
--- a/include/linux/irqdesc.h
+++ b/include/linux/irqdesc.h
@@ -12,6 +12,8 @@ struct irq_affinity_notify;
struct proc_dir_entry;
struct module;
struct irq_desc;
+struct irq_domain;
+struct pt_regs;
/**
* struct irq_desc - interrupt descriptor
@@ -118,6 +120,23 @@ static inline void generic_handle_irq_desc(unsigned int
irq, struct irq_desc *de
int generic_handle_irq(unsigned int irq);
+#ifdef CONFIG_HANDLE_DOMAIN_IRQ
+/*
+ * Convert a HW interrupt number to a logical one using a IRQ domain,
+ * and handle the result interrupt number. Return -EINVAL if
+ * conversion failed. Providing a NULL domain indicates that the
+ * conversion has already been done.
+ */
+int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq,
+ bool lookup, struct pt_regs *regs);
+
+static inline int handle_domain_irq(struct irq_domain *domain,
+ unsigned int hwirq, struct pt_regs *regs)
+{
+ return __handle_domain_irq(domain, hwirq, true, regs);
+}
+#endif
+
/* Test to see if a driver has successfully requested an irq */
static inline int irq_has_action(unsigned int irq)
{
diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig
index d269cec..225086b 100644
--- a/kernel/irq/Kconfig
+++ b/kernel/irq/Kconfig
@@ -55,6 +55,9 @@ config GENERIC_IRQ_CHIP
config IRQ_DOMAIN
bool
+config HANDLE_DOMAIN_IRQ
+ bool
+
config IRQ_DOMAIN_DEBUG
bool Expose hardware/virtual IRQ mapping via debugfs
depends on IRQ_DOMAIN DEBUG_FS
diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c
index 1487a12..a1782f8 100644
--- a/kernel/irq/irqdesc.c
+++ b/kernel/irq/irqdesc.c
@@ -14,6 +14,7 @@
#include linux/kernel_stat.h
#include linux/radix-tree.h
#include linux/bitmap.h
+#include linux/irqdomain.h
#include internals.h
@@ -336,6 +337,47 @@ int generic_handle_irq(unsigned int irq)
}
EXPORT_SYMBOL_GPL(generic_handle_irq);
+#ifdef CONFIG_HANDLE_DOMAIN_IRQ
+/**
+ * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain
+ * @domain:The domain where to perform the lookup
+ * @hwirq: The HW irq number to convert to a logical one
+ * @lookup:Whether to perform the domain lookup or not
+ * @regs: Register file coming from the low-level handling code
+ *
+ * Returns:0 on success, or -EINVAL if conversion has failed
+ */
+int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq,
+ bool lookup, struct pt_regs *regs)
+{
+ struct pt_regs *old_regs = set_irq_regs(regs);
+ unsigned int irq = hwirq;
+ int ret = 0;
+
+ irq_enter();
+
+#ifdef CONFIG_IRQ_DOMAIN
+ if (lookup)
+ irq = irq_find_mapping(domain, hwirq);
+#endif
+
+ /*
+* Some hardware gives randomly wrong interrupts. Rather
+* than crashing, do something sensible.
+*/
+ if (unlikely(!irq || irq = nr_irqs)) {
+ ack_bad_irq(irq);
+ ret = -EINVAL;
+ } else {
+ generic_handle_irq(irq);
+ }
+
+ irq_exit();
+ set_irq_regs(old_regs);
+ return ret;
+}
+#endif
+
/* Dynamic interrupt handling */
/**
--
2.0.4
[PATCH v2 02/26] arm64: convert handle_IRQ to use __handle_domain_irq
In order to limit code duplication, convert the architecture specific
handle_IRQ to use the generic __handle_domain_irq function.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/irq.c | 18 +-
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fd4e81a..1f16ed9 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -30,6 +30,7 @@ config ARM64
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
select GENERIC_TIME_VSYSCALL
+ select HANDLE_DOMAIN_IRQ
select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL
select HAVE_ARCH_JUMP_LABEL
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0f08dfd..2c0e2a7 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -48,23 +48,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
*/
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- /*
-* Some hardware gives randomly wrong interrupts. Rather
-* than crashing, do something sensible.
-*/
- if (unlikely(irq = nr_irqs)) {
- pr_warn_ratelimited(Bad IRQ%u\n, irq);
- ack_bad_irq(irq);
- } else {
- generic_handle_irq(irq);
- }
-
- irq_exit();
- set_irq_regs(old_regs);
+ __handle_domain_irq(NULL, irq, false, regs);
}
void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
--
2.0.4
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[PATCH v2 07/26] irqchip: clps711x: convert to handle_domain_irq
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-clps711x.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-clps711x.c b/drivers/irqchip/irq-clps711x.c
index 33340dc..33127f1 100644
--- a/drivers/irqchip/irq-clps711x.c
+++ b/drivers/irqchip/irq-clps711x.c
@@ -76,24 +76,20 @@ static struct {
static asmlinkage void __exception_irq_entry clps711x_irqh(struct pt_regs
*regs)
{
- u32 irqnr, irqstat;
+ u32 irqstat;
do {
irqstat = readw_relaxed(clps711x_intc-intmr[0])
readw_relaxed(clps711x_intc-intsr[0]);
- if (irqstat) {
- irqnr = irq_find_mapping(clps711x_intc-domain,
-fls(irqstat) - 1);
- handle_IRQ(irqnr, regs);
- }
+ if (irqstat)
+ handle_domain_irq(clps711x_intc-domain,
+ fls(irqstat) - 1, regs);
irqstat = readw_relaxed(clps711x_intc-intmr[1])
readw_relaxed(clps711x_intc-intsr[1]);
- if (irqstat) {
- irqnr = irq_find_mapping(clps711x_intc-domain,
-fls(irqstat) - 1 + 16);
- handle_IRQ(irqnr, regs);
- }
+ if (irqstat)
+ handle_domain_irq(clps711x_intc-domain,
+ fls(irqstat) - 1 + 16, regs);
} while (irqstat);
}
--
2.0.4
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[PATCH v4 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine descriptor, even though it can be
already set earlier. This patch fixes this by making the assignment
conditional, depending on whether current .write_sec callback is NULL.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/kernel/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2c42576..e7383b9 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -125,7 +125,8 @@ void __init init_IRQ(void)
if (IS_ENABLED(CONFIG_OF) IS_ENABLED(CONFIG_CACHE_L2X0)
(machine_desc-l2c_aux_mask || machine_desc-l2c_aux_val)) {
- outer_cache.write_sec = machine_desc-l2c_write_sec;
+ if (!outer_cache.write_sec)
+ outer_cache.write_sec = machine_desc-l2c_write_sec;
ret = l2x0_of_init(machine_desc-l2c_aux_val,
machine_desc-l2c_aux_mask);
if (ret)
--
2.0.4
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[PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs
This series intends to add support for L2 cache on Exynos4 SoCs on boards
running under secure firmware, which requires certain initialization steps
to be done with help of firmware, as selected registers are writable only
from secure mode.
First four patches extend existing support for secure write in L2C driver
to account for design of secure firmware running on Exynos. Namely:
1) direct read access to certain registers is needed on Exynos, because
secure firmware calls set several registers at once,
2) not all boards are running secure firmware, so .write_sec callback
needs to be installed in Exynos firmware ops initialization code,
3) write access to {DATA,TAG}_LATENCY_CTRL registers fron non-secure world
is not allowed and so must use l2c_write_sec as well,
4) on certain boards, default value of prefetch register is incorrect
and must be overridden at L2C initialization.
For boards running with firmware that provides access to individual
L2C registers this series should introduce no functional changes. However
since the driver is widely used on other platforms I'd like to kindly ask
any interested people for testing.
Further three patches add implementation of .write_sec and .configure
callbacks for Exynos secure firmware and necessary DT nodes to enable
L2 cache.
Changes in this version tested on Exynos4412-based TRATS2 board (with secure
firmware). There should be no functional change for Exynos boards running
without secure firmware. I do not have access to affected non-Exynos boards,
so I could not test on them.
Depends on:
- [PATCH v3 0/5] Firmware-assisted suspend/resume of Exynos SoCs
(https://lkml.org/lkml/2014/8/26/445)
Changes since v3:
(https://lkml.org/lkml/2014/7/17/600)
- fixed issues with references to initdata on resume path by creating
a copy of affected structure (pointed out by Russell King),
- fixed unnecessary full reconfiguration of L2C controller on resume
(configuration is already determined after initialization, so the
only thing to do is to push those values to the controller),
- rebased on next-20140717 tag of linux-next tree and last versions
of dependencies.
Changes since v2:
(https://lkml.org/lkml/2014/6/25/416)
- refactored L2C driver to use commit-like interface and make it no longer
depend on availability of writes to individual registers,
- moved L2C resume to assembly code, because doing it later makes some
systems unstable - this is also needed for deeper cpuidle modes,
- dropped unnecessary patch hacking around the .write_sec interface,
- dropped patch making the driver use l2c_write_sec() for LATENCY_CTRL
registers as Exynos is no longer affected and I'm not aware of any
reports that this is also needed on other platforms (can be applied
separately if it turns out to be so),
- rebased onto next-20140717 tag of linux-next tree.
Changes since v1:
(https://www.mail-archive.com/linux-omap@vger.kernel.org/msg106323.html)
- rebased onto for-next branch of linux-samsung tree,
- changed argument order of outer_cache.write_sec() callback to match
l2c_write_sec() function in cache-l2x0.c,
- added support of overriding of prefetch settings to work around incorrect
default settings on certain Exynos4x12-based boards,
- added call to firmware to invalidate whole L2 cache before setting enable
bit in L2C control register (required by Exynos secure firmware).
Tomasz Figa (7):
ARM: l2c: Refactor the driver to use commit-like interface
ARM: l2c: Add interface to ask hypervisor to configure L2C
ARM: l2c: Get outer cache .write_sec callback from mach_desc only if
not NULL
ARM: l2c: Add support for overriding prefetch settings
ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
ARM: EXYNOS: Add support for non-secure L2X0 resume
ARM: dts: exynos4: Add nodes for L2 cache controller
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
arch/arm/include/asm/outercache.h | 3 +
arch/arm/kernel/irq.c | 3 +-
arch/arm/mach-exynos/common.h | 1 +
arch/arm/mach-exynos/firmware.c| 42 +++-
arch/arm/mach-exynos/sleep.S | 41
arch/arm/mm/cache-l2x0.c | 255 -
9 files changed, 281 insertions(+), 97 deletions(-)
--
2.0.4
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[PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume
On Exynos SoCs it is necessary to resume operation of L2C early in assembly code, because otherwise certain systems will crash. This patch adds necessary code to non-secure resume handler. Signed-off-by: Tomasz Figa t.f...@samsung.com --- arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/firmware.c | 4 +++- arch/arm/mach-exynos/sleep.S| 41 + 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index c218200..e88c0f9 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) extern u32 cp15_save_diag; extern u32 cp15_save_power; +extern unsigned long l2x0_regs_phys; extern void __iomem *sysram_ns_base_addr; extern void __iomem *sysram_base_addr; diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 554b350..71bcfbd 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -102,7 +102,9 @@ static int exynos_suspend(void) writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG); writel(virt_to_phys(exynos_cpu_resume_ns), sysram_ns_base_addr + EXYNOS_BOOT_ADDR); - +#ifdef CONFIG_CACHE_L2X0 + l2x0_regs_phys = virt_to_phys(l2x0_saved_regs); +#endif return cpu_suspend(0, exynos_cpu_suspend); } diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S index e3c3730..b8ce8f0 100644 --- a/arch/arm/mach-exynos/sleep.S +++ b/arch/arm/mach-exynos/sleep.S @@ -16,6 +16,8 @@ */ #include linux/linkage.h +#include asm/asm-offsets.h +#include asm/hardware/cache-l2x0.h #include smc.h #define CPU_MASK 0xff00 @@ -74,6 +76,40 @@ ENTRY(exynos_cpu_resume_ns) mov r0, #SMC_CMD_C15RESUME dsb smc #0 +#ifdef CONFIG_CACHE_L2X0 + adr r0, l2x0_regs_phys + ldr r0, [r0] + cmp r0, #0 + beq skip_l2x0 + + ldr r1, [r0, #L2X0_R_PHY_BASE] + ldr r2, [r1, #L2X0_CTRL] + tst r2, #0x1 + bne skip_l2x0 + + ldr r1, [r0, #L2X0_R_TAG_LATENCY] + ldr r2, [r0, #L2X0_R_DATA_LATENCY] + ldr r3, [r0, #L2X0_R_PREFETCH_CTRL] + mov r0, #SMC_CMD_L2X0SETUP1 + smc #0 + + /* Reload saved regs pointer because smc corrupts registers. */ + adr r0, l2x0_regs_phys + ldr r0, [r0] + + ldr r1, [r0, #L2X0_R_PWR_CTRL] + ldr r2, [r0, #L2X0_R_AUX_CTRL] + mov r0, #SMC_CMD_L2X0SETUP2 + smc #0 + + mov r0, #SMC_CMD_L2X0INVALL + smc #0 + + mov r1, #1 + mov r0, #SMC_CMD_L2X0CTRL + smc #0 +skip_l2x0: +#endif /* CONFIG_CACHE_L2X0 */ skip_cp15: b cpu_resume ENDPROC(exynos_cpu_resume_ns) @@ -83,3 +119,8 @@ cp15_save_diag: .globl cp15_save_power cp15_save_power: .long 0 @ cp15 power control +#ifdef CONFIG_CACHE_L2X0 + .globl l2x0_regs_phys +l2x0_regs_phys: + .long 0 @ phys address of l2x0 save struct +#endif /* CONFIG_CACHE_L2X0 */ -- 2.0.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/7] ARM: l2c: Refactor the driver to use commit-like interface
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mm/cache-l2x0.c | 210 ++-
1 file changed, 115 insertions(+), 95 deletions(-)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 5f2c988..b073563 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -40,12 +40,14 @@ struct l2c_init_data {
void (*enable)(void __iomem *, u32, unsigned);
void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
void (*save)(void __iomem *);
+ void (*configure)(void __iomem *);
struct outer_cache_fns outer_cache;
};
#define CACHE_LINE_SIZE32
static void __iomem *l2x0_base;
+static const struct l2c_init_data *l2x0_data;
static DEFINE_RAW_SPINLOCK(l2x0_lock);
static u32 l2x0_way_mask; /* Bitmask of active ways */
static u32 l2x0_size;
@@ -105,6 +107,14 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
}
}
+static void l2c_configure(void __iomem *base)
+{
+ if (l2x0_data-configure)
+ l2x0_data-configure(base);
+
+ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
+}
+
/*
* Enable the L2 cache controller. This function must only be
* called when the cache controller is known to be disabled.
@@ -113,7 +123,12 @@ static void l2c_enable(void __iomem *base, u32 aux,
unsigned num_lock)
{
unsigned long flags;
- l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+ /* Do not touch the controller if already enabled. */
+ if (readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)
+ return;
+
+ l2x0_saved_regs.aux_ctrl = aux;
+ l2c_configure(base);
l2c_unlock(base, num_lock);
@@ -207,6 +222,11 @@ static void l2c_save(void __iomem *base)
l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
}
+static void l2c_resume(void)
+{
+ l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data-num_lock);
+}
+
/*
* L2C-210 specific code.
*
@@ -287,14 +307,6 @@ static void l2c210_sync(void)
__l2c210_cache_sync(l2x0_base);
}
-static void l2c210_resume(void)
-{
- void __iomem *base = l2x0_base;
-
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN))
- l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
-}
-
static const struct l2c_init_data l2c210_data __initconst = {
.type = L2C-210,
.way_size_0 = SZ_8K,
@@ -308,7 +320,7 @@ static const struct l2c_init_data l2c210_data __initconst =
{
.flush_all = l2c210_flush_all,
.disable = l2c_disable,
.sync = l2c210_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -465,7 +477,7 @@ static const struct l2c_init_data l2c220_data = {
.flush_all = l2c220_flush_all,
.disable = l2c_disable,
.sync = l2c220_sync,
- .resume = l2c210_resume,
+ .resume = l2c_resume,
},
};
@@ -614,39 +626,29 @@ static void __init l2c310_save(void __iomem *base)
L310_POWER_CTRL);
}
-static void l2c310_resume(void)
+static void l2c310_configure(void __iomem *base)
{
- void __iomem *base = l2x0_base;
+ unsigned revision;
- if (!(readl_relaxed(base + L2X0_CTRL) L2X0_CTRL_EN)) {
- unsigned revision;
-
- /* restore pl310 setup */
- writel_relaxed(l2x0_saved_regs.tag_latency,
- base + L310_TAG_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.data_latency,
- base + L310_DATA_LATENCY_CTRL);
- writel_relaxed(l2x0_saved_regs.filter_end,
- base + L310_ADDR_FILTER_END);
- writel_relaxed(l2x0_saved_regs.filter_start,
- base + L310_ADDR_FILTER_START);
-
- revision = readl_relaxed(base + L2X0_CACHE_ID)
- L2X0_CACHE_ID_RTL_MASK;
-
- if (revision = L310_CACHE_ID_RTL_R2P0)
- l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
- L310_PREFETCH_CTRL);
- if (revision = L310_CACHE_ID_RTL_R3P0)
-
[PATCH v4 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index 807bb5b..8a182c4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -64,6 +64,15 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 2 2 1;
+ };
+
gic: interrupt-controller@1049 {
cpu-offset = 0x8000;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 861bb91..c7adfd6 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
reg = 0x10023CA0 0x20;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = arm,pl310-cache;
+ reg = 0x10502000 0x1000;
+ cache-unified;
+ cache-level = 2;
+ arm,tag-latency = 2 2 1;
+ arm,data-latency = 3 2 1;
+ arm,double-linefill = 1;
+ arm,double-linefill-incr = 0;
+ arm,double-linefill-wrap = 1;
+ arm,prefetch-drop = 1;
+ arm,prefetch-offset = 7;
+ };
+
clock: clock-controller@1003 {
compatible = samsung,exynos4412-clock;
reg = 0x1003 0x2;
--
2.0.4
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[PATCH v4 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an implementation of
.write_sec and .configure callbacks is provided by this patch.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/firmware.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index f5e626d..554b350 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -17,6 +17,7 @@
#include asm/cacheflush.h
#include asm/cputype.h
#include asm/firmware.h
+#include asm/hardware/cache-l2x0.h
#include asm/suspend.h
#include mach/map.h
@@ -120,6 +121,31 @@ static const struct firmware_ops exynos_firmware_ops = {
.resume = exynos_resume,
};
+static void exynos_l2_write_sec(unsigned long val, unsigned reg)
+{
+ switch (reg) {
+ case L2X0_CTRL:
+ if (val L2X0_CTRL_EN)
+ exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
+ exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
+ break;
+
+ case L2X0_DEBUG_CTRL:
+ exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
+ break;
+
+ default:
+ WARN_ONCE(1, %s: ignoring write to reg 0x%x\n, __func__, reg);
+ }
+}
+
+static void exynos_l2_configure(const struct l2x0_regs *regs)
+{
+ exynos_smc(SMC_CMD_L2X0SETUP1, regs-tag_latency, regs-data_latency,
+ regs-prefetch_ctrl);
+ exynos_smc(SMC_CMD_L2X0SETUP2, regs-pwr_ctrl, regs-aux_ctrl, 0);
+}
+
void __init exynos_firmware_init(void)
{
struct device_node *nd;
@@ -139,4 +165,16 @@ void __init exynos_firmware_init(void)
pr_info(Running under secure firmware.\n);
register_firmware_ops(exynos_firmware_ops);
+
+ /*
+* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
+* running under secure firmware, require certain registers of L2
+* cache controller to be written in secure mode. Here .write_sec
+* callback is provided to perform necessary SMC calls.
+*/
+ if (IS_ENABLED(CONFIG_CACHE_L2X0)
+read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+ outer_cache.write_sec = exynos_l2_write_sec;
+ outer_cache.configure = exynos_l2_configure;
+ }
}
--
2.0.4
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[PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 10 +++
arch/arm/mm/cache-l2x0.c | 39 ++
2 files changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt
b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee..3443d2d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -47,6 +47,16 @@ Optional properties:
- cache-id-part: cache id part number to be used if it is not present
on hardware
- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if
non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
Example:
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 84c6c55..af90a6f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1059,6 +1059,8 @@ static void __init l2c310_of_parse(const struct
device_node *np,
u32 data[3] = { 0, 0, 0 };
u32 tag[3] = { 0, 0, 0 };
u32 filter[2] = { 0, 0 };
+ u32 prefetch;
+ u32 val;
of_property_read_u32_array(np, arm,tag-latency, tag, ARRAY_SIZE(tag));
if (tag[0] tag[1] tag[2])
@@ -1083,6 +1085,43 @@ static void __init l2c310_of_parse(const struct
device_node *np,
l2x0_saved_regs.filter_start = (filter[0] ~(SZ_1M - 1))
| L310_ADDR_FILTER_EN;
}
+
+ prefetch = l2x0_saved_regs.prefetch_ctrl;
+
+ if (!of_property_read_u32(np, arm,double-linefill, val)) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL;
+ }
+
+ if (!of_property_read_u32(np, arm,double-linefill-incr, val)) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
+ }
+
+ if (!of_property_read_u32(np, arm,double-linefill-wrap, val)) {
+ if (!val)
+ prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
+ }
+
+ if (!of_property_read_u32(np, arm,prefetch-drop, val)) {
+ if (val)
+ prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
+ else
+ prefetch = ~L310_PREFETCH_CTRL_PREFETCH_DROP;
+ }
+
+ if (!of_property_read_u32(np, arm,prefetch-offset, val)) {
+ prefetch = ~L310_PREFETCH_CTRL_OFFSET_MASK;
+ prefetch |= val L310_PREFETCH_CTRL_OFFSET_MASK;
+ }
+
+ l2x0_saved_regs.prefetch_ctrl = prefetch;
}
static const struct l2c_init_data of_l2c310_data __initconst = {
--
2.0.4
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[PATCH v4 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.
Signed-off-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/include/asm/outercache.h | 3 +++
arch/arm/mm/cache-l2x0.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/arm/include/asm/outercache.h
b/arch/arm/include/asm/outercache.h
index 891a56b..563b92f 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -23,6 +23,8 @@
#include linux/types.h
+struct l2x0_regs;
+
struct outer_cache_fns {
void (*inv_range)(unsigned long, unsigned long);
void (*clean_range)(unsigned long, unsigned long);
@@ -36,6 +38,7 @@ struct outer_cache_fns {
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
+ void (*configure)(const struct l2x0_regs *);
};
extern struct outer_cache_fns outer_cache;
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index b073563..84c6c55 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -109,6 +109,11 @@ static inline void l2c_unlock(void __iomem *base, unsigned
num)
static void l2c_configure(void __iomem *base)
{
+ if (outer_cache.configure) {
+ outer_cache.configure(l2x0_saved_regs);
+ return;
+ }
+
if (l2x0_data-configure)
l2x0_data-configure(base);
@@ -909,6 +914,7 @@ static int __init __l2c_init(const struct l2c_init_data
*data,
fns = data-outer_cache;
fns.write_sec = outer_cache.write_sec;
+ fns.configure = outer_cache.configure;
if (data-fixup)
data-fixup(l2x0_base, cache_id, fns);
--
2.0.4
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Re: [PATCH] pstore/ram_core: Fix hang on ARMs because of pgprot_noncached
* Arnd Bergmann a...@arndb.de [140826 02:16]:
On Monday 25 August 2014 16:14:50 Tony Lindgren wrote:
-static void *persistent_ram_vmap(phys_addr_t start, size_t size)
+static void *persistent_ram_vmap(phys_addr_t start, size_t size,
+ unsigned int cached)
{
struct page **pages;
phys_addr_t page_start;
@@ -392,7 +393,10 @@ static void *persistent_ram_vmap(phys_addr_t start,
size_t size)
page_start = start - offset_in_page(start);
page_count = DIV_ROUND_UP(size + offset_in_page(start), PAGE_SIZE);
- prot = pgprot_noncached(PAGE_KERNEL);
+ if (cached)
+ prot = pgprot_writecombine(PAGE_KERNEL);
+ else
+ prot = pgprot_noncached(PAGE_KERNEL);
pages = kmalloc_array(page_count, sizeof(struct page *),
GFP_KERNEL);
if (!pages) {
If you have a 'struct page', you also have a cacheable mapping in the kernel
already,
so you are not really supposed to add another uncached mapping. On some
architectures
(e.g. powerpc) that will cause the CPU to checkstop, on others it is undefined
behavior. What is the reason for using an uncached mapping here in the first
place?
The reason for using uncached mapping (really strongly ordered for ARM)
here is because Colin observed lost debug prints just before hanging register
writes because of the write buffer.
But it also sounds like pstore is broken for powerpc in addition to a bunch of
ARMs, and possibly other architectures too.
@@ -411,8 +415,11 @@ static void *persistent_ram_vmap(phys_addr_t start,
size_t size)
return vaddr;
}
-static void *persistent_ram_iomap(phys_addr_t start, size_t size)
+static void *persistent_ram_iomap(phys_addr_t start, size_t size,
+ unsigned int cached)
{
+ void *va;
+
if (!request_mem_region(start, size, persistent_ram)) {
pr_err(request mem region (0x%llx@0x%llx) failed\n,
(unsigned long long)size, (unsigned long
long)start);
@@ -422,19 +429,24 @@ static void *persistent_ram_iomap(phys_addr_t start,
size_t size)
buffer_start_add = buffer_start_add_locked;
buffer_size_add = buffer_size_add_locked;
- return ioremap(start, size);
+ if (cached)
+ va = ioremap(start, size);
+ else
+ va = ioremap_wc(start, size);
+
+ return va;
}
This seems confusing at best, but is probably just wrong: so you use
an uncached mapping if someone asks for cached, but use a (more relaxed)
write-combining mapping if someone asked for a stricter mapping?
It's also the other way round for persistent_ram_vmap above.
Indeed, the cached test for the ioremap is the wrong way around here.
According to your description, the intention is to make atomic operations
work, however most architectures don't allow atomics on either type of
uncached mapping, since atomicity is a feature of the cache coherency
fabric.
The only way I see to actually make atomics work here is to use a cached
mapping and explicit dcache flushes to actually force the data into
persistent storage.
Right, that's what Rob attempted to patch a while back:
https://lkml.org/lkml/2013/4/9/831
See also the comments from Colin in that thread:
https://lkml.org/lkml/2013/4/9/854
The reason why I added the module_param is because Rob's fix did not
go anywhere for over a year now. And adding the module_param seemed to
help with the concerns Colin had. Personally I don't need the strongly
ordered option though, I just need pgprot_writecombine :)
It's starting to sound that we should first apply Rob's original fix
to get pstore working. Then we can figure out how to deal with the
unbuffered mapping for architectures and SoCs that support it.
Regards,
Tony
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Re: [PATCH v2 02/26] arm64: convert handle_IRQ to use __handle_domain_irq
On Tue, Aug 26, 2014 at 11:03:17AM +0100, Marc Zyngier wrote:
In order to limit code duplication, convert the architecture specific
handle_IRQ to use the generic __handle_domain_irq function.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/irq.c | 18 +-
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fd4e81a..1f16ed9 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -30,6 +30,7 @@ config ARM64
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
select GENERIC_TIME_VSYSCALL
+ select HANDLE_DOMAIN_IRQ
select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL
select HAVE_ARCH_JUMP_LABEL
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0f08dfd..2c0e2a7 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -48,23 +48,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
*/
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- /*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
- if (unlikely(irq = nr_irqs)) {
- pr_warn_ratelimited(Bad IRQ%u\n, irq);
- ack_bad_irq(irq);
- } else {
- generic_handle_irq(irq);
- }
-
- irq_exit();
- set_irq_regs(old_regs);
+ __handle_domain_irq(NULL, irq, false, regs);
}
The only thing that's missing is a pr_warn_ratelimited(). Do we still
need it? We could add it to ack_bad_irq() though.
Either way:
Acked-by: Catalin Marinas catalin.mari...@arm.com
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Re: [PATCH v2 25/26] arm64: get rid of handle_IRQ
On Tue, Aug 26, 2014 at 11:03:40AM +0100, Marc Zyngier wrote: All the arm64 irqchip drivers have been converted to handle_domain_irq, making it possible to remove the handle_IRQ stub entierely. Signed-off-by: Marc Zyngier marc.zyng...@arm.com Acked-by: Catalin Marinas catalin.mari...@arm.com -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 27/27] OMAPDSS: connector-analog-tv: Add DT support
Hi Tomi,
On Monday 16 December 2013 16:56:34 Tomi Valkeinen wrote:
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
.../video/omap2/displays-new/connector-analog-tv.c | 66 ++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/drivers/video/omap2/displays-new/connector-analog-tv.c
b/drivers/video/omap2/displays-new/connector-analog-tv.c index
ccd9073f706f..ebed25a86487 100644
--- a/drivers/video/omap2/displays-new/connector-analog-tv.c
+++ b/drivers/video/omap2/displays-new/connector-analog-tv.c
@@ -12,6 +12,7 @@
#include linux/slab.h
#include linux/module.h
#include linux/platform_device.h
+#include linux/of.h
#include video/omapdss.h
#include video/omap-panel-data.h
@@ -42,6 +43,12 @@ static const struct omap_video_timings tvc_pal_timings =
{ .interlace = true,
};
+static const struct of_device_id tvc_of_match[];
+
+struct tvc_of_data {
+ enum omap_dss_venc_type connector_type;
+};
+
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int tvc_connect(struct omap_dss_device *dssdev)
@@ -92,7 +99,10 @@ static int tvc_enable(struct omap_dss_device *dssdev)
in-ops.atv-set_timings(in, ddata-timings);
in-ops.atv-set_type(in, ddata-connector_type);
- in-ops.atv-invert_vid_out_polarity(in, ddata-invert_polarity);
+
+ if (!ddata-dev-of_node)
+ in-ops.atv-invert_vid_out_polarity(in,
+ ddata-invert_polarity);
r = in-ops.atv-enable(in);
if (r)
@@ -205,6 +215,35 @@ static int tvc_probe_pdata(struct platform_device
*pdev) return 0;
}
+static int tvc_probe_of(struct platform_device *pdev)
+{
+ struct panel_drv_data *ddata = platform_get_drvdata(pdev);
+ struct device_node *node = pdev-dev.of_node;
+ struct omap_dss_device *in;
+ const struct of_device_id *match;
+ const struct tvc_of_data *data;
+
+ match = of_match_node(tvc_of_match, pdev-dev.of_node);
+ if (!match) {
+ dev_err(pdev-dev, unsupported device\n);
+ return -ENODEV;
+ }
+
+ data = match-data;
+
+ in = omapdss_of_find_source_for_first_ep(node);
+ if (IS_ERR(in)) {
+ dev_err(pdev-dev, failed to find video source\n);
+ return PTR_ERR(in);
+ }
+
+ ddata-in = in;
+
+ ddata-connector_type = data-connector_type;
+
+ return 0;
+}
+
static int tvc_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
@@ -222,6 +261,10 @@ static int tvc_probe(struct platform_device *pdev)
r = tvc_probe_pdata(pdev);
if (r)
return r;
+ } else if (pdev-dev.of_node) {
+ r = tvc_probe_of(pdev);
+ if (r)
+ return r;
} else {
return -ENODEV;
}
@@ -263,12 +306,33 @@ static int __exit tvc_remove(struct platform_device
*pdev) return 0;
}
+static const struct tvc_of_data tv_svideo_data = {
+ .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+
+static const struct tvc_of_data tv_composite_video_data = {
+ .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
+};
+
+static const struct of_device_id tvc_of_match[] = {
+ {
+ .compatible = svideo-connector,
+ .data = tv_svideo_data,
+ },
+ {
+ .compatible = composite-video-connector,
I've just noticed that this doesn't match the bindings that document the
compatible value to be composite-connector.
+ .data = tv_composite_video_data,
+ },
+ {},
+};
+
static struct platform_driver tvc_connector_driver = {
.probe = tvc_probe,
.remove = __exit_p(tvc_remove),
.driver = {
.name = connector-analog-tv,
.owner = THIS_MODULE,
+ .of_match_table = tvc_of_match,
},
};
--
Regards,
Laurent Pinchart
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Re: [PATCH v2 02/26] arm64: convert handle_IRQ to use __handle_domain_irq
On 26/08/14 17:51, Catalin Marinas wrote:
On Tue, Aug 26, 2014 at 11:03:17AM +0100, Marc Zyngier wrote:
In order to limit code duplication, convert the architecture specific
handle_IRQ to use the generic __handle_domain_irq function.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm64/Kconfig | 1 +
arch/arm64/kernel/irq.c | 18 +-
2 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fd4e81a..1f16ed9 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -30,6 +30,7 @@ config ARM64
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
select GENERIC_TIME_VSYSCALL
+select HANDLE_DOMAIN_IRQ
select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL
select HAVE_ARCH_JUMP_LABEL
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0f08dfd..2c0e2a7 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -48,23 +48,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
*/
void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
-struct pt_regs *old_regs = set_irq_regs(regs);
-
-irq_enter();
-
-/*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
-if (unlikely(irq = nr_irqs)) {
-pr_warn_ratelimited(Bad IRQ%u\n, irq);
-ack_bad_irq(irq);
-} else {
-generic_handle_irq(irq);
-}
-
-irq_exit();
-set_irq_regs(old_regs);
+__handle_domain_irq(NULL, irq, false, regs);
}
The only thing that's missing is a pr_warn_ratelimited(). Do we still
need it? We could add it to ack_bad_irq() though.
Indeed, we could move the warning to ack_bad_irq(), which is always
architecture specific. I'll add that to the next version of the series.
Either way:
Acked-by: Catalin Marinas catalin.mari...@arm.com
Thanks,
M.
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possible bug with v3.17-rc1
Hi, first of all, yes, I will try v3.17-rc2 shortly ;-) So this kicked in when I was doing a rather large upgrade on my board, so many packages were unpacked, installed, setup, etc. I wonder if anybody has faced similar issues with v3.17-rc1 ? This is with an AM437x StarterKit btw. Logs below ps: this just might have screwed my filesystem :-p root@saruman:~# apt-get upgrade Reading package lists... 0%Reading package lists... 100%Reading package lists... Done Building dependency tree... 0%Building dependency tree... 0%Building dependency tree... 50%Building dependency tree... 50%Building dependency tree... 73%Building dependency tree Reading state information... 0%Reading state information... 0%Reading state information... Done Calculating upgrade... Done The following packages were automatically installed and are no longer required: accountsservice aisleriot apache2-bin apg argyll bluez bogofilter bogofilter-bdb bogofilter-common cheese-common cracklib-runtime crda cups-pk-helper dnsmasq-base dnsutils empathy-common espeak-data evince-common evolution-common evolution-data-server evolution-data-server-common finger five-or-more folks-common four-in-a-row gcr gdebi-core gedit-common gir1.2-accountsservice-1.0 gir1.2-clutter-gst-2.0 gir1.2-evince-3.0 gir1.2-gck-1 gir1.2-gcr-3 gir1.2-gdata-0.0 gir1.2-gdesktopenums-3.0 gir1.2-gdm3 gir1.2-gkbd-3.0 gir1.2-gmenu-3.0 gir1.2-gnomebluetooth-1.0 gir1.2-gnomekeyring-1.0 gir1.2-goa-1.0 gir1.2-gst-plugins-base-1.0 gir1.2-gstreamer-0.10 gir1.2-gtkclutter-1.0 gir1.2-gtksource-3.0 gir1.2-gtop-2.0 gir1.2-gucharmap-2.90 gir1.2-ibus-1.0 gir1.2-javascriptcoregtk-3.0 gir1.2-mutter-3.0 gir1.2-networkmanager-1.0 gir1.2-nmgtk-1.0 gir1.2-notify-0.7 gir1.2-packagekitglib-1.0 gir1.2-polkit-1.0 gir1.2-rest-0.7 gir1.2-secret-1 gir1.2-soup-2.4 gir1.2-telepathyglib-0.12 gir1.2-telepathylogger-0.2 gir1.2-totem-plparser-1.0 gir1.2-tracker-1.0 gir1.2-upowerglib-1.0 gir1.2-vte-2.90 gir1.2-webkit-3.0 gir1.2-wnck-3.0 gir1.2-xkl-1.0 gir1.2-zeitgeist-2.0 gir1.2-zpj-0.0 gjs gkbd-capplet gksu gnuchess gnuchess-book grilo-plugins-0.2 gstreamer0.10-alsa gstreamer0.10-nice gstreamer0.10-pulseaudio gstreamer1.0-clutter gstreamer1.0-nice gtk2-engines-pixbuf gtk2-engines-xfce guile-2.0-libs hwdata iagno iputils-tracepath iw libabw-0.0-0 libaccountsservice0 libapache2-mod-dnssd libapr1 libaprutil1 libaprutil1-dbd-sqlite3 libaprutil1-ldap libart-2.0-2 libass4 libatkmm-1.6-1 libbonoboui2-common libboost-system1.55.0 libbrlapi0.6 libcairomm-1.0-1 libcamel-1.2-49 libcdr-0.0-0 libchamplain-0.12-0 libchamplain-gtk-0.12-0 libcheese-gtk23 libcheese7 libclutter-gst-2.0-0 libclutter-gtk-1.0-0 libcolord-gtk1 libcrack2 libdee-1.0-4 libdmapsharing-3.0-2 libdotconf0 libe-book-0.0-0 libebackend-1.2-7 libebook-1.2-14 libebook-contacts-1.2-0 libecal-1.2-16 libedata-book-1.2-20 libedata-cal-1.2-23 libedataserver-1.2-18 libedit2 libespeak1 libetonyek-0.0-0 libevdocument3-4 libevview3-3 libexempi3 libexo-common libexo-helpers libfarstream-0.1-0 libfarstream-0.2-2 libfftw3-3 libfolks-eds25 libfolks-telepathy25 libfolks25 libfreehand-0.0-0 libgail-3-0 libgarcon-1-0 libgarcon-common libgc1c2 libgck-1-0 libgcr-3-common libgcr-base-3-1 libgcr-ui-3-1 libgdata-common libgdata19 libgdict-1.0-6 libgdict-common libgdm1 libgeoclue0 libgeocode-glib0 libgjs0c libgksu2-0 libglade2-0 libglibmm-2.4-1c2a libgnome-bluetooth11 libgnome-keyring-common libgnome-keyring0 libgnome-media-profiles-3.0-0 libgnome-menu-3-0 libgnomecanvas2-0 libgnomecanvas2-common libgnomekbd-common libgnomekbd8 libgnomeui-common libgoa-backend-1.0-1 libgpod-common libgpod4 libgrilo-0.2-1 libgsf-1-114 libgsf-1-common libgsl0ldbl libgtkmm-2.4-1c2a libgtkmm-3.0-1 libgtksourceview-3.0-1 libgtksourceview-3.0-common libgtkspell3-3-0 libgtop2-7 libgtop2-common libgupnp-igd-1.0-4 libgweather-3-6 libgweather-common libgxps2 libibus-1.0-5 libical1 libicc2 libidl0 libimdi0 libiptcdata0 libjpeg-progs libkeybinder0 libkpathsea6 liblinear1 liblouis-data liblouis2 liblua5.1-0 libmagick++5 libmeanwhile1 libmediaart-1.0-0 libmetacity-private0a libminiupnpc8 libmission-control-plugins0 libmozjs185-1.0 libmspub-0.0-0 libmutter0b libmwaw-0.2-2 libnetfilter-conntrack3 libnice10 libnl-route-3-200 libnm-glib-vpn1 libnm-gtk-common libnm-gtk0 libnotify-bin liboauth0 libodfgen-0.0-0 libopts25 liborbit2 liborcus-0.6-0 libpackagekit-glib2-16 libpam-gnome-keyring libpangomm-1.4-1 libpeas-common libperl5.18 libplot2c2 libpst4 libpstoedit0c2a libpulse-mainloop-glib0 libpurple-bin libpurple0 libpwquality-common libpwquality1 libreoffice-avmedia-backend-gstreamer libreoffice-base-core libreoffice-calc libreoffice-draw libreoffice-impress libreoffice-java-common libreoffice-math libreoffice-writer librest-extras-0.7-0 librtmp0 libsgutils2-2 libsocialweb-client2 libsocialweb-common libsocialweb-service libsocialweb0 libsonic0 libspectre1 libspeechd2
Re: [PATCH v2 01/26] genirq: add irq_domain-aware core IRQ handler
On 08/26/14 03:03, Marc Zyngier wrote:
Calling irq_find_mapping from outside a irq_{enter,exit} section is
unsafe and produces ugly messages if CONFIG_PROVE_RCU is enabled:
If coming from the idle state, the rcu_read_lock call in irq_find_mapping
will generate an unpleasant warning:
quote
===
[ INFO: suspicious RCU usage. ]
3.16.0-rc1+ #135 Not tainted
---
include/linux/rcupdate.h:871 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
1 lock held by swapper/0/0:
#0: (rcu_read_lock){..}, at: [ffc00010206c]
irq_find_mapping+0x4c/0x198
Do you have the whole stacktrace? I don't see where this is called
outside of irq_enter() from within the idle loop, but maybe I missed
something.
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Re: [PATCH v2 01/26] genirq: add irq_domain-aware core IRQ handler
On 26/08/14 18:42, Stephen Boyd wrote:
On 08/26/14 03:03, Marc Zyngier wrote:
Calling irq_find_mapping from outside a irq_{enter,exit} section is
unsafe and produces ugly messages if CONFIG_PROVE_RCU is enabled:
If coming from the idle state, the rcu_read_lock call in irq_find_mapping
will generate an unpleasant warning:
quote
===
[ INFO: suspicious RCU usage. ]
3.16.0-rc1+ #135 Not tainted
---
include/linux/rcupdate.h:871 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
1 lock held by swapper/0/0:
#0: (rcu_read_lock){..}, at: [ffc00010206c]
irq_find_mapping+0x4c/0x198
Do you have the whole stacktrace? I don't see where this is called
outside of irq_enter() from within the idle loop, but maybe I missed
something.
Hi Stephen,
Digging into my email, one of the traces looked like this:
stack backtrace:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.16.0-rc1+ #135
Call trace:
[ffc882cc] dump_backtrace+0x0/0x12c
[ffc88408] show_stack+0x10/0x1c
[ffc0004ee5f0] dump_stack+0x74/0xc4
[ffcedfbc] lockdep_rcu_suspicious+0xe8/0x124
[ffc00010218c] irq_find_mapping+0x16c/0x198
[ffc8130c] gic_handle_irq+0x38/0xcc
Most drivers call irq_find_mapping outside of irq_enter()/irq_exit(), as
this is in handle_IRQ().
Thanks,
M.
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Re: [PATCH v2 01/26] genirq: add irq_domain-aware core IRQ handler
On 08/26/14 11:07, Marc Zyngier wrote: Digging into my email, one of the traces looked like this: stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.16.0-rc1+ #135 Call trace: [ffc882cc] dump_backtrace+0x0/0x12c [ffc88408] show_stack+0x10/0x1c [ffc0004ee5f0] dump_stack+0x74/0xc4 [ffcedfbc] lockdep_rcu_suspicious+0xe8/0x124 [ffc00010218c] irq_find_mapping+0x16c/0x198 [ffc8130c] gic_handle_irq+0x38/0xcc Most drivers call irq_find_mapping outside of irq_enter()/irq_exit(), as this is in handle_IRQ(). Ah ok. This is the multi-irq handler case? Has this been broken since v3.2 at least for the gic users? Now that we call irq_enter()/irq_exit() a lot more code runs, including things like updating jiffies when interrupts arrive and invoking softirq? Do we only call irq_exit() on the IPI path otherwise? Are there any plans to send this back to stable trees? Not calling irq_enter()/irq_exit() when we get an interrupt seems like a big problem. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 01/26] genirq: add irq_domain-aware core IRQ handler
On 08/26/14 11:46, Stephen Boyd wrote: On 08/26/14 11:07, Marc Zyngier wrote: Digging into my email, one of the traces looked like this: stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.16.0-rc1+ #135 Call trace: [ffc882cc] dump_backtrace+0x0/0x12c [ffc88408] show_stack+0x10/0x1c [ffc0004ee5f0] dump_stack+0x74/0xc4 [ffcedfbc] lockdep_rcu_suspicious+0xe8/0x124 [ffc00010218c] irq_find_mapping+0x16c/0x198 [ffc8130c] gic_handle_irq+0x38/0xcc Most drivers call irq_find_mapping outside of irq_enter()/irq_exit(), as this is in handle_IRQ(). Ah ok. This is the multi-irq handler case? Has this been broken since v3.2 at least for the gic users? Now that we call irq_enter()/irq_exit() a lot more code runs, including things like updating jiffies when interrupts arrive and invoking softirq? Do we only call irq_exit() on the IPI path otherwise? Are there any plans to send this back to stable trees? Not calling irq_enter()/irq_exit() when we get an interrupt seems like a big problem. Hmm I see we still call handle_IRQ eventually. So it's not as bad as I first thought. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
* Tomi Valkeinen tomi.valkei...@ti.com [140826 02:48]: On 26/08/14 11:51, Tero Kristo wrote: Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated. Fixed by using proper divider clock types for the clock nodes. Signed-off-by: Tero Kristo t-kri...@ti.com Reported-by: Tomi Valkeinen tomi.valkei...@ti.com --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) Tested-by: Tomi Valkeinen tomi.valkei...@ti.com Thanks applying into omap-for-v3.17/fixes-v2. Tony -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 24/26] ARM: omap2: irq: convert to handle_domain_irq
* Marc Zyngier marc.zyng...@arm.com [140826 03:05]:
Use the new handle_domain_irq method to handle interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Seems to boot:
Acked-by: Tony Lindgren t...@atomide.com
---
arch/arm/mach-omap2/irq.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 35b8590..a62ba5a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -248,8 +248,7 @@ out:
irqnr = ACTIVEIRQ_MASK;
if (irqnr) {
- irqnr = irq_find_mapping(domain, irqnr);
- handle_IRQ(irqnr, regs);
+ handle_domain_irq(domain, irqnr, regs);
handled_irq = 1;
}
} while (irqnr);
--
2.0.4
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Re: [PATCH v2 00/26] genirq: fix use of irq_find_mapping outside of legal RCU context
On Tue, 26 Aug 2014, Marc Zyngier wrote:
A number of irqchip drivers are directly calling irq_find_mapping,
which may use a rcu_read_lock call when walking the radix tree.
Turns out that if you hit that point with CONFIG_PROVE_RCU enabled,
the kernel will shout at you, as using RCU in this context may be
illegal (specially if coming from the idle state, where RCU would be
in a quiescent state).
A possible fix would be to wrap calls to irq_find_mapping into a
RCU_NONIDLE macro, but that really looks ugly.
This patch series introduce another generic IRQ entry point
(handle_domain_irq), which has the exact same behaviour as handle_IRQ
(as defined on arm, arm64 and openrisc), except that it also takes a
irq_domain pointer. This allows the logical IRQ lookup to be done
inside the irq_{enter,exit} section, which contains a
rcu_irq_{enter,exit}, making it safe.
Looks good. Should this be routed to the genirq tree?
Thanks,
tglx
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[GIT PULL] omap fixes against v3.17-rc2
The following changes since commit 52addcf9d6669fa439387610bc65c92fa0980cef: Linux 3.17-rc2 (2014-08-25 15:36:20 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v3.17/fixes-against-rc2 for you to fetch changes up to 8fd46439e1f5a7f86d76a08733459b74debd9468: ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates (2014-08-26 13:04:00 -0700) Fixes for omaps, mostly to revert NAND back to using software ECC by default as that's what many boards expect. Also fixes for omap5 clocks, PM wake-up events, GPIO interrupt cells for dra7, and few other minor fixes. Hans Wennborg (1): ARM: OMAP: fix %d confusingly prefixed with 0x in format string Mark Brown (1): ARM: dts: Remove twl6030 clk32g regulator Markus Pargmann (1): ARM: OMAP2+: omap_device: remove warning that clk alias already exists Nishanth Menon (1): ARM: dts: DRA7: fix interrupt-cells for GPIO Roger Quadros (4): mtd: nand: omap: Revert to using software ECC by default ARM: OMAP2+: GPMC: Support Software ECC scheme via DT ARM: dts: omap3430-sdp: Revert to using software ECC for NAND mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc() Tero Kristo (1): ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates Tony Lindgren (2): ARM: dts: Enable UART wake-up events for beagleboard ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 2 +- arch/arm/boot/dts/dra7.dtsi | 16 arch/arm/boot/dts/omap3-beagle.dts | 1 + arch/arm/boot/dts/omap3430-sdp.dts | 2 +- arch/arm/boot/dts/omap54xx-clocks.dtsi | 16 ++-- arch/arm/boot/dts/twl6030.dtsi | 4 arch/arm/mach-omap2/board-flash.c | 2 +- arch/arm/mach-omap2/gpmc-nand.c | 3 ++- arch/arm/mach-omap2/gpmc.c | 7 +-- arch/arm/mach-omap2/id.c| 2 +- arch/arm/mach-omap2/omap_device.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c| 4 drivers/mtd/nand/omap2.c| 16 include/linux/platform_data/mtd-nand-omap2.h| 13 +++-- 14 files changed, 58 insertions(+), 32 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
