Re: [PATCH] I2C: Fix twl4030 timeouts on omap3430
On Tue, Apr 01, 2008 at 03:43:56PM +0300, ext Tony Lindgren wrote: * Tony Lindgren [EMAIL PROTECTED] [080331 17:30]: * Tony Lindgren [EMAIL PROTECTED] [080331 13:43]: * Tony Lindgren [EMAIL PROTECTED] [080328 10:41]: Hi all, This helps with the annoying I2C timeouts. Does anybody have an idea why the twl4030 chip does not like doing multiple transfers in a row? To me the only difference seems to be that clocks are idled between writing the twl4030 register and reading the register value. I'll push this today with a REVISIT comment added. Looks like this kills twl4030 interrupts, so I've reverted it. After looking into this problem a bit more, looks like twl4030 reads to anything in POWER ID (modules 0x10 and higher) will hang twl4030 eventually and I2C controller gets stuck in mode where STP never clears. Repeated reads to USB ID, AUD ID or AUX ID will not hang twl4030. I remember seeing something similar when doing the powerbutton code. Klaus Pedersen found out that leaving CFG_BOOT to its reset value solved the problem. Unfortunately this breaks MADC and USB afaics, so it's not a real solution. CFG_BOOT is programmed in power_companion_init(). Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: FW: [PATCH 00/05] 34XX cpu idle patches - core off
On Fri, Jun 27, 2008 at 05:27:48PM +0530, ext Rajendra Nayak wrote: Hi Peter, I have the CORE off working on top of Jouni's latest patch set posted on l-o. 2 issues which I saw due to which CORE OFF was broken 1) Control module registers were redefined with the same name in control.h while my patches defined them in cpuidle34xx.h. In control.h they were just offsets and in cpuidle34xx.h they were defined as physical address. While saving the control module context, the offset was getting passed to omap_readl resulting in a crash. 2) GPIO clocks disable was moved into SRAM code in Jouni's patch, which would not get executed in OFF path. Thanks. I'm testing them now. 013-TIPATCH-fix-core-off.patch patches include/asm/arch/control.h which doesn't exist on a non-configured kernel. It's better to have the patch modify include/asm-arm/arch-omap/control.h. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: FW: [PATCH 00/05] 34XX cpu idle patches - core off
Hi Rajendra, The patches still require some amount of cleaning, once Jouni posts his next set of workaround patches taking care of the sleep dependecy for PER, I will rework/clean these patches and then send it to the linux-omap list. I am still seeing some issues with debug uart responsiveness which I am looking into. Need to see if the wakeup is configured properly. That's what I'm seeing here as well. OMAP goes to off mode but UART wakeup seems to be broken. Thanks, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: FW: [PATCH 00/05] 34XX cpu idle patches - core off
If by responsiveness it is meant slowness of output (tx path) that' likely good news. It means your hitting interconnect clock stop often and thus getting into first large active mode savings state. This is the biggest step power drop for active states. If your UART looks good you probably are not hitting target states enough from idle. The UART's TX logic is not currently hooked into the wake up mechanism from clockstop (domain INACTIVE but ON, only RX an external IO events). As such to get good speed you need go to no-idle if there is TX work queued else you won't see TX interrupt events until the next wake up period, likely from GPTIMER0 at dynamic tick rate. * Expect to loose the 1st character on debug console as a wake up event. Unless you use RTS/CTS (configured as wakeups) as an early wake up path, you will lose the start bit when the system restarts. For things like bluetooth or other the protocol should re-transmit. If you mean your not waking that's something else. AFAIC it's not waking. Even when using keyboard autorepeat to send spaces or enter, nothing happens. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/11] OMAP3 CPUidle patches
Hi Rajendra, Not sure, but you can try with my .config while I try with yours. I was doing some more testing today, and I saw a hang after a while of idle activity with OFF being attempted multiple times. Using lauterbach showed me it being stuck up in prcm_interrupt_handler trying to clear MPU_IRQSTATUS. Looks like in the PRCM interrupt handler somehow PM_WKST1_CORE is not cleared (I see it set to 0x2000) and hence MPU_IRQSTATUS fails to clear. Ok. I disabled OneNAND support and now I get off mode on VDD2 as well. Consumption on VDD1 is 4uA and 32uA on VDD2. Unfortunately after the first wakeup, off mode is never reached again. Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/11] OMAP3 CPUidle patches
So Rajendra sent his uImage and it works quite ok what comes to off mode on my sdp board. I still see problems with serial console (slow) and on boot I need to generate manually interrupts to get it to boot. Otherwise board hangs at this point: eth0: link up Sending DHCP requests ., OK IP-Config: Got DHCP answer from 0.0.0.0, my address is 192.168.2.101 IP-Config: Complete: device=eth0, addr=192.168.2.101, mask=255.255.255.0, gw=192.168.2.1, host=192.168.2.101, domain=ntc.nokia.com, nis-domain=(none), bootserver=0.0.0.0, rootserver=172.22.146.197, rootpath= Looking up port of RPC 13/2 on 172.22.146.197 Looking up port of RPC 15/1 on 172.22.146.197 VFS: Mounted root (nfs filesystem). Freeing init memory: 108K Rajendra, are you still using .config file you sent to me? Are all the changes in your tree available in l-o list. I tried the same uImage here on my SDP. It goes to off nicely after bootup, but after using the console, VDD2 does not to off anymore. VDD1 does go to off. Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/09] OMAP PM interface implementation using Shared resource f/w
Hi Rajendra, Hi, The patches which follow implement the API's defined by Paul Walmsley as part of the OMAP PM Interface on OMAP3430sdp. Shared resource f/w is used for the underlying implementation. The following resources are modeled 1) MPU/CORE latency resources 2) Power Domain latency resources (One for each Power domain) 3) OPP/Freq resources (For DVFS) The below API from the OMAP PM interface is yet to be implemented. void omap_pm_set_min_bus_tput(struct device *dev, struct bus_type *bus, unsigned long r) I tried to apply this to linux-omap, but when compiling I get the following error message : arch/arm/mach-omap2/clockdomain.c:38:30: error: asm/arch/omap-pm.h: No such file or directory arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_clk_enable': arch/arm/mach-omap2/clockdomain.c:572: error: implicit declaration of function 'omap_pm_pwrdm_active' arch/arm/mach-omap2/clockdomain.c: In function 'omap2_clkdm_clk_disable': arch/arm/mach-omap2/clockdomain.c:626: error: implicit declaration of function 'omap_pm_pwrdm_inactive' make[1]: *** [arch/arm/mach-omap2/clockdomain.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Seems there is a file missing from the patchset. Thanks, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 04/09] OMAP PM srf implementation
Hi Rajendra,
+void omap_pm_set_min_bus_tput(struct device *dev, struct bus_type *bus,
+ unsigned long r)
According to Paul's prototypes this should be
void omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id,
unsigned long r)
+{
+ if (!dev) {
+ WARN_ON(1);
+ return;
+ };
+
+ if (r == 0)
+ pr_debug(OMAP PM: remove min bus tput constraint:
+ dev %p for bus %s\n, dev, bus-name);
+ else
+ pr_debug(OMAP PM: add min bus tput constraint:
+ dev %p for bus %s: rate %ld KiB\n, dev,
+ bus-name, r);
+
+ /*
+ * This code should model the bus and compute the required
+ * bus frequency, convert that to a VDD2 OPP ID, then set the VDD2
+ * OPP appropriately.
+ *
+ * TI CDP code can call constraint_set here on the VDD2 OPP.
+ */
+}
+
omap_pm_if_early_init and omap_pm_if_init are missing. I added dummy
functions for those.
With all of these changes it seems to work.
Cheers,
Peter.
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Re: [PATCH 04/09] OMAP PM srf implementation
Hi Rajendra, Yes, I probably was using an older omap-pm-noop patch from Paul. I did not refresh it since, the later one sent was again not the final one. I though I would refresh it once the final version is posted. Paul, Would you be posting another version of this with changes as suggested by Jouni? Rereading the mails about this function, it seems to me as the original proposal was to use struct bus_type *, but then Paul proposed to use the agent_id. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] PROTECT_KEY register is in the PM_MASTER module not in the PM_RECEIVER module
This patch fixes a write to the wrong address in the triton2 chip. Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- drivers/i2c/chips/twl4030-usb.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/i2c/chips/twl4030-usb.c b/drivers/i2c/chips/twl4030-usb.c index ab335ca..20858b5 100644 --- a/drivers/i2c/chips/twl4030-usb.c +++ b/drivers/i2c/chips/twl4030-usb.c @@ -586,7 +586,7 @@ static void twl4030_usb_ldo_init(struct twl4030_usb *twl) twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); /* disable access to power configuration registers */ - twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY); } static irqreturn_t twl4030_usb_irq(int irq, void *_twl) -- 1.5.3.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 5/9] TWL4030: read and write module ISRs to clear them at init
On Thu, Jul 17, 2008 at 07:34:52PM -0600, ext Paul Walmsley wrote: TWL4030 interrupt status register bits can be cleared in one of two ways: either by reading from the register, or by writing a 1 to the appropriate bit(s) in the register. This behavior can be altered at any time by the twlmodule_SIH_CTRL.COR register bit (clear-on-read). twl4030-core.c does not touch these *_SIH_CTRL registers during boot, and the TWL4030 TRM is deeply confused as to whether COR=1 means that the registers are cleared on reads, or cleared on writes. That's true. But reality is fortunately not so confused :) COR=1 means all IRQs are acknowledged when reading the corresponding ISR. COR=0 means you need to write 1 to the bits in the ISR for interrupts you want to acknowledge. Hope this helps, Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Set correct off mode polarity
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
#define MAX_DPLL_WAIT_TRIES100
+#define OFFMODE_POL(13)
+
struct vdd_prcm_config *curr_vdd1_prcm_set;
struct vdd_prcm_config *curr_vdd2_prcm_set;
static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
}
#endif
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
printk(KERN_INFO Clocking rate (Crystal/DPLL/ARM core):
%ld.%01ld/%ld/%ld MHz\n,
(osc_sys_ck.rate / 100), (osc_sys_ck.rate / 10) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
return -EINVAL;
}
-
if (clk == virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set-speed;
clk_set_rate(dpll1_clk, prcm_vdd-speed);
--
1.5.3.4
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[PATCH] Load triton2 scripts.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/Makefile|2 +-
drivers/i2c/chips/twl4030-power.c | 337 +
2 files changed, 338 insertions(+), 1 deletions(-)
create mode 100644 drivers/i2c/chips/twl4030-power.c
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 1f81ebd..a44e617 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP) += gpio_expander_omap.o
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
-obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o
twl4030-power.o
obj-$(CONFIG_TWL4030_GPIO) += twl4030-gpio.o
obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
obj-$(CONFIG_TWL4030_POWEROFF) += twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030-power.c
b/drivers/i2c/chips/twl4030-power.c
new file mode 100644
index 000..195c3c4
--- /dev/null
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -0,0 +1,337 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by Kalle Jokiniemi
+ * Peter De Schrijver [EMAIL PROTECTED]
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include linux/module.h
+#include linux/pm.h
+#include linux/i2c/twl4030.h
+
+#define PWR_P1_SW_EVENTS 0x10
+#define PWR_DEVOFF (10)
+
+#define PHY_TO_OFF_PM_MASTER(p)(p - 0x36)
+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECIEVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITIONPHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITIONPHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITIONPHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP 0x08
+
+#define ENABLE_WARMRESET (14)
+
+/* sequence script */
+
+#define END_OF_SCRIPT 0x3f
+
+#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12 PHY_TO_OFF_PM_MASTER(0x56)
+#defineR_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
+#defineR_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* Power bus message definitions */
+
+#define DEV_GRP_NULL 0x0
+#define DEV_GRP_P1 0x1
+#define DEV_GRP_P2 0x2
+#define DEV_GRP_P3 0x4
+
+#define RES_GRP_RES0x0
+#define RES_GRP_PP 0x1
+#define RES_GRP_RC 0x2
+#define RES_GRP_PP_RC 0x3
+#define RES_GRP_PR 0x4
+#define RES_GRP_PP_PR 0x5
+#define RES_GRP_RC_PR 0x6
+#define RES_GRP_ALL0x7
+
+#define RES_TYPE2_R0 0x0
+
+#define RES_TYPE_ALL 0x7
+
+#define RES_STATE_WRST 0xF
+#define RES_STATE_ACTIVE 0xE
+#define RES_STATE_SLEEP0x8
+#define RES_STATE_OFF 0x0
+
+/*
+* Power Bus Message Format
+*
+* Broadcast Message (16 Bits)
+* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
+* RES_STATE[3:0]
+*
+* Singular Message (16 Bits)
+* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
+*
+*/
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+ (devgrp 13 | 1 12 | grp 9 | type2 7 | type 4 | state)
+
+#define MSG_SINGULAR(devgrp, id, state) \
+ (devgrp 13 | 0 12 | id 4 | state)
+
+#define R_PROTECT_KEY 0x0E
+#define KEY_1 0xC0
+#define KEY_2 0x0C
+
+struct triton_ins {
+ u16 pmb_message;
+ u8 delay;
+};
+
+
+#define CONFIG_DISABLE_HFCLK 1
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
+
+struct triton_ins sleep_on_seq[] __initdata = {
+ {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
+ {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2
[PATCH] Add SYSOFFMODE option.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/plat-omap/Kconfig |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index d7b34ff..6f891b7 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -73,6 +73,12 @@ config OMAP_SMARTREFLEX compensation for VDD1 and VDD2, user must write 1 to /sys/power/sr_vddX_autocomp, where X is 1 or 2. +config OMAP_SYSOFFMODE +bool OFF mode support + depends on ARCH_OMAP34XX + help + Say Y if you want to allow OMAP to enter OFF mode. + config OMAP_SMARTREFLEX_TESTING bool Smartreflex testing support depends on OMAP_SMARTREFLEX -- 1.5.3.4 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Set correct off mode polarity
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
#define MAX_DPLL_WAIT_TRIES100
+#define OFFMODE_POL(13)
+
struct vdd_prcm_config *curr_vdd1_prcm_set;
struct vdd_prcm_config *curr_vdd2_prcm_set;
static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
}
#endif
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
printk(KERN_INFO Clocking rate (Crystal/DPLL/ARM core):
%ld.%01ld/%ld/%ld MHz\n,
(osc_sys_ck.rate / 100), (osc_sys_ck.rate / 10) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
return -EINVAL;
}
-
if (clk == virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set-speed;
clk_set_rate(dpll1_clk, prcm_vdd-speed);
--
1.5.3.4
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RFC: OMAP3 SYS_OFF_MODE support
The following patch set introduces support for the OMAP3 SYS_OFF_MODE signal. This will cause a properly programmed triton2 to shutdown the VDD1 and VDD2 regulators when both core and MPU powerdomain are in off state. The patches includes programming triton2 with the appropriate scripts for the SDP3430 board. By default the OMAP3 polarity of the SYS_OFF_MODE signal is inverted compared to what triton2 expects. This means the polarity needs to be changed before the triton2 scripts are activated, otherwise the system will crash. At the moment this is done in omap2_clk_init as this function is called before triton2 is initialized. Better suggestions are welcome. Thanks to Kalle Jokiniemi for doing the initial patch and test work. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] Set correct off mode polarity
On Mon, Jul 21, 2008 at 08:22:31PM +0300, ext Felipe Balbi wrote: Hi, style comments inlined. On Mon, Jul 21, 2008 at 07:02:02PM +0300, Peter 'p2' De Schrijver wrote: +#define OFFMODE_POL(13) add spaces after 1 and before 3 (1 3) - unnecessary change ?!? ? This change is necessary, otherwise the system dies as soon as the triton2 sysoffmode scripts become active. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: OMAP3 SYS_OFF_MODE support
On Tue, Jul 22, 2008 at 07:56:10PM +0530, ext Rangasamy, Devaraj wrote: Currently sr_configure_vc() is the only dedicated API to configure Voltage controller parameter. But still SYSOFF specific configuration shall be moved to prcm init. Do you suggest to move all the voltage control initialization to prcm init ? Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] power off on state counter infrastructure
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomain.c | 48 +-
include/asm-arm/arch-omap/powerdomain.h |9 +-
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 7615f9d..721f73c 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,27 @@ static struct powerdomain *_pwrdm_deps_lookup(struct
powerdomain *pwrdm,
return pd-pwrdm;
}
+static int pwr_domain_save_state_cb(struct powerdomain *pwrdm, void *user)
+{
+ pwrdm_save_state(pwrdm);
+
+ return 0;
+}
+
+static int pwr_domain_count_off_mode_cb(struct powerdomain *pwrdm, void *user)
+{
+ int prev;
+
+ prev = pwrdm_read_prev_pwrst(pwrdm);
+
+ if (prev != PWRDM_POWER_OFF pwrdm-state != prev)
+pwrdm-offstate_count++;
+
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+
+ return 0;
+}
+
/* Public functions */
@@ -217,7 +238,7 @@ struct powerdomain *pwrdm_lookup(const char *name)
* anything else to indicate failure; or -EINVAL if the function
* pointer is null.
*/
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), void
*user)
{
struct powerdomain *temp_pwrdm;
unsigned long flags;
@@ -228,7 +249,7 @@ int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
read_lock_irqsave(pwrdm_rwlock, flags);
list_for_each_entry(temp_pwrdm, pwrdm_list, node) {
- ret = (*fn)(temp_pwrdm);
+ ret = (*fn)(temp_pwrdm, user);
if (ret)
break;
}
@@ -1110,4 +1131,27 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
+void pwrdm_save_state(struct powerdomain *pwrdm)
+{
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+}
+
+void pwrdm_check_off_mode(struct powerdomain *pwrdm)
+{
+ int state;
+
+ state = pwrdm_read_pwrst(pwrdm);
+ if (pwrdm-state == PWRDM_POWER_OFF state == PWRDM_POWER_ON)
+ pwrdm-offstate_count++;
+}
+
+void pwrdm_save_state_all(void)
+{
+ pwrdm_for_each(pwr_domain_save_state_cb, NULL);
+}
+
+void pwrdm_count_off_mode(void)
+{
+ pwrdm_for_each(pwr_domain_count_off_mode_cb, NULL);
+}
diff --git a/include/asm-arm/arch-omap/powerdomain.h
b/include/asm-arm/arch-omap/powerdomain.h
index 1cd8942..19ad6fd 100644
--- a/include/asm-arm/arch-omap/powerdomain.h
+++ b/include/asm-arm/arch-omap/powerdomain.h
@@ -117,6 +117,8 @@ struct powerdomain {
struct list_head node;
+ int state;
+ u32 offstate_count;
};
@@ -126,7 +128,8 @@ int pwrdm_register(struct powerdomain *pwrdm);
int pwrdm_unregister(struct powerdomain *pwrdm);
struct powerdomain *pwrdm_lookup(const char *name);
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -165,4 +168,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
+void pwrdm_save_state(struct powerdomain *pwrdm);
+void pwrdm_check_off_mode(struct powerdomain *pwrdm);
+void pwrdm_save_state_all(void);
+void pwrdm_count_off_mode(void);
#endif
--
1.5.6.3
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[PATCH 3/3] Add hooks for counting off on power transitions
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clockdomain.c | 10 ++
arch/arm/mach-omap2/pm34xx.c |6 +-
2 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index e975ca1..fac5778 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -571,6 +571,11 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
/*Hook to inform the OMAP PM layer that the pwrdm has become active */
omap_pm_pwrdm_active(clkdm-pwrdm);
+ if (clkdm != NULL clkdm-pwrdm != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm);
+ pwrdm_check_off_mode(clkdm-pwrdm);
+ }
+
return 0;
}
@@ -625,6 +630,11 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
/*Hook to inform the OMAP PM layer that the pwrdm has become inactive */
omap_pm_pwrdm_inactive(clkdm-pwrdm);
+ if (clkdm != NULL clkdm-pwrdm != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm);
+ pwrdm_save_state(clkdm-pwrdm);
+ }
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8b6b09e..f70035a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -269,6 +269,8 @@ void omap_sram_idle(void)
return;
}
+ pwrdm_save_state_all();
+
/* NEON control */
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
set_pwrdm_state(neon_pwrdm, mpu_next_state);
@@ -346,6 +348,8 @@ void omap_sram_idle(void)
}
omap2_gpio_resume_after_retention();
}
+
+ pwrdm_count_off_mode();
}
static int omap3_fclks_active(void)
@@ -848,7 +852,7 @@ int __init omap3_pm_init(void)
goto err2;
}
- ret = pwrdm_for_each(pwrdms_setup);
+ ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
printk(KERN_ERR Failed to setup powerdomains\n);
goto err2;
--
1.5.6.3
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[PATCH 1/3] Power off on state counter debugging
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile |2 +-
arch/arm/mach-omap2/off-state-counter-debug.c | 50 +
2 files changed, 51 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/off-state-counter-debug.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0d8507c..a48f832 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,7 +5,7 @@
# Common support
obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
- clockdomain.o
+ clockdomain.o off-state-counter-debug.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap2/off-state-counter-debug.c
b/arch/arm/mach-omap2/off-state-counter-debug.c
new file mode 100644
index 000..7db54b6
--- /dev/null
+++ b/arch/arm/mach-omap2/off-state-counter-debug.c
@@ -0,0 +1,50 @@
+#include linux/debugfs.h
+#include linux/seq_file.h
+#include asm/arch/powerdomain.h
+
+
+int show_off_mode_count(struct powerdomain *pwrdm, void *user)
+{
+ struct seq_file *s = (struct seq_file *)user;
+
+ if (strcmp(pwrdm-name, emu_pwrdm)
+ strcmp(pwrdm-name, wkup_pwrdm))
+ seq_printf(s, %s : %d\n, pwrdm-name, pwrdm-offstate_count);
+
+ return 0;
+}
+
+int show_off_mode_counters(struct seq_file *s, void *unused)
+{
+ pwrdm_for_each(show_off_mode_count, s);
+
+ return 0;
+}
+
+static int off_mode_counter_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, show_off_mode_counters, inode-i_private);
+}
+
+static const struct file_operations debug_fops = {
+ .open = off_mode_counter_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int __init off_mode_counter_debug(void)
+{
+ struct dentry *d;
+
+ d = debugfs_create_dir(off_mode_counters, NULL);
+ if (IS_ERR(d))
+ return PTR_ERR(d);
+
+ debugfs_create_file(count, S_IRUGO,
+ d, NULL, debug_fops);
+
+ return 0;
+}
+
+late_initcall(off_mode_counter_debug);
--
1.5.6.3
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Re: [PATCH 0/3] Implement powerdomain off on state counters
On Thu, Jul 24, 2008 at 04:00:31PM +0300, Peter 'p2' De Schrijver wrote: This patchset implement counters to count the number of off to on state transitions in a powerdomain. These counters will be made available to drivers in a later patchset to allow them to make a better informed decision wether to restore the hardware registers or not. Thanks to Tero Kristo for providing the basis of this patch in the form of the PM Debug counters. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] Add PM early init
This patchset add an early init function to initialize the voltage controller and the off mode polarity before the drivers depending on these features are enabled. Peter 'p2' De Schrijver (2): Move voltage controller configuration to pm34xx.c Add early init for voltage controller configuration and off mode polarity. arch/arm/mach-omap2/pm34xx.c | 71 + arch/arm/mach-omap2/smartreflex.c | 60 --- 2 files changed, 71 insertions(+), 60 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] Add early init for voltage controller configuration and off mode polarity.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c | 71 ++
1 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 8b6b09e..06eae7e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -46,6 +46,8 @@
#define OMAP3430_PRM_RSTST \
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OFFMODE_POL(1 3)
+
u32 context_mem[128];
struct power_state {
@@ -707,6 +709,64 @@ static void __init prcm_setup_regs(void)
OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
}
+static void __init configure_vc(void)
+{
+ prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
+ (R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
+
+ prm_write_mod_reg((R_VDD2_SR_CONTROL OMAP3430_VOLRA1_SHIFT) |
+ (R_VDD1_SR_CONTROL OMAP3430_VOLRA0_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_RET OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL0_OFF OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON
+ OMAP3430_VC_CMD_ON_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_RET OMAP3430_VC_CMD_RET_SHIFT) |
+ (OMAP3430_VC_CMD_VAL1_OFF OMAP3430_VC_CMD_OFF_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
+ OMAP3430_GR_MOD,
+ OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+ /* Setup voltctrl and other setup times */
+
+#ifdef CONFIG_OMAP_SYSOFFMODE
+ prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
+ OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_CLKSETUP_OFFSET);
+ prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
+ OMAP3430_SETUP_TIME2_SHIFT) |
+ (OMAP3430_VOLTSETUP_TIME1
+ OMAP3430_SETUP_TIME1_SHIFT),
+ OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
+
+ prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTOFFSET_OFFSET);
+ prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTSETUP2_OFFSET);
+#else
+ prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
+ OMAP3_PRM_VOLTCTRL_OFFSET);
+#endif
+
+}
+
void omap3_save_per_ctx(void)
{
omap_gpio_save();
@@ -1009,3 +1069,14 @@ void save_scratchpad_contents(void)
*(scratchpad_address++) = (u32) sdram_context_address;
}
+static int __init omap3_pm_early_init(void)
+{
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
+ configure_vc();
+
+ return 0;
+}
+
+arch_initcall(omap3_pm_early_init);
--
1.5.6.3
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[PATCH 1/2] Move voltage controller configuration to pm34xx.c
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/smartreflex.c | 60 -
1 files changed, 0 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c
b/arch/arm/mach-omap2/smartreflex.c
index b41fe96..7e4f9a4 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -362,64 +362,6 @@ static void sr_configure_vp(int srid)
}
}
-static void sr_configure_vc(void)
-{
- prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
- (R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
-
- prm_write_mod_reg((R_VDD2_SR_CONTROL OMAP3430_VOLRA1_SHIFT) |
- (R_VDD1_SR_CONTROL OMAP3430_VOLRA0_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL0_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
-
- prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON
- OMAP3430_VC_CMD_ON_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_ONLP OMAP3430_VC_CMD_ONLP_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_RET OMAP3430_VC_CMD_RET_SHIFT) |
- (OMAP3430_VC_CMD_VAL1_OFF OMAP3430_VC_CMD_OFF_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
-
- prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VC_CH_CONF_OFFSET);
-
- prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
- OMAP3430_GR_MOD,
- OMAP3_PRM_VC_I2C_CFG_OFFSET);
-
- /* Setup voltctrl and other setup times */
- /* XXX CONFIG_SYSOFFMODE has not been implemented yet */
-#ifdef CONFIG_OMAP_SYSOFFMODE
- prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET |
- OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTCTRL_OFFSET);
-
- prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_CLKSETUP_OFFSET);
- prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
- OMAP3430_SETUP_TIME2_SHIFT) |
- (OMAP3430_VOLTSETUP_TIME1
- OMAP3430_SETUP_TIME1_SHIFT),
- OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
-
- prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTOFFSET_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTSETUP2_OFFSET);
-#else
- prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
- OMAP3_PRM_VOLTCTRL_OFFSET);
-#endif
-
-}
-
static void sr_configure(struct omap_sr *sr)
{
u32 sr_config;
@@ -845,8 +787,6 @@ static int __init omap3_sr_init(void)
sr_set_nvalues(sr2);
sr_configure_vp(SR2);
- sr_configure_vc();
-
/* Enable SR on T2 */
ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
R_DCDC_GLOBAL_CFG);
--
1.5.6.3
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Re: BeagleBoard not resuming from uart with latest pm-core ?
On Wed, Nov 10, 2010 at 06:32:53PM +0100, ext Kevin Hilman wrote: Jean Pihet jean.pi...@newoldbits.com writes: l-o is currently broken wrt to suspend and idle. Solutions are being worked on for the moment. Kevin, are there solutions available yet? The solution to your previous problem (ensuring runtime PM transitions work during system PM) is included in my pm-core branch, but is not yet the final solution. I've been disussing this issue with the runtime PM maintainers for a final solution. Until then, I will carry this in pm-core. The other problem that I'm aware of so far I've only seen on boards with UART2 console (beagle, Overo, n900.) The printk messages that warn of N900 uses UART3 as its console... UART2 is bluetooth iirc. CHeers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/13] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
On Fri, Nov 19, 2010 at 10:46:19AM +0100, ext Jean Pihet wrote: On Fri, Nov 19, 2010 at 2:54 AM, Nishanth Menon n...@ti.com wrote: From: Richard Woodruff r-woodru...@ti.com Analysis in TI kernel with ETM showed that using cache mapped flush in kernel instead of SO mapped flush cost drops by 65% (3.39mS down to 1.17mS) for clean_l2 which is used during sleep sequences. Overall: - speed up - unfortunately there isn't a good alternative flush method today - code reduction and less maintenance and potential bug in unmaintained code This also fixes the bug with the clean_l2 function usage. Reported-by: Tony Lindgren t...@atomide.com [...@ti.com: ported rkw's proposal to 2.6.37-rc2] Signed-off-by: Nishanth Menon n...@ti.com Signed-off-by: Richard Woodruff r-woodru...@ti.com --- Side note: just dcache needs to be flushed based on inputs from TI internal team arch/arm/mach-omap2/sleep34xx.S | 79 ++ 1 files changed, 13 insertions(+), 66 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2fb205a..8f207b2 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -520,72 +520,17 @@ clean_caches: cmp r9, #1 /* Check whether L2 inval is required or not*/ bne skip_l2_inval clean_l2: - /* read clidr */ - mrc p15, 1, r0, c0, c0, 1 - /* extract loc from clidr */ - ands r3, r0, #0x700 - /* left align loc bit field */ - mov r3, r3, lsr #23 - /* if loc is 0, then no need to clean */ - beq finished - /* start clean at cache level 0 */ - mov r10, #0 -loop1: - /* work out 3x current cache level */ - add r2, r10, r10, lsr #1 - /* extract cache type bits from clidr*/ - mov r1, r0, lsr r2 - /* mask of the bits for current cache only */ - and r1, r1, #7 - /* see what cache we have at this level */ - cmp r1, #2 - /* skip if no cache, or just i-cache */ - blt skip - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - /* isb to sych the new cssrcsidr */ - isb - /* read the new csidr */ - mrc p15, 1, r1, c0, c0, 0 - /* extract the length of the cache lines */ - and r2, r1, #7 - /* add 4 (line length offset) */ - add r2, r2, #4 - ldr r4, assoc_mask - /* find maximum number on the way size */ - ands r4, r4, r1, lsr #3 - /* find bit position of way size increment */ - clz r5, r4 - ldr r7, numset_mask - /* extract max number of the index size*/ - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 - /* create working copy of max way size*/ -loop3: - /* factor way and cache number into r11 */ - orr r11, r10, r9, lsl r5 - /* factor index number into r11 */ - orr r11, r11, r7, lsl r2 - /*clean invalidate by set/way */ - mcr p15, 0, r11, c7, c10, 2 - /* decrement the way*/ - subs r9, r9, #1 - bge loop3 - /*decrement the index */ - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - /* increment cache number */ - cmp r3, r10 - bgt loop1 -finished: - /*swith back to cache level 0 */ - mov r10, #0 - /* select current cache level in cssr */ - mcr p15, 2, r10, c0, c0, 0 - isb + /* + * jump out to kernel flush routine + * - resue that code is better Typo: 'reuse' + * - it executes in a cached space so is faster than refetch per-block + * - should be faster and will change with kernel + * - 'might' have to copy address, load and jump to it + */ + ldr r1, kernel_flush + mov lr, pc + bx r1 It is simpler and more efficient to use: bl v7_flush_dcache_all This doesn't work from SRAM though, because the linker will generate a PC relative branch which is wrong if the code is moved to SRAM at runtime. So the original version needs to stay :) Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote: -Original Message- From: Jean Pihet [mailto:jean.pi...@newoldbits.com] Sent: Friday, November 19, 2010 9:37 AM On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com wrote: On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote: * Jean Pihet jean.pi...@newoldbits.com [101118 10:06]: On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote: About the DPLL lock: 1) wait_sdrc_ok is only called when back from the non-OFF modes, 2) I checked that when running wait_sdrc_ok the CORE is already out of idle and the DPLL is already locked. Note: l-o code has no support for the voltages OFF and the external clocks OFF. What to conclude from 1) and 2)? In my test setup ot looks like wait_sdrc_ok is of no use, but I agree this a premature conclusion. Yeah we should figure out in which cases wait_sdrc_ok is needed. BTW, are you sure you're hitting core idle in your tests? Yes it is OK from the console messages and the counters values in /debug/pm_debug/count. Let me confirm asap with the PRCM registers dump. Here is what I experimented: 1) added a cache flush (v7_flush_kern_cache_all) just before WFI, in all cases, 2) checked the real state entered in low power mode from the console messages, the output of /debug/pm_debug/count and PRCM registers dump 2) is OK, which means that the RET and OFF modes are correctly hit. Can I conclude from 1) that the wake-up code is not running from the cache in RETention? [Derrick, David] To add some context to the wait_sdrc_ok function and why it was added: wait_sdrc_ok was added because the DLL takes 500 L3 clock cycles to lock. So you do not want to go back to DDR before DLL is locked. Also, we found some times DLL never locked so we introduced the DLL kick procedure to force it to lock. The root cause for the DLL not locking has been found though and a workaround implemented. So it should work now :) That still leaves the 500 L3 cycle delay though. Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
On Mon, Nov 22, 2010 at 05:03:59PM +0100, ext Kevin Hilman wrote: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes: On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote: -Original Message- From: Jean Pihet [mailto:jean.pi...@newoldbits.com] Sent: Friday, November 19, 2010 9:37 AM On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com wrote: On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote: * Jean Pihet jean.pi...@newoldbits.com [101118 10:06]: On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote: About the DPLL lock: 1) wait_sdrc_ok is only called when back from the non-OFF modes, 2) I checked that when running wait_sdrc_ok the CORE is already out of idle and the DPLL is already locked. Note: l-o code has no support for the voltages OFF and the external clocks OFF. What to conclude from 1) and 2)? In my test setup ot looks like wait_sdrc_ok is of no use, but I agree this a premature conclusion. Yeah we should figure out in which cases wait_sdrc_ok is needed. BTW, are you sure you're hitting core idle in your tests? Yes it is OK from the console messages and the counters values in /debug/pm_debug/count. Let me confirm asap with the PRCM registers dump. Here is what I experimented: 1) added a cache flush (v7_flush_kern_cache_all) just before WFI, in all cases, 2) checked the real state entered in low power mode from the console messages, the output of /debug/pm_debug/count and PRCM registers dump 2) is OK, which means that the RET and OFF modes are correctly hit. Can I conclude from 1) that the wake-up code is not running from the cache in RETention? [Derrick, David] To add some context to the wait_sdrc_ok function and why it was added: wait_sdrc_ok was added because the DLL takes 500 L3 clock cycles to lock. So you do not want to go back to DDR before DLL is locked. Also, we found some times DLL never locked so we introduced the DLL kick procedure to force it to lock. The root cause for the DLL not locking has been found though and a workaround implemented. So it should work now :) Is the workaround for this reflected in Nishanth's series? No. It seems not. The workaround needs VDD2 voltage scaling which seems to be missing now from l-o ? Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/13] OMAP3: PM: Errata i581 suppport: dll kick strategy
On Wed, Nov 24, 2010 at 05:51:50PM +0100, ext Sripathy, Vishwanath wrote: Nishant, On Fri, Nov 19, 2010 at 7:24 AM, Nishanth Menon n...@ti.com wrote: From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com Errata i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: this is not a complete workaround implementation as recommended by the silicon errata. this is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. How does this WA work when Core enters off mode? SRAM contents are lost when Core enters off. So how this code is copied to SRAM upon wakeup? Where is this code placed when Core entered off mode? This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed. Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Inventra Highspeed Dual Role Controller on TI OMAP 3503
that's no official documentation. It's better to check device's datasheet when you have such questions. Besides, imagine the pain it would be to patch that Kconfig entry everytime we have a new release of an OMAP processor. Maybe it would be better to say something like: available on many OMAP processors instead of mentioning each and every one of them. It would be even better if the availability could be discovered at runtime. Cheers, Peter. -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
On Mon, Dec 20, 2010 at 11:23:27AM +0100, ext Jean Pihet wrote: On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon n...@ti.com wrote: From: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com Erratum i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: *) This is not a complete workaround implementation as recommended by the silicon erratum. this is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. *) This code is mostly important for inactive and retention. The ROM code waits for the maximum dll lock time when resuming from off mode. So for off mode this code isn't really needed. This should eventually get refactored as part of cleanups to sleep34xx.S Cc: Kevin Hilman khil...@deeprootsystems.com Cc: Tony Lindgren t...@atomide.com Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- (no change done, posting for completeness of the series) v2: https://patchwork.kernel.org/patch/365252/ typo correction- erratum, support, added comment from Peter from the thread to commit message v1: http://marc.info/?l=linux-omapm=129013172525234w=2 arch/arm/mach-omap2/sleep34xx.S | 52 +++--- 1 files changed, 47 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2c20fcf..3fbd1e5 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -42,6 +42,7 @@ OMAP3430_PM_PREPWSTST) #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) #define SRAM_BASE_P 0x4020 #define CONTROL_STAT 0x480022F0 #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is @@ -554,31 +555,67 @@ skip_l2_inval: /* Make sure SDRC accesses are ok */ wait_sdrc_ok: + +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */ + ldr r4, cm_idlest_ckgen +wait_dpll3_lock: + ldr r5, [r4] + tst r5, #1 + beq wait_dpll3_lock + ldr r4, cm_idlest1_core +wait_sdrc_ready: ldr r5, [r4] - and r5, r5, #0x2 - cmp r5, #0 - bne wait_sdrc_ok + tst r5, #0x2 + bne wait_sdrc_ready + /* allow DLL powerdown upon hw idle req */ ldr r4, sdrc_power ldr r5, [r4] bic r5, r5, #0x40 str r5, [r4] -wait_dll_lock: +is_dll_in_lock_mode: + /* Is dll in lock mode? */ ldr r4, sdrc_dlla_ctrl ldr r5, [r4] tst r5, #0x4 bxne lr /* wait till dll locks */ - ldr r4, sdrc_dlla_status +wait_dll_lock_timed: + ldr r4, wait_dll_lock_counter + add r4, r4, #1 + str r4, wait_dll_lock_counter + ldr r4, sdrc_dlla_status + mov r6, #8 /* Wait 20uS for lock */ +wait_dll_lock: + subs r6, r6, #0x1 + beq kick_dll It would be good to have more comments on the code flow here: - what are wait_dll_lock_counter and kick_counter used for? For debugging and statistics. So you can find out how many times a 'kick' was needed. - what is the timing based on? Why 20uS for the wait time? This is the maximum lock time of the dll according to TI for OMAP3430. - jumping back and forth to kick_dll and wait_dll_lock_timed is confusing. ldr r5, [r4] and r5, r5, #0x4 cmp r5, #0x4 bne wait_dll_lock bx lr + /* disable/reenable DLL if not locked */ +kick_dll: + ldr r4, sdrc_dlla_ctrl + ldr r5, [r4] + mov r6, r5 + bic r6, #(13) /* disable dll */ + str r6, [r4] + dsb + orr r6, r6, #(13) /* enable dll */ + str r6, [r4] + dsb + ldr r4, kick_counter + add r4, r4, #1 + str r4, kick_counter + b wait_dll_lock_timed + cm_idlest1_core: .word CM_IDLEST1_CORE_V +cm_idlest_ckgen: + .word CM_IDLEST_CKGEN_V sdrc_dlla_status: .word SDRC_DLLA_STATUS_V sdrc_dlla_ctrl: @@ -615,5 +652,10 @@ control_stat: .word CONTROL_STAT kernel_flush: .word v7_flush_dcache_all + /* these 2 words need to be at the end !!! */ +kick_counter: + .word 0 +wait_dll_lock_counter: + .word 0 Why do they need to be at the end? Also, at the end
[PATCH 1/1] Save sram context after changing MPU, DSP or core clocks
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/clock34xx.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index d97d5a9..962ce56 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -911,6 +911,9 @@ printk(%s set to %luHz intended rate %luHz\n,dpll2_clk-name,clk_get_rate(dpll clk_set_rate(dpll3_clk, prcm_vdd-rate); curr_vdd2_prcm_set = prcm_vdd; } + + omap3_save_scratchpad_contents(); + return 0; } -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/1] Save sram context after changing MPU, DSP or core clocks
This patch saves the sram context again after a MPU,DSP or core clock frequency change. This is necessary so the rom code can restore the correct DPLL settings when resuming from off mode. Thanks to Rajendra Nayak for suggesting the problem and coming up with the same fix at about the same time. Peter 'p2' De Schrijver (1): Save sram context after changing MPU, DSP or core clocks arch/arm/mach-omap2/clock34xx.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] Debobs control macro fix
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/plat-omap/include/mach/control.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index 9b06365..759fb71 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -152,7 +152,7 @@ #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ - + ((i) 1) * 4 + (!(i) 1) * 2) + + ((i) 1) * 4 + (!(i 1)) * 2) #define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) #define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) #define OMAP343X_CONTROL_DSS_DPLL_SPREADING(OMAP2_CONTROL_GENERAL + 0x01E0) -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] Fix omap_getspeed.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |1 +
arch/arm/plat-omap/cpu-omap.c |6 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index f771b56..da27e49 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -938,6 +938,7 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
if (clk == virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set-rate;
+ clk-rate = prcm_vdd-rate;
clk_set_rate(dpll1_clk, prcm_vdd-rate);
clk_set_rate(dpll2_clk, dsp_opps[index].rate);
curr_vdd1_prcm_set = prcm_vdd;
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index ae0817d..0a7ce46 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -146,6 +146,12 @@ static int __init omap_cpu_init(struct cpufreq_policy
*policy)
VERY_HI_RATE) / 1000;
}
+ clk_set_rate(mpu_clk, policy-cpuinfo.max_freq * 1000);
+
+ policy-min = policy-cpuinfo.min_freq;
+ policy-max = policy-cpuinfo.max_freq;
+ policy-cur = omap_getspeed(0);
+
/* FIXME: what's the actual transition time? */
policy-cpuinfo.transition_latency = 10 * 1000 * 1000;
return 0;
--
1.5.6.3
--
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[PATCH 0/2] Bug fixes for DVFS
The following patchset fixes some smaal bugs in cpufreq for OMAP3. The first patch fixes omap_getspeed to return meaningful values. The second patch makes sure the omap cpufreq driver is initialized after the cpufreq frameworks and governors are initialized. Peter 'p2' De Schrijver (2): Fix omap_getspeed. Make sure omap cpufreq driver initializes after cpufreq framework and governors arch/arm/mach-omap2/clock34xx.c |1 + arch/arm/plat-omap/cpu-omap.c |8 +++- 2 files changed, 8 insertions(+), 1 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/1] Save sram context after changing MPU, DSP or core clocks
On Fri, Dec 05, 2008 at 11:49:03AM +0200, Kristo Tero (Nokia-D/Tampere) wrote: Hi Peter, This patch causes linker error without CONFIG_PM option, should add #ifdef:s around the call to omap3_save_scratchpad_contents(); That looks a bit ugly though :( Cheers, Peter -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Wait for SDRC ready iso a blind delay
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
---
arch/arm/mach-omap2/sleep34xx.S | 50 --
1 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 0c33e30..d29c180 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -38,6 +38,8 @@
#define PM_PREPWSTST_CORE_P0x48306AE8
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
+#define CM_IDLEST1_CORE_V IO_ADDRESS(OMAP3430_CM_BASE + 0x220)
+
/*
* This is the physical address of the register as specified
* by the _P. To be used while the MMU is still disabled.
@@ -57,6 +59,8 @@
#define SDRC_MR_1_P(OMAP343X_SDRC_BASE + SDRC_MR_1)
#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
#define SDRC_MANUAL_1_P(OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
+#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
+#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -192,7 +196,7 @@ loop:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
@@ -651,21 +655,41 @@ skip_l2_inval:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
/* restore regs and return */
ldmfd sp!, {r0-r12, pc}
-i_dll_wait:
- ldr r4, clk_stabilize_delay
-
-i_dll_delay:
- subsr4, r4, #0x1
- bne i_dll_delay
- ldr r4, sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
- bx lr
+/* Make sure SDRC accesses are ok */
+wait_sdrc_ok:
+ldr r4, cm_idlest1_core
+ldr r5, [r4]
+and r5, r5, #0x2
+cmp r5, #0
+bne wait_sdrc_ok
+ldr r4, sdrc_power
+ldr r5, [r4]
+bic r5, r5, #0x40
+str r5, [r4]
+wait_dll_lock:
+/* Is dll in lock mode? */
+ldr r4, sdrc_dlla_ctrl
+ldr r5, [r4]
+tst r5, #0x4
+bxnelr
+/* wait till dll locks */
+ldr r4, sdrc_dlla_status
+ldr r5, [r4]
+and r5, r5, #0x4
+cmp r5, #0x4
+bne wait_dll_lock
+bx lr
+
+cm_idlest1_core:
+ .word CM_IDLEST1_CORE_V
+sdrc_dlla_status:
+ .word SDRC_DLLA_STATUS_V
+sdrc_dlla_ctrl:
+ .word SDRC_DLLA_CTRL_V
pm_prepwstst_core:
.word PM_PREPWSTST_CORE_V
pm_prepwstst_core_p:
--
1.5.6.3
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[PATCH] Don't scale voltage in C1 state
This patch prevents VDD1 and VDD2 to go to the lowest OPP when entering C1. It improves wakeup latency from 600us to about 50us. Now with signoff :) Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- arch/arm/mach-omap2/pm34xx.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b0b2188..87ef55e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -1052,7 +1052,7 @@ static void __init configure_vc(void) OMAP3_PRM_VC_I2C_CFG_OFFSET); /* Setup voltctrl and other setup times */ - prm_write_mod_reg(OMAP3430_AUTO_RET | OMAP3430_AUTO_SLEEP, + prm_write_mod_reg(OMAP3430_AUTO_RET, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD, -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Wait for SDRC ready iso a blind delay
This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.
Now with signoff :)
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/sleep34xx.S | 51 +--
1 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 0c33e30..33ee85b 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -30,6 +30,7 @@
#include mach/pm.h
#include mach/control.h
+#include cm.h
#include prm.h
#include sdrc.h
@@ -38,6 +39,8 @@
#define PM_PREPWSTST_CORE_P0x48306AE8
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST)
+#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
+
/*
* This is the physical address of the register as specified
* by the _P. To be used while the MMU is still disabled.
@@ -57,6 +60,8 @@
#define SDRC_MR_1_P(OMAP343X_SDRC_BASE + SDRC_MR_1)
#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
#define SDRC_MANUAL_1_P(OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
+#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
+#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -192,7 +197,7 @@ loop:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
@@ -651,21 +656,41 @@ skip_l2_inval:
nop
nop
nop
- bl i_dll_wait
+ bl wait_sdrc_ok
/* restore regs and return */
ldmfd sp!, {r0-r12, pc}
-i_dll_wait:
- ldr r4, clk_stabilize_delay
-
-i_dll_delay:
- subsr4, r4, #0x1
- bne i_dll_delay
- ldr r4, sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
- bx lr
+/* Make sure SDRC accesses are ok */
+wait_sdrc_ok:
+ldr r4, cm_idlest1_core
+ldr r5, [r4]
+and r5, r5, #0x2
+cmp r5, #0
+bne wait_sdrc_ok
+ldr r4, sdrc_power
+ldr r5, [r4]
+bic r5, r5, #0x40
+str r5, [r4]
+wait_dll_lock:
+/* Is dll in lock mode? */
+ldr r4, sdrc_dlla_ctrl
+ldr r5, [r4]
+tst r5, #0x4
+bxnelr
+/* wait till dll locks */
+ldr r4, sdrc_dlla_status
+ldr r5, [r4]
+and r5, r5, #0x4
+cmp r5, #0x4
+bne wait_dll_lock
+bx lr
+
+cm_idlest1_core:
+ .word CM_IDLEST1_CORE_V
+sdrc_dlla_status:
+ .word SDRC_DLLA_STATUS_V
+sdrc_dlla_ctrl:
+ .word SDRC_DLLA_CTRL_V
pm_prepwstst_core:
.word PM_PREPWSTST_CORE_V
pm_prepwstst_core_p:
--
1.5.6.3
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[PATCH 0/1] Do a warm reboot instead of a cold reboot
This patch makes arch_reset do a warm reboot instead of a cold reboot. This is necessary because otherwise the system does not reboot reliably when disabling CLKEN in retention. Note : Unfortuately this breaks retention :( IVA2, PER and CORE don't go to retention after reboot. Peter 'p2' De Schrijver (1): Do a soft reboot instead of a cold boot arch/arm/mach-omap2/prcm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] Do a warm reboot instead of a cold boot
This patch makes omap_prcm_arch_reset do a warm reboot instead of a cold boot Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com --- arch/arm/mach-omap2/prcm.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index c64b668..b405e01 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -135,7 +135,7 @@ void omap_prcm_arch_reset(char mode) else WARN_ON(1); - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); + prm_set_mod_reg_bits(OMAP_RST_GS, prcm_offs, RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: new PM branch available
Hi Kevin, Hello, The latest PM branch is now available[1]. I've done basic testing of retention and off-mode (suspend and dynamic idle) on Beagle and custom HW. My SDP has something still keeping CORE active that others have not seen, but I have yet to debug. Any other reports from SDP testing would be appreciated. Notable changes/updates - rebased on latest clock updates and fixes from Paul - clockfw pre- and post- notifiers - DVFS for VDD2 I tried it on a beagleboard last night, but couldn't get even static retention to work. Some domains (core, per, dss) stay on, but even mpu and neon don't go to retention. They only go to inactive. So could you send your .config file ? Which rootfs are you using, I'm using debian, so maybe something keeps the CPU busy. Are you using NAND or MMC to store your rootfs ? Which beagle HW rev do you have ? I'm testing on a B5 board. And which u-boot are you using ? Thanks, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/1] Do a warm reboot instead of a cold reboot
Hi Jouni, De-Schrijver Peter (Nokia-D/Helsinki) peter.de-schrij...@nokia.com writes: This patch makes arch_reset do a warm reboot instead of a cold reboot. This is necessary because otherwise the system does not reboot reliably when disabling CLKEN in retention. Note : Unfortuately this breaks retention :( IVA2, PER and CORE don't go to retention after reboot. I'm not sure if fixing the problem this way makes sense currently. This will mean that after reboot OMAP modules are not reset. This will cause excactly this kind of problems. If we had that code for reset all the modules on boot, situation might be different. How about resetting also twl4030 in case of reboot. E.g. remove all the scripts from the twl4030? Even then we should be using warm reboot. The fact cold reboot works has been more luck then anything else. How hard is it to fix the module reset on boot ? And what does a OMAP watchdog reboot do ? Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: new PM branch available
Hi Kevin, Hi Peter, Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes: A first guess: this sounds like CONFIG_OMAP_RESET_CLOCKS=y is missing from your .config. The MPU/NEON going active but not RET is an indication to me that some fclk is active so that the fclk check in omap3_can_sleep() fails, so a WFI is never attempted. That's shy Ok. I did enable CONFIG_OMAP_RESET_CLOCKS. But with your config file only PER and CORE did not go to retention. One difference is that I did not enable smartreflex, but as B5 (and B4) are using OMAP3s without proper efuse values, smartreflex shouldn't matter I assume ? I upgrade my u-boot to the latest version, and then PER went to retention as well. The only way to get core to retention was to force idle USBOTG and disable the USBOTG driver. Dynamic retention seems to work only once the system has been in static retention once. Static off mode seems to work, but resume from off kills the UART. The system seems to run though, at least LED0 flickers as usual when the system runs. Sometimes it hangs and I have seen one reboot. Which rootfs are you using, I'm using debian, so maybe something keeps the CPU busy. Are you using NAND or MMC to store your rootfs ? I'm using rootfs on MMC and have tested with busybox-only, debian and OE rootfs. With debian and OE, I usually boot a minimal rootfs, before a full userland comes up. With debian, I changed my /etc/init.d/rcS to start initlevel 1 instead of 'S'. Ok. I tried with both the small OE ramdisk image and rather minimal debian install. I didn't see a difference in behaviour between both. And which u-boot are you using ? I'm using the u-boot from Steve Sakoman's tree[1]. That helped a lot in my initial Beagle testing, but I think the kernel should reset the IVA and D2D now which is the domains that I was having problems with before, so I think that the out of the box u-boot should work fine. I upgraded to this u-boot and it resolved at least one issue. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] per board prm timings
API definition to set prm setup times
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/pm.h |9 +
arch/arm/mach-omap2/pm34xx.c | 39 +--
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 451f247..d79ea07 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,9 +33,18 @@ extern void *omap3_secure_ram_storage;
extern void omap2_block_sleep(void);
extern void omap2_allow_sleep(void);
#ifdef CONFIG_ARCH_OMAP3
+struct prm_setup_times {
+ u16 clksetup;
+ u16 voltsetup_time1;
+ u16 voltsetup_time2;
+ u16 voltoffset;
+ u16 voltsetup2;
+};
+
extern void omap3_pm_off_mode_enable(int);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern void omap3_set_prm_setup_times(struct prm_setup_times *setup_times);
#else
#define omap3_pm_off_mode_enable(int) do {} while (0);
#define omap3_pm_get_suspend_state(pwrdm) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 44189a0..f531638 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,6 +85,14 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
+static struct prm_setup_times prm_setup = {
+ .clksetup = 0xff,
+ .voltsetup_time1 = 0xfff,
+ .voltsetup_time2 = 0xfff,
+ .voltoffset = 0xff,
+ .voltsetup2 = 0xff,
+};
+
static inline void omap3_per_save_context(void)
{
omap3_gpio_save_context();
@@ -880,6 +888,23 @@ int omap3_pm_set_suspend_state(struct powerdomain *pwrdm,
int state)
return -EINVAL;
}
+void omap3_set_prm_setup_times(struct prm_setup_times *setup_times)
+{
+ prm_setup.clksetup = setup_times-clksetup;
+ prm_setup.voltsetup_time1 = setup_times-voltsetup_time1;
+ prm_setup.voltsetup_time2 = setup_times-voltsetup_time2;
+ prm_setup.voltoffset = setup_times-voltoffset;
+ prm_setup.voltsetup2 = setup_times-voltsetup2;
+
+ printk(omap3_set_prm_setup_times %04x, %04x, %04x, %04x, %04x\n,
+ prm_setup.clksetup,
+ prm_setup.voltsetup_time1,
+ prm_setup.voltsetup_time2,
+ prm_setup.voltoffset,
+ prm_setup.voltsetup2);
+
+}
+
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
struct power_state *pwrst;
@@ -1015,6 +1040,7 @@ err2:
static void __init configure_vc(void)
{
+
prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
(R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
@@ -1044,21 +1070,22 @@ static void __init configure_vc(void)
OMAP3430_GR_MOD,
OMAP3_PRM_VC_I2C_CFG_OFFSET);
- /* Setup voltctrl and other setup times */
+ /* Setup value for voltctrl */
prm_write_mod_reg(OMAP3430_AUTO_RET,
OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET);
- prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ /* Write setup times */
+ prm_write_mod_reg(prm_setup.clksetup, OMAP3430_GR_MOD,
OMAP3_PRM_CLKSETUP_OFFSET);
- prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
+ prm_write_mod_reg((prm_setup.voltsetup_time2
OMAP3430_SETUP_TIME2_SHIFT) |
- (OMAP3430_VOLTSETUP_TIME1
+ (prm_setup.voltsetup_time1
OMAP3430_SETUP_TIME1_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltoffset, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTOFFSET_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltsetup2, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTSETUP2_OFFSET);
}
--
1.5.6.3
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[PATCH 0/1] Group and resource assignments for TWL4030
This patch introduces support for board specific group assignments of TWL4030 resources. The resource type and type2 fields can also be specified. Peter 'p2' De Schrijver (1): Group and resource assignments for TWL4030 drivers/mfd/twl4030-power.c | 95 ++- include/linux/i2c/twl4030.h | 41 ++- 2 files changed, 134 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] Group and resource assignments for TWL4030
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
drivers/mfd/twl4030-power.c | 95 ++-
include/linux/i2c/twl4030.h | 41 ++-
2 files changed, 134 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
index d9d1655..c558127 100644
--- a/drivers/mfd/twl4030-power.c
+++ b/drivers/mfd/twl4030-power.c
@@ -38,6 +38,8 @@ static u8 triton_next_free_address = 0x2b;
#define PHY_TO_OFF_PM_MASTER(p)(p - 0x36)
#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
+#define NUM_OF_RESOURCES 28
+
/* resource - hfclk */
#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
@@ -66,6 +68,42 @@ static u8 triton_next_free_address = 0x2b;
#define KEY_1 0xC0
#define KEY_2 0x0C
+/* resource configuration registers */
+
+#define DEVGROUP_OFFSET0
+#define TYPE_OFFSET1
+
+static int __initdata res_config_addrs[] = {
+ [1] = 0x17,
+ [2] = 0x1b,
+ [3] = 0x1f,
+ [4] = 0x23,
+ [5] = 0x27,
+ [6] = 0x2b,
+ [7] = 0x2f,
+ [8] = 0x33,
+ [9] = 0x37,
+ [10] = 0x3b,
+ [11] = 0x3f,
+ [12] = 0x43,
+ [13] = 0x47,
+ [14] = 0x4b,
+ [15] = 0x55,
+ [16] = 0x63,
+ [17] = 0x71,
+ [18] = 0x74,
+ [19] = 0x77,
+ [20] = 0x7a,
+ [21] = 0x7f,
+ [22] = 0x82,
+ [23] = 0x85,
+ [24] = 0x88,
+ [25] = 0x8b,
+ [26] = 0x8e,
+ [27] = 0x91,
+ [28] = 0x94,
+};
+
static int __init twl4030_write_script_byte(u8 address, u8 byte)
{
int err;
@@ -245,10 +283,57 @@ static int __init load_triton_script(struct
twl4030_script *tscript)
return err;
}
+static void __init twl4030_configure_resource(struct twl4030_resconfig
*rconfig)
+{
+ int rconfig_addr;
+ u8 type;
+
+ if (rconfig-resource NUM_OF_RESOURCES) {
+ printk(KERN_ERR
+ TWL4030 Resource %d does not exist\n,
+ rconfig-resource);
+ return;
+ }
+
+ rconfig_addr = res_config_addrs[rconfig-resource];
+
+ /* Set resource group */
+
+ if (rconfig-devgroup = 0)
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ rconfig-devgroup 5,
+ rconfig_addr + DEVGROUP_OFFSET);
+
+ /* Set resource types */
+
+ if (twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER,
+ type,
+ rconfig_addr + TYPE_OFFSET) 0) {
+ printk(KERN_ERR
+ TWL4030 Resource %d type could not read\n,
+ rconfig-resource);
+ return;
+ }
+
+ if (rconfig-type = 0) {
+ type = ~7;
+ type |= rconfig-type;
+ }
+
+ if (rconfig-type2 = 0) {
+ type = ~(3 3);
+ type |= rconfig-type2 3;
+ }
+
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ type, rconfig_addr + TYPE_OFFSET);
+}
+
void __init twl4030_power_init(struct twl4030_power_data *triton2_scripts)
{
int err = 0;
int i;
+ struct twl4030_resconfig *resconfig;
err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, KEY_1,
R_PROTECT_KEY);
@@ -258,12 +343,20 @@ void __init twl4030_power_init(struct twl4030_power_data
*triton2_scripts)
printk(KERN_ERR
TWL4030 Unable to unlock registers\n);
- for (i = 0; i triton2_scripts-size; i++) {
+ for (i = 0; i triton2_scripts-scripts_size; i++) {
err = load_triton_script(triton2_scripts-scripts[i]);
if (err)
break;
}
+ resconfig = triton2_scripts-resource_config;
+ if (resconfig) {
+ while (resconfig-resource) {
+ twl4030_configure_resource(resconfig);
+ resconfig++;
+ }
+ }
+
if (twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, R_PROTECT_KEY))
printk(KERN_ERR
TWL4030 Unable to relock registers\n);
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl4030.h
index 93d483d..e6ce1cd 100644
--- a/include/linux/i2c/twl4030.h
+++ b/include/linux/i2c/twl4030.h
@@ -243,6 +243,37 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg,
unsigned num_bytes);
#define RES_STATE_SLEEP0x8
#define RES_STATE_OFF 0x0
+/* Power resources */
+
+#define RES_VAUX1 1
+#define RES_VAUX2 2
+#define RES_VAUX3 3
+#define RES_VAUX4 4
+#define RES_VMMC1 5
+#define RES_VMMC2 6
+#define RES_VPLL1
[PATCH 0/1] Board specific prm timings
This is an updated version which removes a useless printk. This patch allows for boardspecific prm timings such as voltage and clock setup delays. By default it will use the very conservative timings which were used previously. Peter 'p2' De Schrijver (1): per board prm timings arch/arm/mach-omap2/pm.h |9 + arch/arm/mach-omap2/pm34xx.c | 31 +-- 2 files changed, 34 insertions(+), 6 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] per board prm timings
API definition to set prm setup times.
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/pm.h |9 +
arch/arm/mach-omap2/pm34xx.c | 31 +--
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 451f247..d79ea07 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,9 +33,18 @@ extern void *omap3_secure_ram_storage;
extern void omap2_block_sleep(void);
extern void omap2_allow_sleep(void);
#ifdef CONFIG_ARCH_OMAP3
+struct prm_setup_times {
+ u16 clksetup;
+ u16 voltsetup_time1;
+ u16 voltsetup_time2;
+ u16 voltoffset;
+ u16 voltsetup2;
+};
+
extern void omap3_pm_off_mode_enable(int);
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
+extern void omap3_set_prm_setup_times(struct prm_setup_times *setup_times);
#else
#define omap3_pm_off_mode_enable(int) do {} while (0);
#define omap3_pm_get_suspend_state(pwrdm) do {} while (0);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 44189a0..06aa382 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,6 +85,14 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
+static struct prm_setup_times prm_setup = {
+ .clksetup = 0xff,
+ .voltsetup_time1 = 0xfff,
+ .voltsetup_time2 = 0xfff,
+ .voltoffset = 0xff,
+ .voltsetup2 = 0xff,
+};
+
static inline void omap3_per_save_context(void)
{
omap3_gpio_save_context();
@@ -880,6 +888,15 @@ int omap3_pm_set_suspend_state(struct powerdomain *pwrdm,
int state)
return -EINVAL;
}
+void omap3_set_prm_setup_times(struct prm_setup_times *setup_times)
+{
+ prm_setup.clksetup = setup_times-clksetup;
+ prm_setup.voltsetup_time1 = setup_times-voltsetup_time1;
+ prm_setup.voltsetup_time2 = setup_times-voltsetup_time2;
+ prm_setup.voltoffset = setup_times-voltoffset;
+ prm_setup.voltsetup2 = setup_times-voltsetup2;
+}
+
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
struct power_state *pwrst;
@@ -1015,6 +1032,7 @@ err2:
static void __init configure_vc(void)
{
+
prm_write_mod_reg((R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA1_SHIFT) |
(R_SRI2C_SLAVE_ADDR OMAP3430_SMPS_SA0_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
@@ -1044,21 +1062,22 @@ static void __init configure_vc(void)
OMAP3430_GR_MOD,
OMAP3_PRM_VC_I2C_CFG_OFFSET);
- /* Setup voltctrl and other setup times */
+ /* Setup value for voltctrl */
prm_write_mod_reg(OMAP3430_AUTO_RET,
OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET);
- prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
+ /* Write setup times */
+ prm_write_mod_reg(prm_setup.clksetup, OMAP3430_GR_MOD,
OMAP3_PRM_CLKSETUP_OFFSET);
- prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2
+ prm_write_mod_reg((prm_setup.voltsetup_time2
OMAP3430_SETUP_TIME2_SHIFT) |
- (OMAP3430_VOLTSETUP_TIME1
+ (prm_setup.voltsetup_time1
OMAP3430_SETUP_TIME1_SHIFT),
OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltoffset, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTOFFSET_OFFSET);
- prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
+ prm_write_mod_reg(prm_setup.voltsetup2, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTSETUP2_OFFSET);
}
--
1.5.6.3
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Re: [PATCH 1/1] per board prm timings
Hi Kevin, Peter, I like this approach much better than what we currently have. Pushing to PM branch. The next thing I would like to see is all the register value defines removed from prm-regbits-34xx.h. That header is supposed to be for the bitfield definitions, not for values. True. If this patch goes in, there is no need for the register value defines in prm-regbits-34xx.h any more. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/1] Group and resource assignments for TWL4030
On Fri, Feb 13, 2009 at 09:55:21PM +0100, ext David Brownell wrote: On Tuesday 10 February 2009, Peter 'p2' De Schrijver wrote: This patch introduces support for board specific group assignments of TWL4030 resources. The resource type and type2 fields can also be specified. Do we have any real examples yet of needing to assign resources to anything other than P1 (processor)? Yes. On our custom hardware we use it to assign CLKEN to P3. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] OMAP3 PM Add C0 state
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 53 ++---
1 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 62fbb2e..0b5fd52 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -26,6 +26,7 @@
#include mach/pm.h
#include mach/prcm.h
#include mach/powerdomain.h
+#include mach/clockdomain.h
#include mach/control.h
#include mach/serial.h
@@ -34,9 +35,10 @@
#ifdef CONFIG_CPU_IDLE
#define OMAP3_MAX_STATES 7
-#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
-#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
-#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
+#define OMAP3_STATE_C0 0 /* C0 - MPU WFI + Core active */
+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core inactive */
+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core inactive */
+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core inactive */
#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
@@ -63,6 +65,16 @@ static int omap3_idle_bm_check(void)
return 0;
}
+static int _cpuidle_allow_idle(struct powerdomain *pwrdm, struct clockdomain
*clkdm)
+{
+ omap2_clkdm_allow_idle(clkdm);
+}
+
+static int _cpuidle_deny_idle(struct powerdomain *pwrdm, struct clockdomain
*clkdm)
+{
+ omap2_clkdm_deny_idle(clkdm);
+}
+
/**
* omap3_enter_idle - Programs OMAP3 to enter the specified state
* @dev: cpuidle device
@@ -99,9 +111,19 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
if (omap_irq_pending())
goto return_sleep_time;
+ if (cx-type == OMAP3_STATE_C0) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+ }
+
/* Execute ARM wfi */
omap_sram_idle();
+ if (cx-type == OMAP3_STATE_C0) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+ }
+
return_sleep_time:
getnstimeofday(ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
@@ -140,16 +162,27 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/* omap3_init_power_states - Initialises the OMAP3 specific C states.
*
* Below is the desciption of each C state.
- * C1 . MPU WFI + Core active
- * C2 . MPU CSWR + Core active
- * C3 . MPU OFF + Core active
+ * C0 . MPU WFI + Core active
+ * C1 . MPU WFI + Core inactive
+ * C2 . MPU CSWR + Core inactive
+ * C3 . MPU OFF + Core inactive
* C4 . MPU CSWR + Core CSWR
* C5 . MPU OFF + Core CSWR
* C6 . MPU OFF + Core OFF
*/
void omap_init_power_states(void)
{
- /* C1 . MPU WFI + Core active */
+ /* C0 . MPU WFI + Core active */
+ omap3_power_states[OMAP3_STATE_C0].valid = 1;
+ omap3_power_states[OMAP3_STATE_C0].type = OMAP3_STATE_C0;
+ omap3_power_states[OMAP3_STATE_C0].sleep_latency = 2;
+ omap3_power_states[OMAP3_STATE_C0].wakeup_latency = 2;
+ omap3_power_states[OMAP3_STATE_C0].threshold = 5;
+ omap3_power_states[OMAP3_STATE_C0].mpu_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C0].core_state = PWRDM_POWER_ON;
+ omap3_power_states[OMAP3_STATE_C0].flags = CPUIDLE_FLAG_TIME_VALID;
+
+ /* C1 . MPU WFI + Core inactive */
omap3_power_states[OMAP3_STATE_C1].valid = 1;
omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
@@ -159,7 +192,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
- /* C2 . MPU CSWR + Core active */
+ /* C2 . MPU CSWR + Core inactive */
omap3_power_states[OMAP3_STATE_C2].valid = 1;
omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
@@ -170,7 +203,7 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
- /* C3 . MPU OFF + Core active */
+ /* C3 . MPU OFF + Core inactive */
omap3_power_states[OMAP3_STATE_C3].valid = 1;
omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
omap3_power_states[OMAP3_STATE_C3].sleep_latency = 1500;
@@ -244,7 +277,7 @@ int omap3_idle_init(void)
dev = per_cpu(omap3_idle_dev, smp_processor_id());
- for (i = 1; i OMAP3_MAX_STATES; i++) {
+ for (i = 0; i OMAP3_MAX_STATES; i++) {
cx = omap3_power_states[i
[PATCH 0/1] OMAP3 PM Add C0 state
This patch introduces a new C state C0 which keeps both core and mpu powerdomains in ON state. This gives us low latency at a cost of higher power consumption. Peter 'p2' De Schrijver (1): OMAP3 PM Add C0 state arch/arm/mach-omap2/cpuidle34xx.c | 53 ++--- 1 files changed, 43 insertions(+), 10 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/1] OMAP3 PM Add C0 state
On Mon, Feb 23, 2009 at 07:24:24PM +0100, ext Kevin Hilman wrote: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes: This patch introduces a new C state C0 which keeps both core and mpu powerdomains in ON state. This gives us low latency at a cost of higher power consumption. I don't like the name 'C0' for an idle-state. In ACPI terms, C0 is an active state, not an idle state. I know this is not an ACPI system, but since we're using ACPI names, we should be consistent. Is there a real benefit to having an additional state here? Shouldn't we just make these changes or C1? C1 has a too high wakeup latency (10s of us) for some cases, but C0 (which has a 3us wakeup latency) keeps core on which implies little powersavings. So I think we need both. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/1] Group and resource assignments for TWL4030
On Wed, Mar 04, 2009 at 12:38:16AM +0100, ext David Brownell wrote: On Friday 27 February 2009, Tony Lindgren wrote: * Peter 'p2' De Schrijver peter.de-schrij...@nokia.com [090215 08:49]: On Fri, Feb 13, 2009 at 09:55:21PM +0100, ext David Brownell wrote: On Tuesday 10 February 2009, Peter 'p2' De Schrijver wrote: This patch introduces support for board specific group assignments of TWL4030 resources. The resource type and type2 fields can also be specified. Do we have any real examples yet of needing to assign resources to anything other than P1 (processor)? Yes. On our custom hardware we use it to assign CLKEN to P3. P3 roughly translating to system running, with no regard to whether ARM(s) or DSP are active, yes? Depends on the board. We use P3 to control the system oscillator. The SYSCLK_REQ output of OMAP3 is wired to the CLKREQ input on the TWL4030. OMAP3 will disable SYSCLK_REQ when the system clock is no longer necessary. (Eg, when going to chip retention). This obviously only works if CLKEN is only in P3. (Otherwise it won't be turned off as P1 is still active). A similar setup is used on the TI SDP3430 board. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Add new C state
This patch introduces a new C state which allows MPU to go to WFI but keeps
the core domain active. This offers a much better wakeup latency (3us vs
10s of us for the current C1) at the cost of a higher power consumption.
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/cpuidle34xx.c | 119 +++-
1 files changed, 76 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c
b/arch/arm/mach-omap2/cpuidle34xx.c
index 62fbb2e..5565aa7 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -26,6 +26,7 @@
#include mach/pm.h
#include mach/prcm.h
#include mach/powerdomain.h
+#include mach/clockdomain.h
#include mach/control.h
#include mach/serial.h
@@ -33,13 +34,14 @@
#ifdef CONFIG_CPU_IDLE
-#define OMAP3_MAX_STATES 7
+#define OMAP3_MAX_STATES 8
#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
-#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
-#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
-#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
-#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
-#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
+#define OMAP3_STATE_C2 2 /* C2 - MPU WFI + Core inactive */
+#define OMAP3_STATE_C3 3 /* C2 - MPU CSWR + Core inactive */
+#define OMAP3_STATE_C4 4 /* C3 - MPU OFF + Core iactive */
+#define OMAP3_STATE_C5 5 /* C4 - MPU RET + Core RET */
+#define OMAP3_STATE_C6 6 /* C5 - MPU OFF + Core RET */
+#define OMAP3_STATE_C7 7 /* C6 - MPU OFF + Core OFF */
struct omap3_processor_cx {
u8 valid;
@@ -63,6 +65,16 @@ static int omap3_idle_bm_check(void)
return 0;
}
+static int _cpuidle_allow_idle(struct powerdomain *pwrdm, struct clockdomain
*clkdm)
+{
+ omap2_clkdm_allow_idle(clkdm);
+}
+
+static int _cpuidle_deny_idle(struct powerdomain *pwrdm, struct clockdomain
*clkdm)
+{
+ omap2_clkdm_deny_idle(clkdm);
+}
+
/**
* omap3_enter_idle - Programs OMAP3 to enter the specified state
* @dev: cpuidle device
@@ -99,9 +111,19 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
if (omap_irq_pending())
goto return_sleep_time;
+ if (cx-type == OMAP3_STATE_C1) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+ }
+
/* Execute ARM wfi */
omap_sram_idle();
+ if (cx-type == OMAP3_STATE_C1) {
+ pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
+ pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+ }
+
return_sleep_time:
getnstimeofday(ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
@@ -140,79 +162,90 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/* omap3_init_power_states - Initialises the OMAP3 specific C states.
*
* Below is the desciption of each C state.
- * C1 . MPU WFI + Core active
- * C2 . MPU CSWR + Core active
- * C3 . MPU OFF + Core active
- * C4 . MPU CSWR + Core CSWR
- * C5 . MPU OFF + Core CSWR
- * C6 . MPU OFF + Core OFF
+ * C1 . MPU WFI + Core active
+ * C2 . MPU WFI + Core inactive
+ * C3 . MPU CSWR + Core inactive
+ * C4 . MPU OFF + Core inactive
+ * C5 . MPU CSWR + Core CSWR
+ * C6 . MPU OFF + Core CSWR
+ * C7 . MPU OFF + Core OFF
*/
void omap_init_power_states(void)
{
/* C1 . MPU WFI + Core active */
omap3_power_states[OMAP3_STATE_C1].valid = 1;
omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
- omap3_power_states[OMAP3_STATE_C1].sleep_latency = 10;
- omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 10;
- omap3_power_states[OMAP3_STATE_C1].threshold = 30;
+ omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
+ omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
+ omap3_power_states[OMAP3_STATE_C1].threshold = 5;
omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
- /* C2 . MPU CSWR + Core active */
+ /* C2 . MPU WFI + Core inactive */
omap3_power_states[OMAP3_STATE_C2].valid = 1;
omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
- omap3_power_states[OMAP3_STATE_C2].sleep_latency = 50;
- omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 50;
- omap3_power_states[OMAP3_STATE_C2].threshold = 300;
- omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_RET;
+ omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
+ omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
+ omap3_power_states[OMAP3_STATE_C2].threshold = 30;
+ omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
omap3_power_states[OMAP3_STATE_C2].core_state
[PATCH] Remove fclk check for cpuidle
This patch removes the check to see if some functional clocks are still
enabled before entering sleep.
Signed-off-by: Peter 'p2' De Schrijver peter.de-schrij...@nokia.com
---
arch/arm/mach-omap2/pm34xx.c | 46 --
1 files changed, 0 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index e12ff2a..008a4d2 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -453,58 +453,12 @@ void omap_sram_idle(void)
omap2_clkdm_allow_idle(mpu_pwrdm-pwrdm_clkdms[0]);
}
-/*
- * Check if functional clocks are enabled before entering
- * sleep. This function could be behind CONFIG_PM_DEBUG
- * when all drivers are configuring their sysconfig registers
- * properly and using their clocks properly.
- */
-static int omap3_fclks_active(void)
-{
- u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
- fck_cam = 0, fck_per = 0, fck_usbhost = 0;
-
- fck_core1 = cm_read_mod_reg(CORE_MOD,
- CM_FCLKEN1);
- if (omap_rev() OMAP3430_REV_ES1_0) {
- fck_core3 = cm_read_mod_reg(CORE_MOD,
- OMAP3430ES2_CM_FCLKEN3);
- fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
- CM_FCLKEN);
- fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
- CM_FCLKEN);
- } else
- fck_sgx = cm_read_mod_reg(GFX_MOD,
- OMAP3430ES2_CM_FCLKEN3);
- fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
- CM_FCLKEN);
- fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
- CM_FCLKEN);
- fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
- CM_FCLKEN);
-
- /* Ignore UART clocks. These are handled by UART core (serial.c) */
- fck_core1 = ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
- fck_per = ~OMAP3430_EN_UART3;
-
- /* Ignore GPIO clocks. Handled by GPIO prepare-idle hooks */
- fck_per = ~(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
-OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | OMAP3430_EN_GPIO6);
-
- if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
- fck_cam | fck_per | fck_usbhost)
- return 1;
- return 0;
-}
-
int omap3_can_sleep(void)
{
if (!enable_dyn_sleep)
return 0;
if (!omap_uart_can_sleep())
return 0;
- if (omap3_fclks_active())
- return 0;
if (atomic_read(sleep_block) 0)
return 0;
return 1;
--
1.5.6.3
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[PATCH] Implement powerdomain off on state counters
This patchset implement counters to count the number of off to on state transitions in a powerdomain. These counters will be made available to drivers in a later patchset to allow them to make a better informed decision wether to restore the hardware registers or not. Peter 'p2' De Schrijver (3): Powerdomain debugging Powerdomain off mode counters PM and clock domain hooks for off mode counters arch/arm/mach-omap2/Makefile |2 +- arch/arm/mach-omap2/clockdomain.c | 10 + arch/arm/mach-omap2/pm34xx.c |9 +++- arch/arm/mach-omap2/powerdomain-debug.c | 50 + arch/arm/mach-omap2/powerdomain.c | 48 +++- arch/arm/plat-omap/include/mach/powerdomain.h |9 - 6 files changed, 122 insertions(+), 6 deletions(-) create mode 100644 arch/arm/mach-omap2/powerdomain-debug.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Powerdomain off mode counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomain.c | 48 +++-
arch/arm/plat-omap/include/mach/powerdomain.h |9 -
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 73e2971..80ecae1 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,27 @@ static struct powerdomain *_pwrdm_deps_lookup(struct
powerdomain *pwrdm,
return pd-pwrdm;
}
+static int _pwrdm_save_pwrst_cb(struct powerdomain *pwrdm, void *user)
+{
+ pwrdm_save_pwrst(pwrdm);
+
+ return 0;
+}
+
+static int _pwrdm_count_off_mode_cb(struct powerdomain *pwrdm, void *user)
+{
+ int prev;
+
+ prev = pwrdm_read_prev_pwrst(pwrdm);
+
+ if (prev != PWRDM_POWER_OFF pwrdm-state != prev)
+pwrdm-offstate_count++;
+
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+
+ return 0;
+}
+
/* Public functions */
@@ -217,7 +238,7 @@ struct powerdomain *pwrdm_lookup(const char *name)
* anything else to indicate failure; or -EINVAL if the function
* pointer is null.
*/
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), void
*user)
{
struct powerdomain *temp_pwrdm;
unsigned long flags;
@@ -228,7 +249,7 @@ int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
read_lock_irqsave(pwrdm_rwlock, flags);
list_for_each_entry(temp_pwrdm, pwrdm_list, node) {
- ret = (*fn)(temp_pwrdm);
+ ret = (*fn)(temp_pwrdm, user);
if (ret)
break;
}
@@ -1110,4 +1131,27 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
+void pwrdm_save_pwrst(struct powerdomain *pwrdm)
+{
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+}
+
+void pwrdm_check_off_mode(struct powerdomain *pwrdm)
+{
+ int state;
+
+ state = pwrdm_read_pwrst(pwrdm);
+ if (pwrdm-state == PWRDM_POWER_OFF state == PWRDM_POWER_ON)
+ pwrdm-offstate_count++;
+}
+
+void pwrdm_save_pwrst_all(void)
+{
+ pwrdm_for_each(_pwrdm_save_pwrst_cb, NULL);
+}
+
+void pwrdm_count_off_mode(void)
+{
+ pwrdm_for_each(_pwrdm_count_off_mode_cb, NULL);
+}
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h
b/arch/arm/plat-omap/include/mach/powerdomain.h
index 4948cb7..6147a87 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -117,6 +117,8 @@ struct powerdomain {
struct list_head node;
+ int state;
+ u32 offstate_count;
};
@@ -126,7 +128,8 @@ int pwrdm_register(struct powerdomain *pwrdm);
int pwrdm_unregister(struct powerdomain *pwrdm);
struct powerdomain *pwrdm_lookup(const char *name);
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -164,4 +167,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
+void pwrdm_save_pwrst(struct powerdomain *pwrdm);
+void pwrdm_check_off_mode(struct powerdomain *pwrdm);
+void pwrdm_save_pwrst_all(void);
+void pwrdm_count_off_mode(void);
#endif
--
1.5.6.3
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[PATCH] PM and clock domain hooks for off mode counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clockdomain.c | 10 ++
arch/arm/mach-omap2/pm34xx.c |9 +++--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..5b87b9b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,11 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm.ptr);
+ pwrdm_check_off_mode(clkdm-pwrdm.ptr);
+ }
+
return 0;
}
@@ -618,6 +623,11 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm.ptr);
+ pwrdm_save_pwrst(clkdm-pwrdm.ptr);
+ }
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a16eb33..32f46c9 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -167,11 +167,16 @@ static void omap_sram_idle(void)
return;
}
+ pwrdm_save_pwrst_all();
+
omap2_gpio_prepare_for_retention();
_omap_sram_idle(NULL, save_state);
omap2_gpio_resume_after_retention();
+
+ pwrdm_count_off_mode();
+
}
/*
@@ -521,7 +526,7 @@ static void __init prcm_setup_regs(void)
OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
}
-static int __init pwrdms_setup(struct powerdomain *pwrdm)
+static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
struct power_state *pwrst;
@@ -561,7 +566,7 @@ int __init omap3_pm_init(void)
goto err1;
}
- ret = pwrdm_for_each(pwrdms_setup);
+ ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
printk(KERN_ERR Failed to setup powerdomains\n);
goto err2;
--
1.5.6.3
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[PATCH] Powerdomain debugging
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile|2 +-
arch/arm/mach-omap2/powerdomain-debug.c | 50 +++
2 files changed, 51 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-omap2/powerdomain-debug.c
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d89b7cb..e1adb0e 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -24,7 +24,7 @@ obj-y += pm.o
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP24XX)+= sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
-obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+obj-$(CONFIG_PM_DEBUG) += pm-debug.o powerdomain-debug.o
endif
# SmartReflex driver
diff --git a/arch/arm/mach-omap2/powerdomain-debug.c
b/arch/arm/mach-omap2/powerdomain-debug.c
new file mode 100644
index 000..dda88e1
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain-debug.c
@@ -0,0 +1,50 @@
+#include linux/debugfs.h
+#include linux/seq_file.h
+#include mach/powerdomain.h
+
+
+int show_off_mode_count(struct powerdomain *pwrdm, void *user)
+{
+ struct seq_file *s = (struct seq_file *)user;
+
+ if (strcmp(pwrdm-name, emu_pwrdm)
+ strcmp(pwrdm-name, wkup_pwrdm))
+ seq_printf(s, %s : %d\n, pwrdm-name, pwrdm-offstate_count);
+
+ return 0;
+}
+
+int show_off_mode_counters(struct seq_file *s, void *unused)
+{
+ pwrdm_for_each(show_off_mode_count, s);
+
+ return 0;
+}
+
+static int off_mode_counter_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, show_off_mode_counters, inode-i_private);
+}
+
+static const struct file_operations debug_fops = {
+ .open = off_mode_counter_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int __init off_mode_counter_debug(void)
+{
+ struct dentry *d;
+
+ d = debugfs_create_dir(off_mode_counters, NULL);
+ if (IS_ERR(d))
+ return PTR_ERR(d);
+
+ debugfs_create_file(count, S_IRUGO,
+ d, NULL, debug_fops);
+
+ return 0;
+}
+
+late_initcall(off_mode_counter_debug);
--
1.5.6.3
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[PATCH] Fix build for beagleboard
---
drivers/i2c/chips/twl4030-power.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/chips/twl4030-power.c
b/drivers/i2c/chips/twl4030-power.c
index 195c3c4..04a13aa 100644
--- a/drivers/i2c/chips/twl4030-power.c
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -149,7 +149,7 @@ struct triton_ins t2_wrst_seq[] __initdata = {
struct triton_ins sleep_on_seq[] __initdata = {
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_SLEEP), 4},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_SLEEP), 4},
};
@@ -160,6 +160,9 @@ struct triton_ins sleep_off_seq[] __initdata = {
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_ACTIVE), 0x2},
};
+
+struct triton_ins t2_wrst_seq[] __initdata = { };
+
#endif
static int __init twl4030_write_script_byte(u8 address, u8 byte)
--
1.5.6.3
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[PATCH] Fix for twl4030-power.c build failure for beagleboard
This patch should fix the twl4030-power.c build failure for beagleboard. Peter 'p2' De Schrijver (1): Fix build for beagleboard drivers/i2c/chips/twl4030-power.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] *** SUBJECT HERE ***
*** BLURB HERE *** Peter 'p2' De Schrijver (1): Fix build for beagleboard drivers/i2c/chips/twl4030-power.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Fix build for beagleboard
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/twl4030-power.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/chips/twl4030-power.c
b/drivers/i2c/chips/twl4030-power.c
index 195c3c4..04a13aa 100644
--- a/drivers/i2c/chips/twl4030-power.c
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -149,7 +149,7 @@ struct triton_ins t2_wrst_seq[] __initdata = {
struct triton_ins sleep_on_seq[] __initdata = {
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_SLEEP), 4},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE_R7,
+ {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_SLEEP), 4},
};
@@ -160,6 +160,9 @@ struct triton_ins sleep_off_seq[] __initdata = {
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
RES_STATE_ACTIVE), 0x2},
};
+
+struct triton_ins t2_wrst_seq[] __initdata = { };
+
#endif
static int __init twl4030_write_script_byte(u8 address, u8 byte)
--
1.5.6.3
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[PATCH] Debobs and ETK padconf implementation
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/debobs.c | 214 ++
1 files changed, 214 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debobs.c
diff --git a/arch/arm/mach-omap2/debobs.c b/arch/arm/mach-omap2/debobs.c
new file mode 100644
index 000..1bde1f4
--- /dev/null
+++ b/arch/arm/mach-omap2/debobs.c
@@ -0,0 +1,214 @@
+/*
+ * arch/arm/mach-omap2/debobs.c
+ *
+ * Handle debobs pads
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Peter De Schrijver [EMAIL PROTECTED]
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/debugfs.h
+#include linux/uaccess.h
+#include linux/module.h
+#include mach/control.h
+#include mach/mux.h
+#include mach/gpio.h
+#include mach/board.h
+
+#define ETK_GPIO_BEGIN 12
+#define ETK_GPIO(i)(ETK_GPIO_BEGIN + i)
+#define NUM_OF_DEBOBS_PADS 18
+
+enum debobs_pad_mode {
+ GPIO = 0,
+ OBS = 1,
+ ETK = 2,
+ NO_MODE = 3,
+};
+
+static char *debobs_pad_mode_names[] = {
+ [GPIO] = GPIO,
+ [OBS] = OBS,
+ [ETK] = ETK,
+};
+
+struct obs {
+ u16 offset;
+ u8 value;
+ u8 mask;
+};
+
+struct debobs_pad {
+ enum debobs_pad_mode mode;
+ struct obs core_obs;
+ struct obs wakeup_obs;
+};
+
+static struct debobs_pad debobs_pads[NUM_OF_DEBOBS_PADS];
+
+static int debobs_mode_open(struct inode *inode, struct file *file)
+{
+ file-private_data = inode-i_private;
+
+ return 0;
+}
+
+static ssize_t debobs_mode_read(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ char buffer[10];
+ int size;
+ int pad_number = (int)file-private_data;
+ struct debobs_pad *e = debobs_pads[pad_number];
+
+ size = snprintf(buffer, sizeof(buffer), %s\n,
+ debobs_pad_mode_names[e-mode]);
+ return simple_read_from_buffer(user_buf, count, ppos, buffer, size);
+}
+
+static ssize_t debobs_mode_write(struct file *file, const char __user
*user_buf,
+ size_t count, loff_t *ppos)
+{
+ char buffer[10];
+ int buf_size, i, pad_number;
+ u16 muxmode = OMAP34XX_MUX_MODE7;
+
+ memset(buffer, 0, sizeof(buffer));
+ buf_size = min(count, (sizeof(buffer)-1));
+
+ if (copy_from_user(buffer, user_buf, buf_size))
+ return -EFAULT;
+
+ pad_number = (int)file-private_data;
+
+ for (i = 0; i NO_MODE; i++) {
+ if (!strnicmp(debobs_pad_mode_names[i],
+ buffer,
+ strlen(debobs_pad_mode_names[i]))) {
+ switch (i) {
+ case ETK:
+ muxmode = OMAP34XX_MUX_MODE0;
+ break;
+ case GPIO:
+ muxmode = OMAP34XX_MUX_MODE4;
+ break;
+ case OBS:
+ muxmode = OMAP34XX_MUX_MODE7;
+ break;
+ }
+ omap_ctrl_writew(muxmode,
+ OMAP343X_PADCONF_ETK(pad_number));
+ debobs_pads[pad_number].mode = i;
+
+ return count;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct file_operations debobs_mode_fops = {
+ .open = debobs_mode_open,
+ .read = debobs_mode_read,
+ .write = debobs_mode_write,
+};
+
+static int debobs_get(void *data, u64 *val)
+{
+ struct obs *o = data;
+
+ *val = o-value;
+
+ return 0;
+}
+
+static int debobs_set(void *data, u64 val)
+{
+ struct obs *o = data;
+
+ val = BIT(o-mask) - 1;
+
+ omap_ctrl_writeb(val, o-offset);
+ o-value = val;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(debobs_fops, debobs_get, debobs_set, %llu\n);
+
+static inline int __init _new_debobs_pad(struct debobs_pad *pad, char *name,
+ int number, struct dentry *root)
+{
+ struct dentry *d;
+ struct obs *o;
+
+ d = debugfs_create_dir(name, root);
+ if (IS_ERR(d))
+ return
[PATCH] Add definitions for ETK pads and debobs registers
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/plat-omap/include/mach/control.h | 34 + 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index ef8cf12..19addae 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -149,6 +149,8 @@ #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ + + ((i) 1) * 4 + (!(i) 1) * 2) #define OMAP343X_CONTROL_DEBOBS_0 (OMAP2_CONTROL_GENERAL + 0x01B0) #define OMAP343X_CONTROL_DEBOBS_1 (OMAP2_CONTROL_GENERAL + 0x01B4) #define OMAP343X_CONTROL_DEBOBS_2 (OMAP2_CONTROL_GENERAL + 0x01B8) @@ -170,6 +172,38 @@ #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02b4) +/* 34xx PADCONF register offsets */ + +#define OMAP343X_PADCONF_ETK(i)(OMAP2_CONTROL_PADCONFS + 0x5a8 + \ + (i)*2) +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) +#define OMAP343X_PADCONF_ETK_D0OMAP343X_PADCONF_ETK(2) +#define OMAP343X_PADCONF_ETK_D1OMAP343X_PADCONF_ETK(3) +#define OMAP343X_PADCONF_ETK_D2OMAP343X_PADCONF_ETK(4) +#define OMAP343X_PADCONF_ETK_D3OMAP343X_PADCONF_ETK(5) +#define OMAP343X_PADCONF_ETK_D4OMAP343X_PADCONF_ETK(6) +#define OMAP343X_PADCONF_ETK_D5OMAP343X_PADCONF_ETK(7) +#define OMAP343X_PADCONF_ETK_D6OMAP343X_PADCONF_ETK(8) +#define OMAP343X_PADCONF_ETK_D7OMAP343X_PADCONF_ETK(9) +#define OMAP343X_PADCONF_ETK_D8OMAP343X_PADCONF_ETK(10) +#define OMAP343X_PADCONF_ETK_D9OMAP343X_PADCONF_ETK(11) +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) + +/* 34xx GENERAL_WKUP regist offsets */ + +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ + 0x008 + (i)) +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) /* * REVISIT: This list of registers is not comprehensive - there are more -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Add debobs Kconfig item
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/Kconfig | 10 +- arch/arm/mach-omap2/Makefile |3 +++ 2 files changed, 12 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index d0bbbf8..639af08 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -151,4 +151,12 @@ config OMAP3_OFF_MODE depends on ARCH_OMAP3 default n help - Use off mode for powerdomains. \ No newline at end of file + Use off mode for powerdomains. + +config OMAP3_DEBOBS + bool OMAP 3430 Debug observability support + depends on ARCH_OMAP3 DEBUG_FS + default n + help + Use ETK pads for debug observability + diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 23fc127..88d3af0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -40,6 +40,9 @@ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o mmu_mach-objs := mmu.o +# Debobs +obj-$(CONFIG_OMAP3_DEBOBS) += debobs.o + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC)+= board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o board-h4-mmc.o -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] debobs support for OMAP3430.
This patch adds support for debug observability on OMAP3430 using the ETK lines. Fixes some potential issues with the OMAP343X_CONTROL_DEBOBS, OMAP343X_PADCONF_ETK and OMAP343X_CONTROL_WKUP_DEBOBSMUX macros. Peter 'p2' De Schrijver (3): Add definitions for ETK pads and debobs registers Debobs and ETK padconf implementation Add debobs Kconfig item arch/arm/mach-omap2/Kconfig | 10 ++- arch/arm/mach-omap2/Makefile |3 + arch/arm/mach-omap2/debobs.c | 214 + arch/arm/plat-omap/include/mach/control.h | 34 + 4 files changed, 260 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-omap2/debobs.c -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Move some counter functions to powerdomain.c
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 107 ++--
1 files changed, 16 insertions(+), 91 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 380a2a0..a375312 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -318,94 +318,20 @@ int pm_dbg_regset_save(int reg_set)
return 0;
}
-static int _pm_dbg_state_switch(struct powerdomain *pwrdm, int flag)
+void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
{
s64 t;
struct timespec now;
- int prev;
- int state;
- if (pwrdm == NULL)
- return -EINVAL;
-
- state = pwrdm_read_pwrst(pwrdm);
-
- switch (flag) {
- case PM_DBG_STATE_NOW:
- prev = pwrdm-state;
- break;
- case PM_DBG_STATE_PREV:
- prev = pwrdm_read_prev_pwrst(pwrdm);
- if (pwrdm-state != prev)
- pwrdm-state_counter[prev]++;
- break;
- default:
- return -EINVAL;
- }
-
- if (pm_dbg_init_done) {
- /* Update timer for previous state */
- getnstimeofday(now);
- t = timespec_to_ns(now);
-
- pwrdm-state_timer[prev] += t - pwrdm-timer;
-
- pwrdm-timer = t;
-
- if (state != prev)
- pwrdm-state_counter[state]++;
- }
-
- pwrdm-state = state;
-
- return 0;
-}
-
-int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm)
-{
- return _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
-}
-
-int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm)
-{
- if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
- pwrdm_wait_transition(clkdm-pwrdm.ptr);
- return pm_dbg_pwrdm_state_switch(clkdm-pwrdm.ptr);
- }
-
- return -EINVAL;
-}
-
-int pm_dbg_clk_state_switch(struct clk *clk)
-{
- if (clk != NULL clk-clkdm.ptr != NULL)
- return pm_dbg_clkdm_state_switch(clk-clkdm.ptr);
- return -EINVAL;
-}
+ if (!pm_dbg_init_done)
+ return;
-static int pm_dbg_pre_suspend_cb(struct powerdomain *pwrdm)
-{
- pwrdm_clear_all_prev_pwrst(pwrdm);
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
- return 0;
-}
-
-static int pm_dbg_post_suspend_cb(struct powerdomain *pwrdm)
-{
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_PREV);
- return 0;
-}
+ getnstimeofday(now);
+ t = timespec_to_ns(now);
-int pm_dbg_pre_suspend(void)
-{
- pwrdm_for_each(pm_dbg_pre_suspend_cb);
- return 0;
-}
+ pwrdm-state_timer[prev] += t - pwrdm-timer;
-int pm_dbg_post_suspend(void)
-{
- pwrdm_for_each(pm_dbg_post_suspend_cb);
- return 0;
+ pwrdm-timer = t;
}
enum {
@@ -489,25 +415,23 @@ int pm_dbg_regset_init(int reg_set)
return 0;
}
-static int __init pwrdms_setup(struct powerdomain *pwrdm)
+int __init _pwrdm_debug_setup(struct powerdomain *pwrdm, void *user)
{
- s64 t;
- int i;
+ s64 t=0;
struct timespec now;
+ int i;
+
+printk(pwrdm: %p\n,pwrdm);
getnstimeofday(now);
t = timespec_to_ns(now);
+ pwrdm-timer = t;
+
for (i = 0; i 4; i++) {
- pwrdm-state_counter[i] = 0;
pwrdm-state_timer[i] = 0;
}
- pwrdm_wait_transition(pwrdm);
- pwrdm-state = pwrdm_read_pwrst(pwrdm);
- pwrdm-state_counter[pwrdm-state] = 1;
- pwrdm-timer = t;
-
(void) debugfs_create_file(pwrdm-name, S_IRUGO|S_IWUSR,
pm_dbg_dir, pwrdm, debug_pwrdm_fops);
@@ -535,7 +459,7 @@ static int __init pm_dbg_init(void)
if (IS_ERR(pm_dbg_dir))
return PTR_ERR(pm_dbg_dir);
- pwrdm_for_each(pwrdms_setup);
+ pwrdm_for_each(_pwrdm_debug_setup, NULL);
pm_dbg_dir = debugfs_create_dir(registers, d);
if (IS_ERR(pm_dbg_dir))
@@ -552,6 +476,7 @@ static int __init pm_dbg_init(void)
}
+
pm_dbg_init_done = 1;
return 0;
--
1.5.6.3
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[PATCH] Move PM debug counters to normal PM code. Preview.
This patchset makes the PM counters no longer debug only. This will allow drivers to decide if they need to reinitialize the hardware due to an off to on transition. This probably needs some more work/thinking. Peter 'p2' De Schrijver (5): Move some counter functions to powerdomain.c Adapt prototypes for counter functions Move counter function into generic OMAP PM Make counter types unsigned, add closure pointer to pwrdm_for_each, add prototypes Add hooks to PM layer and clock tree for PM counters arch/arm/mach-omap2/clock.c |3 +- arch/arm/mach-omap2/clockdomain.c |4 +- arch/arm/mach-omap2/pm-debug.c| 107 arch/arm/mach-omap2/pm.h | 14 +-- arch/arm/mach-omap2/pm34xx.c | 10 +- arch/arm/mach-omap2/powerdomain.c | 113 +++-- arch/arm/plat-omap/include/mach/powerdomain.h | 13 ++- 7 files changed, 146 insertions(+), 118 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Adapt prototypes for counter functions
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/pm.h | 14 -- 1 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index aad4aeb..16212c1 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -45,11 +45,8 @@ struct seq_file; struct clk; struct clockdomain; struct powerdomain; -extern int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm); -extern int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm); -extern int pm_dbg_clk_state_switch(struct clk *clk); -extern int pm_dbg_pre_suspend(void); -extern int pm_dbg_post_suspend(void); +extern int pwrdms_debug_setup(struct powerdomain *pwrdm); +extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); extern int pm_dbg_regset_save(int reg_set); extern int pm_dbg_regset_init(int reg_set); extern int pwrdm_dbg_show_counters(struct seq_file *s, void *unused); @@ -57,11 +54,8 @@ extern int pwrdm_dbg_show_timers(struct seq_file *s, void *unused); extern int clkdm_dbg_show_counters(struct seq_file *s, void *unused); extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); #else -#define pm_dbg_pwrdm_state_switch(domain) do; while (0) -#define pm_dbg_clkdm_state_switch(domain) do; while (0) -#define pm_dbg_clk_state_switch(domain) do; while (0) -#define pm_dbg_pre_suspend() do; while (0) -#define pm_dbg_post_suspend() do; while (0) +#define pwrdms_debug_setup(pwrdm) do ; while (0) +#define pm_dbg_update_time(pwrdm, prev) do ; while (0) #define pm_dbg_regset_save(reg_set) do; while (0) #define pm_dbg_regset_init(reg_set) do; while (0) #define pwrdm_dbg_show_counters(s,unused) do; while (0) -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] Add hooks to PM layer and clock tree for PM counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |3 ++-
arch/arm/mach-omap2/clockdomain.c |4 ++--
arch/arm/mach-omap2/pm34xx.c | 10 +-
3 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d0006c4..1c94c02 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1028,6 +1028,7 @@ void omap2_clk_disable_unused(struct clk *clk)
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
_omap2_clk_disable(clk);
- pm_dbg_clk_state_switch(clk);
+ if (clk-clkdm.ptr != NULL)
+ pwrdm_clkdm_state_switch(clk-clkdm.ptr);
}
#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index 9670ed1..74e0817 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -569,7 +569,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
- pm_dbg_clkdm_state_switch(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
return 0;
}
@@ -622,7 +622,7 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
- pm_dbg_clkdm_state_switch(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1b0272d..a2fa210 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -279,7 +279,7 @@ void omap_sram_idle(void)
disable_smartreflex(SR1);
disable_smartreflex(SR2);
- pm_dbg_pre_suspend();
+ pwrdm_pre_suspend();
/* NEON control */
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
@@ -362,7 +362,7 @@ void omap_sram_idle(void)
enable_smartreflex(SR1);
enable_smartreflex(SR2);
- pm_dbg_post_suspend();
+ pwrdm_post_suspend();
}
/*
@@ -472,7 +472,7 @@ int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
if (sleep_switch) {
cm_rmw_mod_reg_bits(0x3, 0x3, pwrdm-prcm_offs, 0x48);
pwrdm_wait_transition(pwrdm);
- pm_dbg_pwrdm_state_switch(pwrdm);
+ pwrdm_state_switch(pwrdm);
}
err:
@@ -795,7 +795,7 @@ static ssize_t state_store(struct kobject *kobj, struct
kobj_attribute *attr,
return n;
}
-static int __init pwrdms_setup(struct powerdomain *pwrdm)
+static int __init pwrdms_setup(struct powerdomain *pwrdm, void *user)
{
struct power_state *pwrst;
struct kobj_attribute *attr;
@@ -874,7 +874,7 @@ int __init omap3_pm_init(void)
goto err2;
}
- ret = pwrdm_for_each(pwrdms_setup);
+ ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
printk(KERN_ERR Failed to setup powerdomains\n);
goto err2;
--
1.5.6.3
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[PATCH 0/5] Move PM debug counters to normal PM code. Preview with sequence numbers
This patchset makes the PM counters no longer debug only. This will allow drivers to decide if they need to reinitialize the hardware due to an off to on transition. Patchset was made against the pm-0 branch. Peter 'p2' De Schrijver (5): Move some counter functions to powerdomain.c Adapt prototypes for counter functions Move counter function into generic OMAP PM Make counter types unsigned, add closure pointer to pwrdm_for_each, add prototypes Add hooks to PM layer and clock tree for PM counters arch/arm/mach-omap2/clock.c |3 +- arch/arm/mach-omap2/clockdomain.c |4 +- arch/arm/mach-omap2/pm-debug.c| 107 arch/arm/mach-omap2/pm.h | 14 +-- arch/arm/mach-omap2/pm34xx.c | 10 +- arch/arm/mach-omap2/powerdomain.c | 113 +++-- arch/arm/plat-omap/include/mach/powerdomain.h | 13 ++- 7 files changed, 146 insertions(+), 118 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/5] Move some counter functions to powerdomain.c
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c | 107 ++--
1 files changed, 16 insertions(+), 91 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 380a2a0..a375312 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -318,94 +318,20 @@ int pm_dbg_regset_save(int reg_set)
return 0;
}
-static int _pm_dbg_state_switch(struct powerdomain *pwrdm, int flag)
+void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
{
s64 t;
struct timespec now;
- int prev;
- int state;
- if (pwrdm == NULL)
- return -EINVAL;
-
- state = pwrdm_read_pwrst(pwrdm);
-
- switch (flag) {
- case PM_DBG_STATE_NOW:
- prev = pwrdm-state;
- break;
- case PM_DBG_STATE_PREV:
- prev = pwrdm_read_prev_pwrst(pwrdm);
- if (pwrdm-state != prev)
- pwrdm-state_counter[prev]++;
- break;
- default:
- return -EINVAL;
- }
-
- if (pm_dbg_init_done) {
- /* Update timer for previous state */
- getnstimeofday(now);
- t = timespec_to_ns(now);
-
- pwrdm-state_timer[prev] += t - pwrdm-timer;
-
- pwrdm-timer = t;
-
- if (state != prev)
- pwrdm-state_counter[state]++;
- }
-
- pwrdm-state = state;
-
- return 0;
-}
-
-int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm)
-{
- return _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
-}
-
-int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm)
-{
- if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
- pwrdm_wait_transition(clkdm-pwrdm.ptr);
- return pm_dbg_pwrdm_state_switch(clkdm-pwrdm.ptr);
- }
-
- return -EINVAL;
-}
-
-int pm_dbg_clk_state_switch(struct clk *clk)
-{
- if (clk != NULL clk-clkdm.ptr != NULL)
- return pm_dbg_clkdm_state_switch(clk-clkdm.ptr);
- return -EINVAL;
-}
+ if (!pm_dbg_init_done)
+ return;
-static int pm_dbg_pre_suspend_cb(struct powerdomain *pwrdm)
-{
- pwrdm_clear_all_prev_pwrst(pwrdm);
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
- return 0;
-}
-
-static int pm_dbg_post_suspend_cb(struct powerdomain *pwrdm)
-{
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_PREV);
- return 0;
-}
+ getnstimeofday(now);
+ t = timespec_to_ns(now);
-int pm_dbg_pre_suspend(void)
-{
- pwrdm_for_each(pm_dbg_pre_suspend_cb);
- return 0;
-}
+ pwrdm-state_timer[prev] += t - pwrdm-timer;
-int pm_dbg_post_suspend(void)
-{
- pwrdm_for_each(pm_dbg_post_suspend_cb);
- return 0;
+ pwrdm-timer = t;
}
enum {
@@ -489,25 +415,23 @@ int pm_dbg_regset_init(int reg_set)
return 0;
}
-static int __init pwrdms_setup(struct powerdomain *pwrdm)
+int __init _pwrdm_debug_setup(struct powerdomain *pwrdm, void *user)
{
- s64 t;
- int i;
+ s64 t=0;
struct timespec now;
+ int i;
+
+printk(pwrdm: %p\n,pwrdm);
getnstimeofday(now);
t = timespec_to_ns(now);
+ pwrdm-timer = t;
+
for (i = 0; i 4; i++) {
- pwrdm-state_counter[i] = 0;
pwrdm-state_timer[i] = 0;
}
- pwrdm_wait_transition(pwrdm);
- pwrdm-state = pwrdm_read_pwrst(pwrdm);
- pwrdm-state_counter[pwrdm-state] = 1;
- pwrdm-timer = t;
-
(void) debugfs_create_file(pwrdm-name, S_IRUGO|S_IWUSR,
pm_dbg_dir, pwrdm, debug_pwrdm_fops);
@@ -535,7 +459,7 @@ static int __init pm_dbg_init(void)
if (IS_ERR(pm_dbg_dir))
return PTR_ERR(pm_dbg_dir);
- pwrdm_for_each(pwrdms_setup);
+ pwrdm_for_each(_pwrdm_debug_setup, NULL);
pm_dbg_dir = debugfs_create_dir(registers, d);
if (IS_ERR(pm_dbg_dir))
@@ -552,6 +476,7 @@ static int __init pm_dbg_init(void)
}
+
pm_dbg_init_done = 1;
return 0;
--
1.5.6.3
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[PATCH 2/5] Adapt prototypes for counter functions
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/pm.h | 14 -- 1 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index aad4aeb..16212c1 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -45,11 +45,8 @@ struct seq_file; struct clk; struct clockdomain; struct powerdomain; -extern int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm); -extern int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm); -extern int pm_dbg_clk_state_switch(struct clk *clk); -extern int pm_dbg_pre_suspend(void); -extern int pm_dbg_post_suspend(void); +extern int pwrdms_debug_setup(struct powerdomain *pwrdm); +extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); extern int pm_dbg_regset_save(int reg_set); extern int pm_dbg_regset_init(int reg_set); extern int pwrdm_dbg_show_counters(struct seq_file *s, void *unused); @@ -57,11 +54,8 @@ extern int pwrdm_dbg_show_timers(struct seq_file *s, void *unused); extern int clkdm_dbg_show_counters(struct seq_file *s, void *unused); extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); #else -#define pm_dbg_pwrdm_state_switch(domain) do; while (0) -#define pm_dbg_clkdm_state_switch(domain) do; while (0) -#define pm_dbg_clk_state_switch(domain) do; while (0) -#define pm_dbg_pre_suspend() do; while (0) -#define pm_dbg_post_suspend() do; while (0) +#define pwrdms_debug_setup(pwrdm) do ; while (0) +#define pm_dbg_update_time(pwrdm, prev) do ; while (0) #define pm_dbg_regset_save(reg_set) do; while (0) #define pm_dbg_regset_init(reg_set) do; while (0) #define pwrdm_dbg_show_counters(s,unused) do; while (0) -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/5] Make counter types unsigned, add closure pointer to pwrdm_for_each, add prototypes
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/plat-omap/include/mach/powerdomain.h | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h
b/arch/arm/plat-omap/include/mach/powerdomain.h
index 7c3dbb3..c8f194b 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -116,9 +116,10 @@ struct powerdomain {
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
struct list_head node;
-#ifdef CONFIG_PM_DEBUG
+
int state;
- int state_counter[4];
+ unsigned state_counter[4];
+#ifdef CONFIG_PM_DEBUG
s64 timer;
s64 state_timer[4];
#endif
@@ -131,7 +132,8 @@ int pwrdm_register(struct powerdomain *pwrdm);
int pwrdm_unregister(struct powerdomain *pwrdm);
struct powerdomain *pwrdm_lookup(const char *name);
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
@@ -169,4 +171,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_suspend(void);
+int pwrdm_post_suspend(void);
+
#endif
--
1.5.6.3
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Re: [PATCH] Debobs and ETK padconf implementation
The cross-platform gpiolib calls should be used here.
+ snprintf(name, sizeof(name), hw_dbg%d, i);
+ err = _new_debobs_pad(debobs_pads[i], name, i,
+ debobs_root);
+ if (err) {
+ omap_free_gpio(ETK_GPIO(i));
+ return err;
+ }
+ }
+ }
In the successful case, future calls to gpio_request() to use these
lines will fail, since the line is reserved by the omap_request_gpio()
call.
Yes. That's intended. If debobs sucessfully claims the GPIO line, noone
else should be allowed to claim it, unless debobs releases it again.
Cheers,
Peter.
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Re: [PATCH] Debobs and ETK padconf implementation
On Thu, Sep 25, 2008 at 02:40:19PM +0300, ext Kevin Hilman wrote:
Peter 'p2' De Schrijver [EMAIL PROTECTED] writes:
The cross-platform gpiolib calls should be used here.
+snprintf(name, sizeof(name), hw_dbg%d, i);
+err = _new_debobs_pad(debobs_pads[i], name, i,
+debobs_root);
+if (err) {
+omap_free_gpio(ETK_GPIO(i));
+return err;
+}
+}
+}
In the successful case, future calls to gpio_request() to use these
lines will fail, since the line is reserved by the omap_request_gpio()
call.
Yes. That's intended. If debobs sucessfully claims the GPIO line, noone
else should be allowed to claim it, unless debobs releases it again.
In that case, what is the proposed method for other kernel code to use
the debobs lines?
Hmm, good point :) My idea was to use the gpiolib calls on GPIO12 -
GPIO29, but then there is no way for a user to know if the GPIO was
assigned to debobs or not... Maybe debobs should register as gpiolib
'chip' and reexport those lines ? Would that make sense ?
Cheers,
Peter.
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Re: [PATCH] Debobs and ETK padconf implementation
In that case, what is the proposed method for other kernel code to use the debobs lines? Hmm, good point :) My idea was to use the gpiolib calls on GPIO12 - GPIO29, but then there is no way for a user to know if the GPIO was assigned to debobs or not... Maybe debobs should register as gpiolib 'chip' and reexport those lines ? Would that make sense ? Actually, debobs should be claiming IO pads, not GPIOs. Unfortunately there is no way to do that currently :( Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] PM counters
This patch introduces counters for the various PM states in OMAP3. Peter 'p2' De Schrijver (2): PM counter infrastructure. Hook into PM counters arch/arm/mach-omap2/clock.c |2 + arch/arm/mach-omap2/clockdomain.c |4 + arch/arm/mach-omap2/pm34xx.c |6 ++ arch/arm/mach-omap2/powerdomain.c | 94 + arch/arm/plat-omap/include/mach/powerdomain.h |7 ++ 5 files changed, 113 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] PM counter infrastructure.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomain.c | 94 +
arch/arm/plat-omap/include/mach/powerdomain.h |7 ++
2 files changed, 101 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 73e2971..7107eb9 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,6 +35,11 @@
#include mach/powerdomain.h
#include mach/clockdomain.h
+enum {
+ PWRDM_STATE_NOW = 0,
+ PWRDM_STATE_PREV,
+};
+
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
@@ -102,6 +107,63 @@ static struct powerdomain *_pwrdm_deps_lookup(struct
powerdomain *pwrdm,
return pd-pwrdm;
}
+static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+{
+
+ int prev;
+ int state;
+
+ if (pwrdm == NULL)
+ return -EINVAL;
+
+ state = pwrdm_read_pwrst(pwrdm);
+
+ switch (flag) {
+ case PWRDM_STATE_NOW:
+ prev = pwrdm-state;
+ break;
+ case PWRDM_STATE_PREV:
+ prev = pwrdm_read_prev_pwrst(pwrdm);
+ if (pwrdm-state != prev)
+ pwrdm-state_counter[prev]++;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (state != prev)
+ pwrdm-state_counter[state]++;
+
+ pwrdm-state = state;
+
+ return 0;
+}
+
+static int _pwrdm_pre_suspend_cb(struct powerdomain *pwrdm)
+{
+ pwrdm_clear_all_prev_pwrst(pwrdm);
+ _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+ return 0;
+}
+
+static int _pwrdm_post_suspend_cb(struct powerdomain *pwrdm)
+{
+ _pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
+ return 0;
+}
+
+static __init void _pwrdm_setup(struct powerdomain *pwrdm)
+{
+ int i;
+
+ for (i = 0; i 4; i++)
+ pwrdm-state_counter[i] = 0;
+
+ pwrdm_wait_transition(pwrdm);
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+ pwrdm-state_counter[pwrdm-state] = 1;
+
+}
/* Public functions */
@@ -1110,4 +1172,36 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
+int pwrdm_state_switch(struct powerdomain *pwrdm)
+{
+ return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+}
+
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
+{
+ if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm.ptr);
+ return pwrdm_state_switch(clkdm-pwrdm.ptr);
+ }
+
+ return -EINVAL;
+}
+int pwrdm_clk_state_switch(struct clk *clk)
+{
+ if (clk != NULL clk-clkdm.ptr != NULL)
+ return pwrdm_clkdm_state_switch(clk-clkdm.ptr);
+ return -EINVAL;
+}
+
+int pwrdm_pre_suspend(void)
+{
+ pwrdm_for_each(_pwrdm_pre_suspend_cb);
+ return 0;
+}
+
+int pwrdm_post_suspend(void)
+{
+ pwrdm_for_each(_pwrdm_post_suspend_cb);
+ return 0;
+}
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h
b/arch/arm/plat-omap/include/mach/powerdomain.h
index 69c9e67..d80ad4a 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -117,6 +117,8 @@ struct powerdomain {
struct list_head node;
+ int state;
+ unsigned state_counter[4];
};
@@ -164,4 +166,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_suspend(void);
+int pwrdm_post_suspend(void);
+
#endif
--
1.5.6.3
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[PATCH 1/1] Hook into PM counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |2 ++
arch/arm/mach-omap2/clockdomain.c |4
arch/arm/mach-omap2/pm34xx.c |6 ++
3 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c3af24e..dbbc7c8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1013,5 +1013,7 @@ void omap2_clk_disable_unused(struct clk *clk)
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
_omap2_clk_disable(clk);
+ if (clk-clkdm.ptr != NULL)
+ pwrdm_clkdm_state_switch(clk-clkdm.ptr);
}
#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..5249fe8 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
@@ -618,6 +620,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a828db6..5913c4d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
disable_smartreflex(SR1);
disable_smartreflex(SR2);
+ pwrdm_pre_suspend();
+
omap2_gpio_prepare_for_retention();
_omap_sram_idle(NULL, save_state);
@@ -179,6 +181,9 @@ static void omap_sram_idle(void)
/* Enable smartreflex after WFI */
enable_smartreflex(SR1);
enable_smartreflex(SR2);
+
+ pwrdm_post_suspend();
+
}
/*
@@ -260,6 +265,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (sleep_switch) {
omap2_clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
+ pwrdm_state_switch(pwrdm);
}
err:
--
1.5.6.3
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[PATCH 2/2] Hook into PM counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |2 ++
arch/arm/mach-omap2/clockdomain.c |4
arch/arm/mach-omap2/pm34xx.c |6 ++
3 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c3af24e..dbbc7c8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1013,5 +1013,7 @@ void omap2_clk_disable_unused(struct clk *clk)
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
_omap2_clk_disable(clk);
+ if (clk-clkdm.ptr != NULL)
+ pwrdm_clkdm_state_switch(clk-clkdm.ptr);
}
#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..5249fe8 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
@@ -618,6 +620,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a828db6..5913c4d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
disable_smartreflex(SR1);
disable_smartreflex(SR2);
+ pwrdm_pre_suspend();
+
omap2_gpio_prepare_for_retention();
_omap_sram_idle(NULL, save_state);
@@ -179,6 +181,9 @@ static void omap_sram_idle(void)
/* Enable smartreflex after WFI */
enable_smartreflex(SR1);
enable_smartreflex(SR2);
+
+ pwrdm_post_suspend();
+
}
/*
@@ -260,6 +265,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (sleep_switch) {
omap2_clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
+ pwrdm_state_switch(pwrdm);
}
err:
--
1.5.6.3
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Re: [PATCH 1/1] Hook into PM counters
This seems to be duplicate. You can ignore it.
Cheers,
Peter.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |2 ++
arch/arm/mach-omap2/clockdomain.c |4
arch/arm/mach-omap2/pm34xx.c |6 ++
3 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c3af24e..dbbc7c8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1013,5 +1013,7 @@ void omap2_clk_disable_unused(struct clk *clk)
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
_omap2_clk_disable(clk);
+ if (clk-clkdm.ptr != NULL)
+ pwrdm_clkdm_state_switch(clk-clkdm.ptr);
}
#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..5249fe8 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
@@ -618,6 +620,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a828db6..5913c4d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
disable_smartreflex(SR1);
disable_smartreflex(SR2);
+ pwrdm_pre_suspend();
+
omap2_gpio_prepare_for_retention();
_omap_sram_idle(NULL, save_state);
@@ -179,6 +181,9 @@ static void omap_sram_idle(void)
/* Enable smartreflex after WFI */
enable_smartreflex(SR1);
enable_smartreflex(SR2);
+
+ pwrdm_post_suspend();
+
}
/*
@@ -260,6 +265,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (sleep_switch) {
omap2_clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
+ pwrdm_state_switch(pwrdm);
}
err:
--
1.5.6.3
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Re: does twl3040-pwrirq.c need to be a separate file?
Hi David, On Mon, Sep 29, 2008 at 02:17:12PM -0700, ext David Brownell wrote: Hi Peter, I see your patch 68d7477caca19c0b52b5d4e85700cd3e6115577f created pwrirq.c as a separate file and thread. I guess choose this solution because it was similar to the GPIO IRQs. Originally, this was 1 shared IRQ. But I wanted to change this to avoid every driver having to read PWR_ISR1 and clear his interrupt. This saves some i2c transactions. I'm wondering if there's any particular reason that bank of interrupts shouldn't be handled directly by twl4030-core, and even by the same IRQ handling thread. I don't think so. As it stands now the TWL core is not especially core-ish in this respect, and I'd like to see that be resolved (e.g. by a patch I'll probably write this afternoon) before this code goes to mainline ... Ok. Good. Cheers, Peter. -- goa is a state of mind -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] debobs support for OMAP3430.
This patch adds support for debug observability on OMAP3430 using the ETK lines. A new interface for using debug GPIOs is provided. This interface makes sure the debobs subsystem is initialized before actual gpiolib calls are made. Peter 'p2' De Schrijver (3): Add definitions for ETK pads and debobs registers Debobs and ETK padconf implementation Add debobs Kconfig item arch/arm/mach-omap2/Makefile |3 + arch/arm/mach-omap2/debobs.c | 239 + arch/arm/plat-omap/Kconfig|7 + arch/arm/plat-omap/include/mach/control.h | 34 arch/arm/plat-omap/include/mach/debobs.h |7 + 5 files changed, 290 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-omap2/debobs.c create mode 100644 arch/arm/plat-omap/include/mach/debobs.h -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3] Add debobs Kconfig item
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/mach-omap2/Makefile |3 +++ arch/arm/plat-omap/Kconfig |7 +++ 2 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e18da0c..a30d5ff 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -40,6 +40,9 @@ obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o mmu_mach-objs := mmu.o +# Debobs +obj-$(CONFIG_OMAP3_DEBOBS) += debobs.o + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC)+= board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o board-h4-mmc.o diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 960c13f..ebcfd27 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -205,6 +205,13 @@ config OMAP_32K_TIMER endchoice +config OMAP3_DEBOBS + bool OMAP 3430 Debug observability support + depends on ARCH_OMAP3 DEBUG_FS + default n + help + Use ETK pads for debug observability + config OMAP_32K_TIMER_HZ int Kernel internal timer frequency for 32KHz timer range 32 1024 -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] Add definitions for ETK pads and debobs registers
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED] --- arch/arm/plat-omap/include/mach/control.h | 34 + 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h index 9ca0e08..0ea0060 100644 --- a/arch/arm/plat-omap/include/mach/control.h +++ b/arch/arm/plat-omap/include/mach/control.h @@ -150,6 +150,40 @@ #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ + + ((i) 1) * 4 + (!(i) 1) * 2) +/* 34xx PADCONF register offsets */ + +#define OMAP343X_PADCONF_ETK(i)(OMAP2_CONTROL_PADCONFS + 0x5a8 + \ + (i)*2) +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) +#define OMAP343X_PADCONF_ETK_D0OMAP343X_PADCONF_ETK(2) +#define OMAP343X_PADCONF_ETK_D1OMAP343X_PADCONF_ETK(3) +#define OMAP343X_PADCONF_ETK_D2OMAP343X_PADCONF_ETK(4) +#define OMAP343X_PADCONF_ETK_D3OMAP343X_PADCONF_ETK(5) +#define OMAP343X_PADCONF_ETK_D4OMAP343X_PADCONF_ETK(6) +#define OMAP343X_PADCONF_ETK_D5OMAP343X_PADCONF_ETK(7) +#define OMAP343X_PADCONF_ETK_D6OMAP343X_PADCONF_ETK(8) +#define OMAP343X_PADCONF_ETK_D7OMAP343X_PADCONF_ETK(9) +#define OMAP343X_PADCONF_ETK_D8OMAP343X_PADCONF_ETK(10) +#define OMAP343X_PADCONF_ETK_D9OMAP343X_PADCONF_ETK(11) +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) + +/* 34xx GENERAL_WKUP regist offsets */ + +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ + 0x008 + (i)) +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) /* * REVISIT: This list of registers is not comprehensive - there are more -- 1.5.6.3 -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] Debobs and ETK padconf implementation
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/debobs.c | 239 ++
arch/arm/plat-omap/include/mach/debobs.h |7 +
2 files changed, 246 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-omap2/debobs.c
create mode 100644 arch/arm/plat-omap/include/mach/debobs.h
diff --git a/arch/arm/mach-omap2/debobs.c b/arch/arm/mach-omap2/debobs.c
new file mode 100644
index 000..4fbabef
--- /dev/null
+++ b/arch/arm/mach-omap2/debobs.c
@@ -0,0 +1,239 @@
+/*
+ * arch/arm/mach-omap2/debobs.c
+ *
+ * Handle debobs pads
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * Written by Peter De Schrijver [EMAIL PROTECTED]
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+
+#include linux/kernel.h
+#include linux/init.h
+#include linux/debugfs.h
+#include linux/uaccess.h
+#include linux/module.h
+#include mach/control.h
+#include mach/mux.h
+#include mach/gpio.h
+#include mach/board.h
+
+#define ETK_GPIO_BEGIN 12
+#define ETK_GPIO(i)(ETK_GPIO_BEGIN + i)
+#define NUM_OF_DEBOBS_PADS 18
+
+static int debobs_initialized;
+
+enum debobs_pad_mode {
+ GPIO = 0,
+ OBS = 1,
+ ETK = 2,
+ NO_MODE = 3,
+};
+
+static char *debobs_pad_mode_names[] = {
+ [GPIO] = GPIO,
+ [OBS] = OBS,
+ [ETK] = ETK,
+};
+
+struct obs {
+ u16 offset;
+ u8 value;
+ u8 mask;
+};
+
+struct debobs_pad {
+ enum debobs_pad_mode mode;
+ struct obs core_obs;
+ struct obs wakeup_obs;
+};
+
+static struct debobs_pad debobs_pads[NUM_OF_DEBOBS_PADS];
+
+static int debobs_mode_open(struct inode *inode, struct file *file)
+{
+ file-private_data = inode-i_private;
+
+ return 0;
+}
+
+static ssize_t debobs_mode_read(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ char buffer[10];
+ int size;
+ int pad_number = (int)file-private_data;
+ struct debobs_pad *e = debobs_pads[pad_number];
+
+ size = snprintf(buffer, sizeof(buffer), %s\n,
+ debobs_pad_mode_names[e-mode]);
+ return simple_read_from_buffer(user_buf, count, ppos, buffer, size);
+}
+
+static ssize_t debobs_mode_write(struct file *file, const char __user
*user_buf,
+ size_t count, loff_t *ppos)
+{
+ char buffer[10];
+ int buf_size, i, pad_number;
+ u16 muxmode = OMAP34XX_MUX_MODE7;
+
+ memset(buffer, 0, sizeof(buffer));
+ buf_size = min(count, (sizeof(buffer)-1));
+
+ if (copy_from_user(buffer, user_buf, buf_size))
+ return -EFAULT;
+
+ pad_number = (int)file-private_data;
+
+ for (i = 0; i NO_MODE; i++) {
+ if (!strnicmp(debobs_pad_mode_names[i],
+ buffer,
+ strlen(debobs_pad_mode_names[i]))) {
+ switch (i) {
+ case ETK:
+ muxmode = OMAP34XX_MUX_MODE0;
+ break;
+ case GPIO:
+ muxmode = OMAP34XX_MUX_MODE4;
+ break;
+ case OBS:
+ muxmode = OMAP34XX_MUX_MODE7;
+ break;
+ }
+ omap_ctrl_writew(muxmode,
+ OMAP343X_PADCONF_ETK(pad_number));
+ debobs_pads[pad_number].mode = i;
+
+ return count;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct file_operations debobs_mode_fops = {
+ .open = debobs_mode_open,
+ .read = debobs_mode_read,
+ .write = debobs_mode_write,
+};
+
+static int debobs_get(void *data, u64 *val)
+{
+ struct obs *o = data;
+
+ *val = o-value;
+
+ return 0;
+}
+
+static int debobs_set(void *data, u64 val)
+{
+ struct obs *o = data;
+
+ val = BIT(o-mask) - 1;
+
+ omap_ctrl_writeb(val, o-offset);
+ o-value = val;
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(debobs_fops, debobs_get, debobs_set, %llu\n);
+
+static inline int __init _new_debobs_pad(struct debobs_pad *pad, char *name,
+ int number, struct dentry
[PATCH 0/2] PM counters
This patch introduces counters for the various PM states in OMAP3. Peter 'p2' De Schrijver (2): PM counter infrastructure. Hook into PM counters arch/arm/mach-omap2/clock.c |2 + arch/arm/mach-omap2/clockdomain.c |4 + arch/arm/mach-omap2/pm34xx.c |6 ++ arch/arm/mach-omap2/powerdomain.c | 94 + arch/arm/plat-omap/include/mach/powerdomain.h |7 ++ 5 files changed, 113 insertions(+), 0 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-omap in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/2] Hook into PM counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |2 ++
arch/arm/mach-omap2/clockdomain.c |4
arch/arm/mach-omap2/pm34xx.c |6 ++
3 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c3af24e..dbbc7c8 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -1013,5 +1013,7 @@ void omap2_clk_disable_unused(struct clk *clk)
printk(KERN_INFO Disabling unused clock \%s\\n, clk-name);
_omap2_clk_disable(clk);
+ if (clk-clkdm.ptr != NULL)
+ pwrdm_clkdm_state_switch(clk-clkdm.ptr);
}
#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..5249fe8 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
@@ -618,6 +620,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+
return 0;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index a828db6..1fbb690 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
disable_smartreflex(SR1);
disable_smartreflex(SR2);
+ pwrdm_pre_transition();
+
omap2_gpio_prepare_for_retention();
_omap_sram_idle(NULL, save_state);
@@ -179,6 +181,9 @@ static void omap_sram_idle(void)
/* Enable smartreflex after WFI */
enable_smartreflex(SR1);
enable_smartreflex(SR2);
+
+ pwrdm_post_transition();
+
}
/*
@@ -260,6 +265,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32
state)
if (sleep_switch) {
omap2_clkdm_allow_idle(pwrdm-pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
+ pwrdm_state_switch(pwrdm);
}
err:
--
1.5.6.3
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[PATCH 1/2] PM counter infrastructure.
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomain.c | 94 +
arch/arm/plat-omap/include/mach/powerdomain.h |7 ++
2 files changed, 101 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index 73e2971..349b7ab 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,6 +35,11 @@
#include mach/powerdomain.h
#include mach/clockdomain.h
+enum {
+ PWRDM_STATE_NOW = 0,
+ PWRDM_STATE_PREV,
+};
+
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
@@ -102,6 +107,63 @@ static struct powerdomain *_pwrdm_deps_lookup(struct
powerdomain *pwrdm,
return pd-pwrdm;
}
+static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
+{
+
+ int prev;
+ int state;
+
+ if (pwrdm == NULL)
+ return -EINVAL;
+
+ state = pwrdm_read_pwrst(pwrdm);
+
+ switch (flag) {
+ case PWRDM_STATE_NOW:
+ prev = pwrdm-state;
+ break;
+ case PWRDM_STATE_PREV:
+ prev = pwrdm_read_prev_pwrst(pwrdm);
+ if (pwrdm-state != prev)
+ pwrdm-state_counter[prev]++;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (state != prev)
+ pwrdm-state_counter[state]++;
+
+ pwrdm-state = state;
+
+ return 0;
+}
+
+static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm)
+{
+ pwrdm_clear_all_prev_pwrst(pwrdm);
+ _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+ return 0;
+}
+
+static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm)
+{
+ _pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
+ return 0;
+}
+
+static __init void _pwrdm_setup(struct powerdomain *pwrdm)
+{
+ int i;
+
+ for (i = 0; i 4; i++)
+ pwrdm-state_counter[i] = 0;
+
+ pwrdm_wait_transition(pwrdm);
+ pwrdm-state = pwrdm_read_pwrst(pwrdm);
+ pwrdm-state_counter[pwrdm-state] = 1;
+
+}
/* Public functions */
@@ -1110,4 +1172,36 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
+int pwrdm_state_switch(struct powerdomain *pwrdm)
+{
+ return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
+}
+
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
+{
+ if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
+ pwrdm_wait_transition(clkdm-pwrdm.ptr);
+ return pwrdm_state_switch(clkdm-pwrdm.ptr);
+ }
+
+ return -EINVAL;
+}
+int pwrdm_clk_state_switch(struct clk *clk)
+{
+ if (clk != NULL clk-clkdm.ptr != NULL)
+ return pwrdm_clkdm_state_switch(clk-clkdm.ptr);
+ return -EINVAL;
+}
+
+int pwrdm_pre_transition(void)
+{
+ pwrdm_for_each(_pwrdm_pre_transition_cb);
+ return 0;
+}
+
+int pwrdm_post_transition(void)
+{
+ pwrdm_for_each(_pwrdm_post_transition_cb);
+ return 0;
+}
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h
b/arch/arm/plat-omap/include/mach/powerdomain.h
index 69c9e67..52663fc 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -117,6 +117,8 @@ struct powerdomain {
struct list_head node;
+ int state;
+ unsigned state_counter[4];
};
@@ -164,4 +166,9 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_transition(void);
+int pwrdm_post_transition(void);
+
#endif
--
1.5.6.3
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[PATCH 3/3] Add twl4030 power platform device
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/twl4030-core.c | 41 ++
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
index 9debab4..42d9e4f 100644
--- a/drivers/i2c/chips/twl4030-core.c
+++ b/drivers/i2c/chips/twl4030-core.c
@@ -70,6 +70,12 @@
#define twl_has_madc() false
#endif
+#ifdef CONFIG_TWL4030_POWER
+#define twl_has_power()true
+#else
+#define twl_has_power()false
+#endif
+
#if defined(CONFIG_RTC_DRV_TWL4030) || defined(CONFIG_RTC_DRV_TWL4030_MODULE)
#define twl_has_rtc() true
#else
@@ -838,6 +844,41 @@ static int add_children(struct twl4030_platform_data
*pdata)
}
}
+ if (twl_has_power() pdata-power) {
+ twl = twl4030_modules[TWL4030_SLAVENUM_NUM3];
+
+ pdev = platform_device_alloc(twl4030_power, -1);
+ if (!pdev) {
+ pr_debug(%s: can't alloc power dev\n, DRIVER_NAME);
+ status = -ENOMEM;
+ goto err;
+ }
+
+ if (status == 0) {
+ pdev-dev.parent = twl-client-dev;
+ status = platform_device_add_data(pdev, pdata-power,
+ sizeof(*pdata-power));
+ if (status 0) {
+ platform_device_put(pdev);
+ dev_dbg(twl-client-dev,
+ can't add power data, %d\n,
+ status);
+ goto err;
+ }
+ }
+
+ if (status == 0)
+ status = platform_device_add(pdev);
+
+ if (status 0) {
+ platform_device_put(pdev);
+ dev_dbg(twl-client-dev,
+ can't create power dev, %d\n,
+ status);
+ goto err;
+ }
+ }
+
if (twl_has_rtc()) {
twl = twl4030_modules[TWL4030_SLAVENUM_NUM3];
--
1.5.6.3
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[PATCH 2/3] Adapt twl4030 power code to new twl4030 code
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/i2c/chips/twl4030-power.c | 290 +++--
include/linux/i2c/twl4030.h | 64
2 files changed, 181 insertions(+), 173 deletions(-)
diff --git a/drivers/i2c/chips/twl4030-power.c
b/drivers/i2c/chips/twl4030-power.c
index cb325b0..4a543a2 100644
--- a/drivers/i2c/chips/twl4030-power.c
+++ b/drivers/i2c/chips/twl4030-power.c
@@ -26,17 +26,20 @@
#include linux/module.h
#include linux/pm.h
#include linux/i2c/twl4030.h
+#include linux/platform_device.h
#include asm/mach-types.h
+static u8 triton_next_free_address = 0x2b;
+
#define PWR_P1_SW_EVENTS 0x10
#define PWR_DEVOFF (10)
#define PHY_TO_OFF_PM_MASTER(p)(p - 0x36)
-#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
+#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
/* resource - hfclk */
-#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECIEVER(0xe6)
+#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
/* PM events */
#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
@@ -50,8 +53,6 @@
#define ENABLE_WARMRESET (14)
-/* sequence script */
-
#define END_OF_SCRIPT 0x3f
#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
@@ -61,112 +62,10 @@
#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
-/* Power bus message definitions */
-
-#define DEV_GRP_NULL 0x0
-#define DEV_GRP_P1 0x1
-#define DEV_GRP_P2 0x2
-#define DEV_GRP_P3 0x4
-
-#define RES_GRP_RES0x0
-#define RES_GRP_PP 0x1
-#define RES_GRP_RC 0x2
-#define RES_GRP_PP_RC 0x3
-#define RES_GRP_PR 0x4
-#define RES_GRP_PP_PR 0x5
-#define RES_GRP_RC_PR 0x6
-#define RES_GRP_ALL0x7
-
-#define RES_TYPE2_R0 0x0
-
-#define RES_TYPE_ALL 0x7
-
-#define RES_STATE_WRST 0xF
-#define RES_STATE_ACTIVE 0xE
-#define RES_STATE_SLEEP0x8
-#define RES_STATE_OFF 0x0
-
-/*
-* Power Bus Message Format
-*
-* Broadcast Message (16 Bits)
-* DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
-* RES_STATE[3:0]
-*
-* Singular Message (16 Bits)
-* DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
-*
-*/
-
-#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
- (devgrp 13 | 1 12 | grp 9 | type2 7 | type 4 | state)
-
-#define MSG_SINGULAR(devgrp, id, state) \
- (devgrp 13 | 0 12 | id 4 | state)
-
#define R_PROTECT_KEY 0x0E
#define KEY_1 0xC0
#define KEY_2 0x0C
-struct triton_ins {
- u16 pmb_message;
- u8 delay;
-};
-
-
-#define CONFIG_DISABLE_HFCLK 1
-
-#if defined(CONFIG_MACH_OMAP_3430SDP) || defined(CONFIG_MACH_OMAP_3430LABRADOR)
-
-struct triton_ins sleep_on_seq[] __initdata = {
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
-#ifdef CONFIG_DISABLE_HFCLK
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_OFF), 3},
-#endif /* #ifdef CONFIG_DISABLE_HFCLK */
-};
-
-struct triton_ins sleep_off_seq[] __initdata = {
-#ifndef CONFIG_DISABLE_HFCLK
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 4},
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 2},
-#else
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
-#endif /* #ifndef CONFIG_DISABLE_HFCLK */
-};
-
-struct triton_ins t2_wrst_seq[] __initdata = {
- {MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_OFF), 2},
- {MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_WRST), 15},
- {MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_WRST), 15},
- {MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_WRST), 0x60},
- {MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 2},
- {MSG_SINGULAR(DEV_GRP_NULL, 0x1b, RES_STATE_ACTIVE), 2},
-};
-#else
-struct triton_ins sleep_on_seq[] __initdata = {
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_RC, RES_TYPE_ALL, RES_TYPE2_R0,
- RES_STATE_SLEEP), 4},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
- RES_STATE_SLEEP), 4},
-};
-
-struct triton_ins sleep_off_seq[] __initdata = {
- {MSG_SINGULAR(DEV_GRP_NULL, 0x17, RES_STATE_ACTIVE), 0x30},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP_PR, RES_TYPE_ALL, RES_TYPE2_R0,
- RES_STATE_ACTIVE), 0x37},
- {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, RES_TYPE_ALL, RES_TYPE2_R0,
- RES_STATE_ACTIVE), 0x2},
-};
-
-struct triton_ins t2_wrst_seq[] __initdata = { };
-
-#endif
[PATCH 2/3] Add pm-debug counters
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm-debug.c| 153 -
arch/arm/mach-omap2/pm.h | 19 +---
arch/arm/plat-omap/include/mach/powerdomain.h | 14 ++-
3 files changed, 87 insertions(+), 99 deletions(-)
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 380a2a0..64d40c4 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -167,8 +167,8 @@ struct dentry *pm_dbg_dir;
static int pm_dbg_init_done;
enum {
- PM_DBG_STATE_NOW = 0,
- PM_DBG_STATE_PREV,
+ DEBUG_FILE_COUNTERS = 0,
+ DEBUG_FILE_TIMERS,
};
struct pm_module_def {
@@ -218,6 +218,13 @@ static const struct pm_module_def pm_dbg_reg_modules[] = {
static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
+static const char pwrdm_state_names[][4] = {
+ OFF,
+ RET,
+ INA,
+ ON
+};
+
static int pm_dbg_get_regset_size(void)
{
static int regset_size;
@@ -318,107 +325,96 @@ int pm_dbg_regset_save(int reg_set)
return 0;
}
-static int _pm_dbg_state_switch(struct powerdomain *pwrdm, int flag)
+void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
{
s64 t;
struct timespec now;
- int prev;
- int state;
- if (pwrdm == NULL)
- return -EINVAL;
+ if (!pm_dbg_init_done)
+ return ;
- state = pwrdm_read_pwrst(pwrdm);
+ /* Update timer for previous state */
+ getnstimeofday(now);
+ t = timespec_to_ns(now);
- switch (flag) {
- case PM_DBG_STATE_NOW:
- prev = pwrdm-state;
- break;
- case PM_DBG_STATE_PREV:
- prev = pwrdm_read_prev_pwrst(pwrdm);
- if (pwrdm-state != prev)
- pwrdm-state_counter[prev]++;
- break;
- default:
- return -EINVAL;
- }
+ pwrdm-state_timer[prev] += t - pwrdm-timer;
- if (pm_dbg_init_done) {
- /* Update timer for previous state */
- getnstimeofday(now);
- t = timespec_to_ns(now);
+ pwrdm-timer = t;
- pwrdm-state_timer[prev] += t - pwrdm-timer;
+}
- pwrdm-timer = t;
+static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
+{
+ struct seq_file *s = (struct seq_file *)user;
- if (state != prev)
- pwrdm-state_counter[state]++;
- }
+ if (strcmp(clkdm-name, emu_clkdm) == 0 ||
+ strcmp(clkdm-name, wkup_clkdm) == 0)
+ return 0;
- pwrdm-state = state;
+ seq_printf(s, %s-%s (%d), clkdm-name,
+ clkdm-pwrdm.ptr-name,
+ atomic_read(clkdm-usecount));
+ seq_printf(s, \n);
return 0;
}
-int pm_dbg_pwrdm_state_switch(struct powerdomain *pwrdm)
+static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
{
- return _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
-}
+ struct seq_file *s = (struct seq_file *)user;
+ int i;
-int pm_dbg_clkdm_state_switch(struct clockdomain *clkdm)
-{
- if (clkdm != NULL clkdm-pwrdm.ptr != NULL) {
- pwrdm_wait_transition(clkdm-pwrdm.ptr);
- return pm_dbg_pwrdm_state_switch(clkdm-pwrdm.ptr);
- }
+ if (strcmp(pwrdm-name, emu_pwrdm) == 0 ||
+ strcmp(pwrdm-name, wkup_pwrdm) == 0)
+ return 0;
- return -EINVAL;
-}
+ if (pwrdm-state != pwrdm_read_pwrst(pwrdm))
+ printk(KERN_ERR pwrdm state mismatch(%s) %d != %d\n,
+ pwrdm-name, pwrdm-state, pwrdm_read_pwrst(pwrdm));
-int pm_dbg_clk_state_switch(struct clk *clk)
-{
- if (clk != NULL clk-clkdm.ptr != NULL)
- return pm_dbg_clkdm_state_switch(clk-clkdm.ptr);
- return -EINVAL;
-}
+ seq_printf(s, %s (%s), pwrdm-name,
+ pwrdm_state_names[pwrdm-state]);
+ for (i = 0; i 4; i++)
+ seq_printf(s, ,%s:%d, pwrdm_state_names[i],
+ pwrdm-state_counter[i]);
-static int pm_dbg_pre_suspend_cb(struct powerdomain *pwrdm)
-{
- pwrdm_clear_all_prev_pwrst(pwrdm);
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_NOW);
- return 0;
-}
+ seq_printf(s, \n);
-static int pm_dbg_post_suspend_cb(struct powerdomain *pwrdm)
-{
- _pm_dbg_state_switch(pwrdm, PM_DBG_STATE_PREV);
return 0;
}
-int pm_dbg_pre_suspend(void)
+static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
{
- pwrdm_for_each(pm_dbg_pre_suspend_cb);
+ struct seq_file *s = (struct seq_file *)user;
+ int i;
+
+ if (strcmp(pwrdm-name, emu_pwrdm) == 0 ||
+ strcmp(pwrdm-name, wkup_pwrdm) == 0)
+ return 0;
+
+ pwrdm_state_switch(pwrdm);
+
+ seq_printf(s, %s (%s
Re: [PATCH 2/3] Adapt twl4030 power code to new twl4030 code
Hi David,
Your set of patches seems to have discarded support for quite
a few platforms. I don't quite know the details of what these
PM scripts are doing ... could they be misbehaving on Beagle,
so that they explain why reboot on RC8 fails?
It might. At least the warmreset script might cause problems on Beagle.
I'm not familiar enough with beagle to know for sure.
+static int __init twl4030_power_probe(struct platform_device *pdev)
Pretty much everything here is init code, which is fine;
I like seeing smaller runtime images. But:
@@ -340,4 +271,17 @@ static int __init twl4030_power_init(void)
}
+static struct platform_driver twl4030_power = {
+ .probe = twl4030_power_probe,
+ .driver = {
+ .name = twl4030_power,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init twl4030_power_init(void)
+{
+ return platform_driver_register(twl4030_power);
... in that case, why not platform_driver_probe(), so there's
not even a whiff of a notion that this driver remain init is
done?
That's correct. The 'driver' basically loads the scripts in the twl4030 and
that's it. The hw will then execute the scripts when necessary.
And I can't help but wonder why this isn't just part of
the twl4030-core code, without even a platform device/driver.
If you think all this script loading stuff can go into twl4030-core, I
can make a patch to move it there.
I didn't move it to drivers/mfd because it seemed almost all
SDP-specific. But to the extent that it's something generic
and part of the core, maybe that's where it should be.
Not necessarily part of the same file.
It's not SDP specific, but it is OMAP specific I think. At least I can't
see use cases outside OMAP2/3.
Cheers,
Peter.
--
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[PATCH 3/7] Twl4030 power code updated for new twl4030 core
This patch adds the twl4030 power handling. It downloads the scripts provided
by the board configuration to the twl4030 and configures the chip to call
the relevant script for each event (processor group 1 and 2 sleep,
processor group 3 sleep, wakeup or warm reset).
Signed-off-by: Peter 'p2' De Schrijver [EMAIL PROTECTED]
---
drivers/mfd/twl4030-power.c | 270 +++
1 files changed, 270 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/twl4030-power.c
diff --git a/drivers/mfd/twl4030-power.c b/drivers/mfd/twl4030-power.c
new file mode 100644
index 000..bdeac36
--- /dev/null
+++ b/drivers/mfd/twl4030-power.c
@@ -0,0 +1,270 @@
+/*
+ * linux/drivers/i2c/chips/twl4030-power.c
+ *
+ * Handle TWL4030 Power initialization
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2006 Texas Instruments, Inc
+ *
+ * Written by Kalle Jokiniemi
+ * Peter De Schrijver [EMAIL PROTECTED]
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License. See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include linux/module.h
+#include linux/pm.h
+#include linux/i2c/twl4030.h
+#include linux/platform_device.h
+
+#include asm/mach-types.h
+
+static u8 triton_next_free_address = 0x2b;
+
+#define PWR_P1_SW_EVENTS 0x10
+#define PWR_DEVOFF (10)
+
+#define PHY_TO_OFF_PM_MASTER(p)(p - 0x36)
+#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
+
+/* PM events */
+#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITIONPHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITIONPHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITIONPHY_TO_OFF_PM_MASTER(0x38)
+
+#define LVL_WAKEUP 0x08
+
+#define ENABLE_WARMRESET (14)
+
+#define END_OF_SCRIPT 0x3f
+
+#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12 PHY_TO_OFF_PM_MASTER(0x56)
+#defineR_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
+#defineR_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
+#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
+
+#define R_PROTECT_KEY 0x0E
+#define KEY_1 0xC0
+#define KEY_2 0x0C
+
+static int __init twl4030_write_script_byte(u8 address, u8 byte)
+{
+ int err;
+
+ err = twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
+ R_MEMORY_ADDRESS);
+ err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, byte,
+ R_MEMORY_DATA);
+
+ return err;
+}
+
+static int __init twl4030_write_script_ins(u8 address, u16 pmb_message,
+ u8 delay, u8 next)
+{
+ int err = 0;
+
+ address *= 4;
+ err |= twl4030_write_script_byte(address++, pmb_message 8);
+ err |= twl4030_write_script_byte(address++, pmb_message 0xff);
+ err |= twl4030_write_script_byte(address++, delay);
+ err |= twl4030_write_script_byte(address++, next);
+
+ return err;
+}
+
+static int __init twl4030_write_script(u8 address, struct twl4030_ins *script,
+ int len)
+{
+ int err = 0;
+
+ for (; len; len--, address++, script++) {
+ if (len == 1)
+ err |= twl4030_write_script_ins(address,
+ script-pmb_message,
+ script-delay,
+ END_OF_SCRIPT);
+ else
+ err |= twl4030_write_script_ins(address,
+ script-pmb_message,
+ script-delay,
+ address + 1);
+ }
+
+ return err;
+}
+
+static int __init config_wakeup3_sequence(u8 address)
+{
+
+ int err = 0;
+
+ /* Set SLEEP to ACTIVE SEQ address for P3 */
+ err |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, address,
+ R_SEQ_ADD_S2A3
