On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote:
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent: Friday, November 19, 2010 9:37 AM
On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com
wrote:
On Thu, Nov 18, 2010 at
Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes:
On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote:
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent: Friday, November 19, 2010 9:37 AM
On Thu, Nov 18, 2010 at 7:34 PM, Jean
On Mon, Nov 22, 2010 at 5:03 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes:
On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote:
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
On Mon, Nov 22, 2010 at 05:03:59PM +0100, ext Kevin Hilman wrote:
Peter 'p2' De Schrijver peter.de-schrij...@nokia.com writes:
On Fri, Nov 19, 2010 at 05:14:15PM +0100, ext Derrick, David wrote:
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent:
Peter 'p2' De Schrijver had written, on 11/22/2010 10:22 AM, the following:
[...]
The root cause for the DLL not locking has been found though and a
workaround implemented. So it should work now :)
Is the workaround for this reflected in Nishanth's series?
No. It seems not. The workaround
Nishanth Menon n...@ti.com writes:
Peter 'p2' De Schrijver had written, on 11/22/2010 10:22 AM, the following:
[...]
The root cause for the DLL not locking has been found though and a
workaround implemented. So it should work now :)
Is the workaround for this reflected in Nishanth's series?
Kevin Hilman had written, on 11/22/2010 12:23 PM, the following:
Nishanth Menon n...@ti.com writes:
Peter 'p2' De Schrijver had written, on 11/22/2010 10:22 AM, the following:
[...]
The root cause for the DLL not locking has been found though and a
workaround implemented. So it should work
HI Tony,
On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [101118 10:06]:
On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote:
About the
* Jean Pihet jean.pi...@newoldbits.com [101119 07:27]:
HI Tony,
On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [101118 10:06]:
On Thu, Nov 18, 2010
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent: Friday, November 19, 2010 9:37 AM
On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet
On Fri, Nov 19, 2010 at 5:14 PM, Derrick, David dderr...@ti.com wrote:
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent: Friday, November 19, 2010 9:37 AM
On Thu, Nov 18, 2010 at 7:34 PM, Jean Pihet jean.pi...@newoldbits.com
wrote:
On Thu, Nov 18, 2010 at 7:27
From: Vishwanath BS vishwanath...@ti.com
For historical reasons the OMAP3 sleep code is run from SRAM.
This code can run from DDR which provides better performance and
leaves the SRAM available for other uses.
Tested on ZOOM3, OMAP3EVM, Beagleboard, n900
with full RET and OFF modes.
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Jean Pihet
Sent: Thursday, November 18, 2010 8:52 AM
To: linux-omap@vger.kernel.org
Cc: Vishwanath BS; Kevin Hillman; Jean Pihet
Subject: [PATCH 1/2] OMAP3 PM: move
: Vishwanath BS; Kevin Hillman; Jean Pihet
Subject: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
From: Vishwanath BS vishwanath...@ti.com
For historical reasons the OMAP3 sleep code is run from SRAM.
This code can run from DDR which provides better performance and
leaves the SRAM available
-Original Message-
From: Sripathy, Vishwanath [mailto:vishwanath...@ti.com]
Sent: Thursday, November 18, 2010 9:09 AM
To: Nishanth Menon
Cc: Jean Pihet; linux-omap@vger.kernel.org; Kevin Hillman; Jean
Pihet-XID
Subject: Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
NIshant
Pihet-XID
Subject: Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
NIshant,
On Thu, Nov 18, 2010 at 8:27 PM, Nishanth Menon n...@ti.com wrote:
-Original Message-
From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
ow...@vger.kernel.org] On Behalf Of Jean Pihet
Sent
-Original Message-
From: Jean Pihet [mailto:jean.pi...@newoldbits.com]
Sent: Thursday, November 18, 2010 9:15 AM
[...]
Tested on ZOOM3, OMAP3EVM, Beagleboard, n900
with full RET and OFF modes.
Sorry, But I disagree with this patch.
There is a silicon errata which
Nishanth Menon n...@ti.com writes:
From: Vishwanath BS vishwanath...@ti.com
For historical reasons the OMAP3 sleep code is run from SRAM.
This code can run from DDR which provides better performance and
leaves the SRAM available for other uses.
Tested on ZOOM3, OMAP3EVM, Beagleboard, n900
Kevin Hilman had written, on 11/18/2010 09:52 AM, the following:
Nishanth Menon n...@ti.com writes:
From: Vishwanath BS vishwanath...@ti.com
For historical reasons the OMAP3 sleep code is run from SRAM.
This code can run from DDR which provides better performance and
leaves the SRAM available
* Nishanth Menon n...@ti.com [101118 08:46]:
But after wfi in wait_sdrc_ok as part of the code executing in SRAM
today omap34xx_cpu_suspend - we are waiting for DPLL3 lock prior to
accessing DDR - how do we execute that logic in SDRAM?
I too am a bit concerned how this will all keep working.
* Tony Lindgren t...@atomide.com [101118 09:42]:
* Nishanth Menon n...@ti.com [101118 08:46]:
But after wfi in wait_sdrc_ok as part of the code executing in SRAM
today omap34xx_cpu_suspend - we are waiting for DPLL3 lock prior to
accessing DDR - how do we execute that logic in SDRAM?
On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote:
* Nishanth Menon n...@ti.com [101118 08:46]:
But after wfi in wait_sdrc_ok as part of the code executing in SRAM
today omap34xx_cpu_suspend - we are waiting for DPLL3 lock prior to
accessing DDR - how do we execute that
* Jean Pihet jean.pi...@newoldbits.com [101118 10:06]:
On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote:
About the DPLL lock:
1) wait_sdrc_ok is only called when back from the non-OFF modes,
2) I checked that when running wait_sdrc_ok the CORE is already out of
idle and
On Thu, Nov 18, 2010 at 7:27 PM, Tony Lindgren t...@atomide.com wrote:
* Jean Pihet jean.pi...@newoldbits.com [101118 10:06]:
On Thu, Nov 18, 2010 at 6:52 PM, Tony Lindgren t...@atomide.com wrote:
About the DPLL lock:
1) wait_sdrc_ok is only called when back from the non-OFF modes,
2) I
Kevin,
-Original Message-
From: Kevin Hilman [mailto:khil...@deeprootsystems.com]
Sent: Saturday, September 25, 2010 1:28 AM
To: Sripathy, Vishwanath
Cc: linux-omap@vger.kernel.org; linaro-...@lists.linaro.org
Subject: Re: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
Vishwanath
* Vishwanath BS vishwanath...@ti.com [100924 03:50]:
There is no need to keep omap3 sleep code in SRAM. This code can be run very
well on DDR. This would help us to instrument CPUIdle latencies.
Uhh, are you sure about this? To me it sounds like you're then
relying on the code running from the
* Tony Lindgren t...@atomide.com [100924 11:53]:
* Vishwanath BS vishwanath...@ti.com [100924 03:50]:
There is no need to keep omap3 sleep code in SRAM. This code can be run very
well on DDR. This would help us to instrument CPUIdle latencies.
Uhh, are you sure about this? To me it sounds
Vishwanath BS vishwanath...@ti.com writes:
There is no need to keep omap3 sleep code in SRAM.
This code can be run very well on DDR.
/me remains skeptical
This would help us to instrument CPUIdle latencies.
Indeed, but...
I'm afraid we will need a much more descriptive changelog here,
: [PATCH 1/2] OMAP3 PM: move omap3 sleep to ddr
* Tony Lindgren t...@atomide.com [100924 11:53]:
* Vishwanath BS vishwanath...@ti.com [100924 03:50]:
There is no need to keep omap3 sleep code in SRAM. This code can be
run very
well on DDR. This would help us to instrument CPUIdle
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