Hi Vignesh,
Le 30/11/2015 06:15, Vignesh R a écrit :
> Certain spi controllers may provide accelerated interface to read from
> m25p80 type flash devices. This interface provides better read
> performance than regular SPI interface.
> Call spi_flash_read(), if supported, to make use of such
On 12/01/2015 10:09 PM, Tony Lindgren wrote:
> * Vignesh R [151130 20:46]:
>> On 12/01/2015 04:04 AM, Tony Lindgren wrote:
>>>
>>> Actually none of the IO areas above are within the same interconnect target:
>>>
>>> 0x4b30 QSPI0 address space in L3 main interconnect
>>>
Hi,
On 12/03/2015 03:12 PM, Cyrille Pitchen wrote:
> Hi Vignesh,
>
> Le 30/11/2015 06:15, Vignesh R a écrit :
>> Certain spi controllers may provide accelerated interface to read from
>> m25p80 type flash devices. This interface provides better read
>> performance than regular SPI interface.
>>
Hi Tony,
On Tuesday 20 October 2015 08:22 PM, Tony Lindgren wrote:
> * John Ogness [151020 00:33]:
>> On 2015-10-20, Sekhar Nori wrote:
Do you know what really is causing the spurious interrupts in your
case?
>>>
>>> No, not yet.
>>
>>
On 03/12/15 11:52, Brian Norris wrote:
> Hi,
>
> On Thu, Dec 03, 2015 at 11:38:14AM +0530, Roger Quadros wrote:
>> On 03/12/15 10:39, Brian Norris wrote:
>>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
We do a couple of things in this series which result in
cleaner
On Mon, Aug 24, 2015 at 04:21:11PM +0300, Roger Quadros wrote:
> Hi,
>
> This series centralizes OTG/Dual-role functionality in the kernel.
> As of now I've got Dual-role functionality working pretty reliably on
> dra7-evm and am437x-gp-evm.
>
> DWC3 controller and platform related patches will
2015-12-01 7:00 GMT+08:00 Arnd Bergmann :
> Some header files are never included outside of a mach-w90x900
> directory and do not need to be made visible in include/mach,
> so let's just move them all down one level.
>
> Signed-off-by: Arnd Bergmann
Acked-by: Wan
Hi Brian,
On Wed, 2 Dec 2015 20:45:44 -0800
Brian Norris wrote:
> (to be clear, this branch of discussion isn't directly regarding the TI
> changes; we can handle any generic handling afterward, as long as we get
> the DT binding right now)
>
> On Tue, Oct 27, 2015
Peter,
On 03/12/15 13:49, Peter Chen wrote:
> On Mon, Aug 24, 2015 at 04:21:11PM +0300, Roger Quadros wrote:
>> Hi,
>>
>> This series centralizes OTG/Dual-role functionality in the kernel.
>> As of now I've got Dual-role functionality working pretty reliably on
>> dra7-evm and am437x-gp-evm.
>>
On 12/02/2015 04:35 PM, Andy Shevchenko wrote:
>> +const static struct dma_filter_map *dma_filter_match(struct dma_device
>> *device,
>> + const char *name,
>> + struct device *dev)
>> +{
>> + const
Hi,
Changes since RFC v03:
- No longer RFC
- Dropped the arch/arm/mcah-davinci and daVinci MMC and SPI patches so we don't
have inter subsystem issues.
- Comments from Andy to patch no 3 has been addressed with the exception of
moving code over to device_property
- 'struct dma_filter_map'
Channel matching with private_candidate() is used in two paths, the error
checking is slightly different in them and they are duplicating code also.
Move the code under find_candidate() to provide consistent execution and
going to allow us to reuse this mode of channel lookup later.
Add support for providing device to filter_fn mapping so client drivers
can switch to use the dma_request_chan() API.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/edma.c | 6 ++
include/linux/platform_data/edma.h | 7 +++
2 files changed, 13
On Tue, Dec 01, 2015 at 03:55:07PM +0200, Nikita Kiryanov wrote:
> CompuLab SB-SOM baseboard is a carrier board for multiple arm-based SoMs.
> It currently supports (with minor adjustments to assembly) CM-T43, CM-T54,
> and CM-QS600 modules. It is a building block in the SBC-T43 single board
>
* Grygorii Strashko [151130 07:58]:
> ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
> But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
> Timekeeping core misbehaves. For example, execution of command
> "sleep 5" will take 10
* Tony Lindgren [151203 08:34]:
>
> It seems we should apply this as a fix unless somebody has better ideas.
Actually I think the fix for now is "[4.4-rc][PATCH v2] ARM: dts: am4372: fix
clock source for arm twd and global timers" until PM starts working?
Regards,
Tony
--
To
* Grygorii Strashko [151203 08:35]:
> On 12/03/2015 06:00 PM, Tony Lindgren wrote:
> > * Tony Lindgren [151130 08:29]:
> >> We want to be able to probe a few selected device drivers before hwmod
> >> code populates the clocks in omap_hwmod_setup_all().
* Tero Kristo [151130 06:44]:
> + /*
> + * Errata i810 - DPLL controller can get stuck while transitioning
> + * to a power saving state. Software must ensure the DPLL can not
> + * transition to a low power state while changing M/N values.
> + * Easiest
* Grygorii Strashko [151118 07:36]:
> Hi Mark,
>
> On 11/18/2015 04:15 PM, Mark Rutland wrote:
> > On Wed, Nov 18, 2015 at 04:01:55PM +0200, Grygorii Strashko wrote:
> >> Keep ARM TWD and Global timer's nodes disabled by default - if someone
> >> would like to use them
On 12/03/2015 06:00 PM, Tony Lindgren wrote:
> * Tony Lindgren [151130 08:29]:
>> We want to be able to probe a few selected device drivers before hwmod
>> code populates the clocks in omap_hwmod_setup_all(). This allows us to
>> convert most of the clock drivers into regular
On Thu, Dec 3, 2015 at 4:33 PM, Peter Ujfalusi wrote:
> The two API function can cover most, if not all current APIs used to
> request a channel. With minimal effort dmaengine drivers, platforms and
> dmaengine user drivers can be converted to use the two function.
>
>
On Thu, Dec 3, 2015 at 4:33 PM, Peter Ujfalusi wrote:
> Hi,
> As it has been discussed in the following thread:
> http://www.gossamer-threads.com/lists/linux/kernel/2181487#2181487
>
> With this series I have taken a path which would result two new API, which can
> be used
On Thursday 03 December 2015 08:32 PM, Tony Lindgren wrote:
> * Sekhar Nori [151203 03:29]:
>> On Tuesday 20 October 2015 08:22 PM, Tony Lindgren wrote:
>>>
>>> OK thanks for testing. My guess from the above list would be EDMA
>>> or CPSW missing a flush of posted write. Maybe try
* Sekhar Nori [151203 07:25]:
> On Thursday 03 December 2015 08:32 PM, Tony Lindgren wrote:
> >
> > Yes we should naturally fix up the kernel locking.
>
> Alright. Thanks!
>
> >
> > Please also add something like "enable debug for more information"
> > to the warning. And then
On Thursday 03 December 2015 16:33:12 Peter Ujfalusi wrote:
> diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
> index 0675e268d577..46b305ea0d21 100644
> --- a/drivers/dma/edma.c
> +++ b/drivers/dma/edma.c
> @@ -2297,6 +2297,12 @@ static int edma_probe(struct platform_device *pdev)
>
* Dave Gerlach [151202 12:30]:
> On 10/20/2015 11:18 AM, Tony Lindgren wrote:
> >* Dave Gerlach [150922 17:20]:
> >>This series is version 3 of the code to introduce a wkup_m3_ipc driver
> >>to handle communication between the MPU and Cortex M3 present on TI
On Thursday 03 December 2015 16:33:11 Peter Ujfalusi wrote:
> +
> +/**
> + * dma_request_chan - try to allocate an exclusive slave channel
> + * @dev: pointer to client device structure
> + * @name: slave channel name
> + *
> + * Returns pointer to appropriate DMA channel on success or
On 12/03/2015 05:38 PM, Arnd Bergmann wrote:
> On Thursday 03 December 2015 16:33:12 Peter Ujfalusi wrote:
>> diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
>> index 0675e268d577..46b305ea0d21 100644
>> --- a/drivers/dma/edma.c
>> +++ b/drivers/dma/edma.c
>> @@ -2297,6 +2297,12 @@ static int
On Thursday 03 December 2015 17:42:31 Peter Ujfalusi wrote:
> >
> >> + if (chan) {
> >> + /* Valid channel found */
> >> + if (!IS_ERR(chan) || PTR_ERR(chan) == -EPROBE_DEFER)
> >> + return chan;
> >> +
> >> + pr_warn("%s: %s
* Tony Lindgren [151202 17:36]:
> On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
> ADPLLs have several dividers and muxes controlled by a shared
> control register for each PLL.
>
> Note that for the clocks to work as device drivers for booting on
> dm814x, this
* Sekhar Nori [151203 03:29]:
> On Tuesday 20 October 2015 08:22 PM, Tony Lindgren wrote:
> >
> > OK thanks for testing. My guess from the above list would be EDMA
> > or CPSW missing a flush of posted write. Maybe try adding a readback
> > of the related device revision register
* Roger Quadros [151203 01:02]:
> On 03/12/15 11:52, Brian Norris wrote:
> > On Thu, Dec 03, 2015 at 11:38:14AM +0530, Roger Quadros wrote:
> >
> > I think I may have misunderstood the branch proposal. If Tony queues up:
> >
> > l2-mtd.git (or just up to commit a61ae81a1907)
>
On 12/03/2015 05:32 PM, Arnd Bergmann wrote:
> On Thursday 03 December 2015 16:33:11 Peter Ujfalusi wrote:
>> +
>> +/**
>> + * dma_request_chan - try to allocate an exclusive slave channel
>> + * @dev: pointer to client device structure
>> + * @name: slave channel name
>> + *
>> + *
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any
If mask is NULL skip the mask matching against the DMA device capabilities.
Signed-off-by: Peter Ujfalusi
---
drivers/dma/dmaengine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index
* Tony Lindgren [151130 08:29]:
> We want to be able to probe a few selected device drivers before hwmod
> code populates the clocks in omap_hwmod_setup_all(). This allows us to
> convert most of the clock drivers into regular device drivers.
>
> We only need a few minimal
* Rob Herring [151203 06:25]:
> On Tue, Dec 01, 2015 at 03:55:07PM +0200, Nikita Kiryanov wrote:
> > CompuLab SB-SOM baseboard is a carrier board for multiple arm-based SoMs.
> > It currently supports (with minor adjustments to assembly) CM-T43, CM-T54,
> > and CM-QS600 modules.
* Rob Herring [151202 07:24]:
> On Tue, Dec 01, 2015 at 08:03:03PM +0200, Dmitry Lifshitz wrote:
> > Add support for CompuLab CM-SOM-AM57X board.
> >
> > CL-SOM-AM57x is a miniature System-on-Module (SoM) based on
> > TI Sitara AM57x ARM Cortex-A15 System-on-Chip family.
> >
>
On 03/12/15 18:13, Tony Lindgren wrote:
* Linus Walleij [151201 06:07]:
On Fri, Nov 27, 2015 at 6:21 PM, Sudeep Holla wrote:
From: Sudeep Holla
The IRQF_NO_SUSPEND flag is used to identify the interrupts that should
* Grygorii Strashko [151203 10:18]:
> On 12/02/2015 01:38 AM, Tony Lindgren wrote:
>
> > Tony Lindgren (10):
> >ARM: OMAP2+: Fix timer entries for dm814x
> >clk: ti: Add few dm814x clock aliases
> >ARM: OMAP2+: Add DPPLS clock manager for dm814x
> >ARM:
We can boot dra62x j5-eco using the dm814x code as the clocks and
devices are mapped in the device tree. The dra62x is also known
as jacinto 5.
We may want to add separate soc_is macros for dra62x if needed,
but this gets us to the point where we can boot dra62x with just
dts changes.
Let's also
Hi all,
Here are minimal changes to add support for dra62x also known as
jacinto 5 or j5-eco. We can leverage the dm814x support being fixed in
mainline kernel also for dra62x. Compared to dm814x, dra62x has a
bit different clocks and devices.
To boot j5-eco evm, you need the the patches below
The dra762x j5-eco is similar to dm814x with a bit different clocks
and devices.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dra62x-clocks.dtsi | 49
arch/arm/boot/dts/dra62x.dtsi| 23 +
2 files changed, 72
This allows us to boot dra62x j5-eco evm with NFSroot.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/dra62x-j5eco-evm.dts | 28
2 files changed, 30 insertions(+), 1 deletion(-)
create mode
* Grygorii Strashko [151203 10:21]:
> On 12/03/2015 06:37 PM, Tony Lindgren wrote:
> > * Tony Lindgren [151203 08:34]:
> >>
> >> It seems we should apply this as a fix unless somebody has better ideas.
> >
> > Actually I think the fix for now is
* Sudeep Holla [151203 11:00]:
> On 03/12/15 18:13, Tony Lindgren wrote:
> >At least on omaps, this controller is always powered and we never want to
> >suspend it as it handles wake-up events for all the IO pins. And that
> >usecase sounds exactly like what you're
* Grygorii Strashko [151203 10:36]:
>
> I think, this patch should not break our wake-up functionality.
> It will just change the moment when pcs_irq_handler() will be called:
>
> before this change:
> - suspend_enter()
>
> - arch_suspend_enable_irqs();
>
Hi Peter,
* Peter Ujfalusi [151016 00:23]:
I noticed something while changing dm81xx to use the edma_xbar..
> --- a/arch/arm/boot/dts/am33xx.dtsi
> +++ b/arch/arm/boot/dts/am33xx.dtsi
> +
> + edma_xbar: dma-router@44e10f90 {
> + compatible
On 12/03/2015 06:35 PM, Tony Lindgren wrote:
> * Grygorii Strashko [151130 07:58]:
>> ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
>> But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
>> Timekeeping core misbehaves. For
Hello Tony,
On 12/03/2015 03:16 PM, Tony Lindgren wrote:
> * Javier Martinez Canillas [151203 10:03]:
>> Hello,
>>
>> This series converts the IGEPv2 (IGEP0020) and IGEP COM Module (IGEP0030)
>> Device Tree to use the MMC power sequence provider to initialize the SDIO
>>
When the WiFi support was added to the IGEP0030 board, the MMC subsystem
did not provide a mechanism to define power sequence providers. So a DT
hack was used to toggle the WiFi chip reset and power down pins by using
fake fixed regulators whose enable GPIO was the GPIOs connected to these
pins.
* Linus Walleij [151201 06:07]:
> On Fri, Nov 27, 2015 at 6:21 PM, Sudeep Holla wrote:
>
> > From: Sudeep Holla
> >
> > The IRQF_NO_SUSPEND flag is used to identify the interrupts that should
> > be left enabled so as to
On 12/02/2015 01:38 AM, Tony Lindgren wrote:
> Hi all,
>
> Here are some fixes for v4.5 merge window to get dm814x-evm booting.
> While hp t410 boots based on the bootloader clocks, dm814x-evm needs
> more things configured. Especially the clock dts entries were all
> wrong and just happened to
On 12/03/2015 06:37 PM, Tony Lindgren wrote:
> * Tony Lindgren [151203 08:34]:
>>
>> It seems we should apply this as a fix unless somebody has better ideas.
>
> Actually I think the fix for now is "[4.4-rc][PATCH v2] ARM: dts: am4372: fix
> clock source for arm twd and global
On 12/03/2015 08:13 PM, Tony Lindgren wrote:
> * Linus Walleij [151201 06:07]:
>> On Fri, Nov 27, 2015 at 6:21 PM, Sudeep Holla wrote:
>>
>>> From: Sudeep Holla
>>>
>>> The IRQF_NO_SUSPEND flag is used to identify the
* Javier Martinez Canillas [151203 10:03]:
> Hello,
>
> This series converts the IGEPv2 (IGEP0020) and IGEP COM Module (IGEP0030)
> Device Tree to use the MMC power sequence provider to initialize the SDIO
> WiFi chip instead of using fake fixed regulators to just toggle
There's mmc interface on j5-eco evm that's wired to the
sd_1 interface.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dra62x-j5eco-evm.dts | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts
The edma is the same as on am33xx, except it has four tptc
instances. And we need the edma_xbar for at least mmc3, so
let's use the edma_xbar and the new binding as suggested by
Peter Ujfalusi .
Cc: Peter Ujfalusi
Signed-off-by: Tony Lindgren
Let's add mmc entries for dm814x. To do that, we need to rename some
entries to be common for 81xx.
Cc: Paul Walmsley
Signed-off-by: Tony Lindgren
---
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 93 ++
1 file changed, 83
Add mmc device entries for dm814x.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dm814x.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 9d81980e..18a8f0d 100644
There is a mmc slot on the dm8148-evm that's wired to the sd_1
interface.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dm8148-evm.dts | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/dm8148-evm.dts
Let's add the DM814X_IOPAD macro the same way as we have for dm816x and
am33xx as this allows comparing the registers with the documentation easily.
The pinctrl bits are yet again different on dm814x.
Cc: Linus Walleij
Signed-off-by: Tony Lindgren
---
There's a 2GB emmc on hp t410 that's wired to the sd_2 interface.
Note that we also need to configure the evtmux using edma_xbar for
edma channels.
Signed-off-by: Tony Lindgren
---
arch/arm/boot/dts/dm8148-t410.dts | 35 +++
1 file changed, 35
Hi,
These patches add mmc support for dm814x and dra62x. These patches
depend on what's listed at:
http://marc.info/?l=linux-omap=144918431819264=2
Regards,
Tony
Tony Lindgren (7):
ARM: dts: Add pinctrl macros for dm814x
ARM: dts: Update edma bindings on dm814x to use edma_xbar
ARM:
On 4 December 2015 at 00:11, Tony Lindgren wrote:
> We can boot dra62x j5-eco using the dm814x code as the clocks and
> devices are mapped in the device tree. The dra62x is also known
> as jacinto 5.
I'm pretty sure the "eco" in the name isn't optional. As far as I know:
Hello,
This series converts the IGEPv2 (IGEP0020) and IGEP COM Module (IGEP0030)
Device Tree to use the MMC power sequence provider to initialize the SDIO
WiFi chip instead of using fake fixed regulators to just toggle the Reset
and Power pins in the chip.
The patches were tested on an DM3730
When the WiFi support was added to the IGEP0020 board, the MMC subsystem
did not provide a mechanism to define power sequence providers. So a DT
hack was used to toggle the WiFi chip reset and power down pins by using
fake fixed regulators whose enable GPIO was the GPIOs connected to these
pins.
On 12/03/2015 06:41 PM, Tony Lindgren wrote:
> * Grygorii Strashko [151203 08:35]:
>> On 12/03/2015 06:00 PM, Tony Lindgren wrote:
>>> * Tony Lindgren [151130 08:29]:
We want to be able to probe a few selected device drivers before hwmod
code
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