On Tuesday 13 August 2013 03:35 PM, Marc Zyngier wrote:
On 2013-08-13 10:46, Mark Rutland wrote:
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+
On 2013-08-13 10:46, Mark Rutland wrote:
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+
On Tue, Jul 30, 2013 at 12:25:46PM +0100, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
Hi Rajendra,
On 30/07/2013 15:01, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+compatible = ti,omap4-mcspi;
+reg =
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+
On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra
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