Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On Tuesday 13 August 2013 03:35 PM, Marc Zyngier wrote:
On 2013-08-13 10:46, Mark Rutland wrote:
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
+* active low level-sensitive
+*/
+ interrupts = 1 13 0x308,
+1 14 0x308;
+ clock-frequency = 6144000;
+ };
+ };
The cpu nodes should have a reg matching their unit-address, and a
device_type = cpu.
The timer nodes should *not* be under the CPU nodes. They should be
under under the root node. I realise that it makes intuitive sense to
describe per-cpu resources this way, but that's not the way the bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Mark, all valid points. I just updated the patch to include all the missing
interrupts and registers for timer and gic and moved the timer node out as
its supposed to be.
Great!
Do you really need the clock-frequency property? It's far preferrable to
have your bootloader do the right thing and program CNTFRQ with the
correct value.
I kept the clock-frequency property since our bootloader does not handle
this
and I am not sure if its a good idea to have the dependency on bootloader
to do this.
There is precedent for handling it this way, but it would be far nicer
to fix the bootloader to set CNTFRQ. For one thing it's only writeable
from the secure side, so a host os can't fix it up for guests that might
depend on it rather than dt. I realise it's not necessarily as simple as
it sounds to fix that up, however.
Indeed, having the wrong CNTFRQ in the host has the unfortunate effect of
propagating the crap into the guests.
While this can be worked around for Linux guests (you have to hack the DT
passed to the guests, which is very unpleasant at best and varies from one
host to another), there is nothing you can do for non-DT guests.
So please, fix it in your firmware/boot-ROM while it is still time.
Marc, makes sense. Turns out our bootROM (for dra7) does not do this today but
does have an api to do it.
So while we figure how to do this some place else, I will go ahead and drop
this from dt for now.
Thanks for the review.
regards,
Rajendra
Thanks,
M.
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
+* active low level-sensitive
+*/
+ interrupts = 1 13 0x308,
+1 14 0x308;
+ clock-frequency = 6144000;
+ };
+ };
The cpu nodes should have a reg matching their unit-address, and a
device_type = cpu.
The timer nodes should *not* be under the CPU nodes. They should be
under under the root node. I realise that it makes intuitive sense to
describe per-cpu resources this way, but that's not the way the bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Mark, all valid points. I just updated the patch to include all the missing
interrupts and registers for timer and gic and moved the timer node out as
its supposed to be.
Do you really need the clock-frequency property? It's far preferrable to
have your bootloader do the right thing and program CNTFRQ with the
correct value.
I kept the clock-frequency property since our bootloader does not handle this
and I am not sure if its a good idea to have the dependency on bootloader
to do this.
Updated patch:
From 4d2e7cfe8a8a37686a4af26f320ab0d66acb Mon Sep 17 00:00:00 2001
From: R Sricharan r.sricha...@ti.com
Date: Thu, 7 Feb 2013 16:14:00 +0530
Subject: [PATCH] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm
board
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/dra7-evm.dts | 140 ++
arch/arm/boot/dts/dra7.dtsi| 568
3 files changed, 710 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..e2f8566 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-bone.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
- am43x-epos-evm.dtb
+ am43x-epos-evm.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 000..21fe16b
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include dra7.dtsi
+
+/ {
+ model = TI DRA7;
+ compatible = ti,dra7-evm, ti,dra752, ti,dra7;
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x6000; /* 1536 MB */
+ };
+};
+
+dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins =
+ 0x400 0x6 /* i2c1_sda */
+ 0x404 0x6 /* i2c1_scl */
+ ;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins =
+ 0x408 0x6 /* i2c2_sda */
+ 0x40c 0x6 /* i2c2_scl */
+ ;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins =
+ 0x410 0x6 /* i2c3_sda */
+ 0x414 0x6 /* i2c3_scl */
+ ;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins =
+ 0x3a4 0x4 /* spi2_clk */
+ 0x3a8 0x4 /* spi2_d1 */
+ 0x3ac 0x4 /* spi2_d0 */
+ 0x3b0 0xc /* spi2_cs0 */
+ 0x3b4 0xc /* spi2_cs1 */
+ 0x3b8 0xe0006 /* spi2_cs2 */
+ 0x3bc 0xe0006 /* spi2_cs3 */
+ ;
+ };
+
+ mcspi2_pins:
Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
+* active low level-sensitive
+*/
+ interrupts = 1 13 0x308,
+1 14 0x308;
+ clock-frequency = 6144000;
+ };
+ };
The cpu nodes should have a reg matching their unit-address, and a
device_type = cpu.
The timer nodes should *not* be under the CPU nodes. They should be
under under the root node. I realise that it makes intuitive sense to
describe per-cpu resources this way, but that's not the way the bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Mark, all valid points. I just updated the patch to include all the missing
interrupts and registers for timer and gic and moved the timer node out as
its supposed to be.
Great!
Do you really need the clock-frequency property? It's far preferrable to
have your bootloader do the right thing and program CNTFRQ with the
correct value.
I kept the clock-frequency property since our bootloader does not handle this
and I am not sure if its a good idea to have the dependency on bootloader
to do this.
There is precedent for handling it this way, but it would be far nicer
to fix the bootloader to set CNTFRQ. For one thing it's only writeable
from the secure side, so a host os can't fix it up for guests that might
depend on it rather than dt. I realise it's not necessarily as simple as
it sounds to fix that up, however.
[...]
+ timer {
+ compatible = arm,armv7-timer;
+ /* PPI secure/nonsecure IRQ */
The comment's now stale, and I don't think it's necessary - the binding
defines the order these are in.
+ interrupts = GIC_PPI 13 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 14 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 11 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_LOW),
+GIC_PPI 10 (GIC_CPU_MASK_RAW(3) |
IRQ_TYPE_LEVEL_LOW);
+ clock-frequency = 6144000;
+ };
Thanks,
Mark.
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On 2013-08-13 10:46, Mark Rutland wrote:
[Adding Marc to Cc]
On Tue, Aug 13, 2013 at 08:24:31AM +0100, Rajendra Nayak wrote:
[]..
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
+* active low level-sensitive
+*/
+ interrupts = 1 13 0x308,
+1 14 0x308;
+ clock-frequency = 6144000;
+ };
+ };
The cpu nodes should have a reg matching their unit-address, and a
device_type = cpu.
The timer nodes should *not* be under the CPU nodes. They should
be
under under the root node. I realise that it makes intuitive sense
to
describe per-cpu resources this way, but that's not the way the
bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Mark, all valid points. I just updated the patch to include all the
missing
interrupts and registers for timer and gic and moved the timer node
out as
its supposed to be.
Great!
Do you really need the clock-frequency property? It's far
preferrable to
have your bootloader do the right thing and program CNTFRQ with
the
correct value.
I kept the clock-frequency property since our bootloader does not
handle this
and I am not sure if its a good idea to have the dependency on
bootloader
to do this.
There is precedent for handling it this way, but it would be far
nicer
to fix the bootloader to set CNTFRQ. For one thing it's only
writeable
from the secure side, so a host os can't fix it up for guests that
might
depend on it rather than dt. I realise it's not necessarily as simple
as
it sounds to fix that up, however.
Indeed, having the wrong CNTFRQ in the host has the unfortunate effect
of propagating the crap into the guests.
While this can be worked around for Linux guests (you have to hack the
DT passed to the guests, which is very unpleasant at best and varies
from one host to another), there is nothing you can do for non-DT
guests.
So please, fix it in your firmware/boot-ROM while it is still time.
Thanks,
M.
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On Tue, Jul 30, 2013 at 12:25:46PM +0100, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/dra7-evm.dts | 163 ++
arch/arm/boot/dts/dra7.dtsi| 488
3 files changed, 653 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
[...]
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
new file mode 100644
index 000..8a0c08e
--- /dev/null
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -0,0 +1,488 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on omap4.dtsi
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+ compatible = ti,dra7xx;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = uart1;
+ serial1 = uart2;
+ serial2 = uart3;
+ serial3 = uart4;
+ serial4 = uart5;
+ serial5 = uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a15;
+ timer {
+ compatible = arm,armv7-timer;
+ /*
+* PPI secure/nonsecure IRQ,
+* active low level-sensitive
+*/
+ interrupts = 1 13 0x308,
+1 14 0x308;
+ clock-frequency = 6144000;
+ };
+ };
The cpu nodes should have a reg matching their unit-address, and a
device_type = cpu.
The timer nodes should *not* be under the CPU nodes. They should be
under under the root node. I realise that it makes intuitive sense to
describe per-cpu resources this way, but that's not the way the bindings
are intended to be used (does thei DT even work?).
No virtual/hypervisor interrupts?
Do you really need the clock-frequency property? It's far preferrable to
have your bootloader do the right thing and program CNTFRQ with the
correct value.
+
+ gic: interrupt-controller@48211000 {
+ compatible = arm,cortex-a15-gic;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x48211000 0x1000,
+ 0x48212000 0x1000;
Similarly, no GICH/GICV registers?
Thanks,
Mark.
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
Hi Rajendra,
On 30/07/2013 15:01, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+compatible = ti,omap4-mcspi;
+reg = 0x480ba000 0x200;
+interrupts = 0 48 0x4;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = mcspi4;
+ti,spi-num-cs = 1;
+dmas = sdma 70, sdma 71;
+dma-names = tx0, rx0;
+};
+};
+};
ref: [1], we discussed that we should now be able to introduce all instances of
h/w blocks into the dra7.dts. Further, considering [2]
hmm, thats a long discussion on crossbar driver that [1] points to. Do you want
to summarize what you mean by 'introduce all instances of h/w blocks'
I recommend reading the last few emails on the thread about how we could do
this with pinctrl. unfortunately, this patch is not informative enough to
indicate that not all instances of the potential IP blocks are listed here.
would you not want to follow status = disabled for all modules by default and
enable required modules in board file, so that we dont have to respin this yet again?
Well, I was just following the convention of whats already followed on existing
OMAPs. See [3] for some views on these.
DRA7 case, I would not think it makes sense due to the number of product
variants being done, not all will use the same set. Further, rationale for DRA7
and my suggestion for Grant's option (1) is mainly because the product variants
will require more dtsis rather than board files using the product variants use
just the necessary modules from a common dtsi. Makes support of variants like
OMAP57xx etc trivial and constrainted to board file usage, rather than spinning
off new dtsis.
Makes sense with the different product variants for DRA7, AM335x already does
it this way, but the rest of OMAP3/4/5 are doing it the other way.
I think its just too confusing to follow different conventions for different
SoCs. We should stick to just one, either this way or that.
I think bucketing DRA7(with multitude of SoC variants) with OMAP family(usually
with 5 variants) will be a wrong approach. we should choose the approach
appropriate for the SoC. hence, OMAPx having all default enabled makes sense (as
the delta is usually trivial), but on DRA7, the variants are larger :(
just my 2 cents.
I can respin with the changes, but before I do so, Benoit do you agree with the
rationale for these and fine with the approach?
Sorry for the very late reply. I've just seen it because Mark's answer
put in again in my gmail box.
I'm not sure to understand what Nishanth and you are arguing for :-)
If this is about the default status state, I think that this flag is
anyway confusing because you cannot know if we are considering an IP
that does not exist at all in a variant or an IP that is not used on a
certain board...
This potential issue we can have with the second case is that the IP
might be enabled by the boot loader and never disabled because
status=disabled prevent DT to create the device, and thus prevent the
driver to properly idle the device.
That's why I did not like the usage of status=disabled by default,
because the way DT core handle that might not be appropriate for an IP
that is there but not use.
For a variant that does not contain physically the IP, that flag can be
relevant.
Regarding which default status is the best, I guess as soon as it is
consistant across a chip family, both are fine to me.
Not necessarily related to your discussion, but I still think that DT is
missing a flag to make the difference between the two cases.
Regards,
Benoit
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/dra7-evm.dts | 163 ++
arch/arm/boot/dts/dra7.dtsi| 488
3 files changed, 653 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..e2f8566 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-bone.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
- am43x-epos-evm.dtb
+ am43x-epos-evm.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 000..7b0b563
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ dra7.dtsi
+
+/ {
+ model = TI DRA7;
+ compatible = ti,dra7-evm, ti,dra7;
+
+ memory {
+ device_type = memory;
+ reg = 0x8000 0x6000; /* 1536 MB */
+ };
+};
+
+dra7_pmx_core {
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins =
+ 0x400 0x6 /* i2c1_sda */
+ 0x404 0x6 /* i2c1_scl */
+ ;
+ };
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins =
+ 0x408 0x6 /* i2c2_sda */
+ 0x40c 0x6 /* i2c2_scl */
+ ;
+ };
+
+ i2c3_pins: pinmux_i2c3_pins {
+ pinctrl-single,pins =
+ 0x410 0x6 /* i2c3_sda */
+ 0x414 0x6 /* i2c3_scl */
+ ;
+ };
+
+ mcspi1_pins: pinmux_mcspi1_pins {
+ pinctrl-single,pins =
+ 0x3a4 0x4 /* spi2_clk */
+ 0x3a8 0x4 /* spi2_d1 */
+ 0x3ac 0x4 /* spi2_d0 */
+ 0x3b0 0xc /* spi2_cs0 */
+ 0x3b4 0xc /* spi2_cs1 */
+ 0x3b8 0xe0006 /* spi2_cs2 */
+ 0x3bc 0xe0006 /* spi2_cs3 */
+ ;
+ };
+
+ mcspi2_pins: pinmux_mcspi2_pins {
+ pinctrl-single,pins =
+ 0x3c0 0x4 /* spi2_sclk */
+ 0x3c4 0xc /* spi2_d1 */
+ 0x3c8 0xc /* spi2_d1 */
+ 0x3cc 0xe /* spi2_cs0 */
+ ;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins =
+ 0x3e0 0xe /* uart1_rxd */
+ 0x3e4 0xe /* uart1_txd */
+ 0x3e8 0x60003 /* uart1_ctsn */
+ 0x3ec 0x60003 /* uart1_rtsn */
+ ;
+ };
+
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins =
+ 0x3f0 0x6 /* uart2_rxd */
+ 0x3f4 0x6 /* uart2_txd */
+ 0x3f8 0x6 /* uart2_ctsn */
+ 0x3fc 0x6 /* uart2_rtsn */
+ ;
+ };
+
+ uart3_pins: pinmux_uart3_pins {
+ pinctrl-single,pins =
+ 0x248 0xc /* uart3_rxd */
+ 0x24c 0xc /* uart3_txd */
+ ;
+ };
+};
+
+i2c1 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins;
+
+ clock-frequency = 40;
+};
+
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins;
+
+ clock-frequency = 40;
+};
+
+i2c3 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c3_pins;
+
+ clock-frequency = 340;
+};
+
+i2c4 {
+ status = disabled;
+};
+
+i2c5 {
+ status = disabled;
+};
+
+mcspi1 {
+ pinctrl-names = default;
+ pinctrl-0
Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Rajendra Nayak rna...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/Makefile |3 +-
arch/arm/boot/dts/dra7-evm.dts | 163 ++
arch/arm/boot/dts/dra7.dtsi| 488
3 files changed, 653 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/dra7-evm.dts
create mode 100644 arch/arm/boot/dts/dra7.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..e2f8566 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -173,7 +173,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
am335x-bone.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
-am43x-epos-evm.dtb
+am43x-epos-evm.dtb \
+dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 000..7b0b563
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ dra7.dtsi
+
+/ {
+model = TI DRA7;
+compatible = ti,dra7-evm, ti,dra7;
+
+memory {
+device_type = memory;
+reg = 0x8000 0x6000; /* 1536 MB */
+};
+};
+
+dra7_pmx_core {
+i2c1_pins: pinmux_i2c1_pins {
+pinctrl-single,pins =
+0x400 0x6/* i2c1_sda */
+0x404 0x6/* i2c1_scl */
+;
+};
+
+i2c2_pins: pinmux_i2c2_pins {
+pinctrl-single,pins =
+0x408 0x6/* i2c2_sda */
+0x40c 0x6/* i2c2_scl */
+;
+};
+
+i2c3_pins: pinmux_i2c3_pins {
+pinctrl-single,pins =
+0x410 0x6/* i2c3_sda */
+0x414 0x6/* i2c3_scl */
+;
+};
+
+mcspi1_pins: pinmux_mcspi1_pins {
+pinctrl-single,pins =
+0x3a4 0x4/* spi2_clk */
+0x3a8 0x4/* spi2_d1 */
+0x3ac 0x4/* spi2_d0 */
+0x3b0 0xc/* spi2_cs0 */
+0x3b4 0xc/* spi2_cs1 */
+0x3b8 0xe0006/* spi2_cs2 */
+0x3bc 0xe0006/* spi2_cs3 */
+;
+};
+
+mcspi2_pins: pinmux_mcspi2_pins {
+pinctrl-single,pins =
+0x3c0 0x4/* spi2_sclk */
+0x3c4 0xc/* spi2_d1 */
+0x3c8 0xc/* spi2_d1 */
+0x3cc 0xe/* spi2_cs0 */
+;
+};
+
+uart1_pins: pinmux_uart1_pins {
+pinctrl-single,pins =
+0x3e0 0xe/* uart1_rxd */
+0x3e4 0xe/* uart1_txd */
+0x3e8 0x60003/* uart1_ctsn */
+0x3ec 0x60003/* uart1_rtsn */
+;
+};
+
+uart2_pins: pinmux_uart2_pins {
+pinctrl-single,pins =
+0x3f0 0x6 /* uart2_rxd */
+0x3f4 0x6 /* uart2_txd */
+0x3f8 0x6 /* uart2_ctsn */
+0x3fc 0x6 /* uart2_rtsn */
+;
+};
+
+uart3_pins: pinmux_uart3_pins {
+pinctrl-single,pins =
+0x248 0xc /* uart3_rxd */
+0x24c 0xc /* uart3_txd */
+;
+};
+};
+
+i2c1 {
+pinctrl-names = default;
+pinctrl-0 = i2c1_pins;
+
+clock-frequency = 40;
+};
+
+i2c2 {
+pinctrl-names = default;
+pinctrl-0 = i2c2_pins;
+
+clock-frequency = 40;
+};
+
+i2c3 {
+pinctrl-names = default;
+pinctrl-0 = i2c3_pins;
+
+clock-frequency = 340;
+};
+
+i2c4 {
+status = disabled;
+};
+
+i2c5 {
+status = disabled;
+};
+
+mcspi1 {
+pinctrl-names = default;
+pinctrl-0 = mcspi1_pins;
+};
+
+mcspi2 {
+pinctrl-names = default;
+pinctrl-0 = mcspi2_pins;
+};
+
+mcspi3 {
+status = disabled;
+};
+
+mcspi4 {
+status = disabled;
+};
+
+uart1 {
+pinctrl-names = default;
+pinctrl-0 = uart1_pins;
+};
+
+uart2 {
+
Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+compatible = ti,omap4-mcspi;
+reg = 0x480ba000 0x200;
+interrupts = 0 48 0x4;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = mcspi4;
+ti,spi-num-cs = 1;
+dmas = sdma 70, sdma 71;
+dma-names = tx0, rx0;
+};
+};
+};
ref: [1], we discussed that we should now be able to introduce all instances of
h/w blocks into the dra7.dts. Further, considering [2]
hmm, thats a long discussion on crossbar driver that [1] points to. Do you want
to summarize what you mean by 'introduce all instances of h/w blocks'
I recommend reading the last few emails on the thread about how we could
do this with pinctrl. unfortunately, this patch is not informative
enough to indicate that not all instances of the potential IP blocks are
listed here.
would you not want to follow status = disabled for all modules by default and
enable required modules in board file, so that we dont have to respin this yet again?
Well, I was just following the convention of whats already followed on existing
OMAPs. See [3] for some views on these.
DRA7 case, I would not think it makes sense due to the number of product
variants being done, not all will use the same set. Further, rationale
for DRA7 and my suggestion for Grant's option (1) is mainly because the
product variants will require more dtsis rather than board files using
the product variants use just the necessary modules from a common dtsi.
Makes support of variants like OMAP57xx etc trivial and constrainted to
board file usage, rather than spinning off new dtsis.
[1] http://marc.info/?t=13741659941r=1w=2
[2] http://marc.info/?l=linux-omapm=137510358229479w=2
[3]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
--
Regards,
Nishanth Menon
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+compatible = ti,omap4-mcspi;
+reg = 0x480ba000 0x200;
+interrupts = 0 48 0x4;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = mcspi4;
+ti,spi-num-cs = 1;
+dmas = sdma 70, sdma 71;
+dma-names = tx0, rx0;
+};
+};
+};
ref: [1], we discussed that we should now be able to introduce all
instances of h/w blocks into the dra7.dts. Further, considering [2]
hmm, thats a long discussion on crossbar driver that [1] points to. Do you
want to summarize what you mean by 'introduce all instances of h/w blocks'
I recommend reading the last few emails on the thread about how we could do
this with pinctrl. unfortunately, this patch is not informative enough to
indicate that not all instances of the potential IP blocks are listed here.
would you not want to follow status = disabled for all modules by default
and enable required modules in board file, so that we dont have to respin
this yet again?
Well, I was just following the convention of whats already followed on
existing OMAPs. See [3] for some views on these.
DRA7 case, I would not think it makes sense due to the number of product
variants being done, not all will use the same set. Further, rationale for
DRA7 and my suggestion for Grant's option (1) is mainly because the product
variants will require more dtsis rather than board files using the product
variants use just the necessary modules from a common dtsi. Makes support of
variants like OMAP57xx etc trivial and constrainted to board file usage,
rather than spinning off new dtsis.
Makes sense with the different product variants for DRA7, AM335x already does
it this way, but the rest of OMAP3/4/5 are doing it the other way.
I think its just too confusing to follow different conventions for different
SoCs. We should stick to just one, either this way or that.
[1] http://marc.info/?t=13741659941r=1w=2
[2] http://marc.info/?l=linux-omapm=137510358229479w=2
[3]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
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Re: [PATCH v2 8/8] ARM: DRA7: dts: Add the dts files for dra7 SoC and dra7-evm board
On Tuesday 30 July 2013 06:29 PM, Nishanth Menon wrote:
On 07/30/2013 07:56 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:16 PM, Nishanth Menon wrote:
On 07/30/2013 07:41 AM, Rajendra Nayak wrote:
On Tuesday 30 July 2013 06:00 PM, Nishanth Menon wrote:
On 07/30/2013 06:25 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
[...]
+mcspi4: spi@480ba000 {
+compatible = ti,omap4-mcspi;
+reg = 0x480ba000 0x200;
+interrupts = 0 48 0x4;
+#address-cells = 1;
+#size-cells = 0;
+ti,hwmods = mcspi4;
+ti,spi-num-cs = 1;
+dmas = sdma 70, sdma 71;
+dma-names = tx0, rx0;
+};
+};
+};
ref: [1], we discussed that we should now be able to introduce all
instances of h/w blocks into the dra7.dts. Further, considering [2]
hmm, thats a long discussion on crossbar driver that [1] points to. Do you
want to summarize what you mean by 'introduce all instances of h/w blocks'
I recommend reading the last few emails on the thread about how we could do
this with pinctrl. unfortunately, this patch is not informative enough to
indicate that not all instances of the potential IP blocks are listed here.
would you not want to follow status = disabled for all modules by
default and enable required modules in board file, so that we dont have
to respin this yet again?
Well, I was just following the convention of whats already followed on
existing OMAPs. See [3] for some views on these.
DRA7 case, I would not think it makes sense due to the number of product
variants being done, not all will use the same set. Further, rationale for
DRA7 and my suggestion for Grant's option (1) is mainly because the product
variants will require more dtsis rather than board files using the product
variants use just the necessary modules from a common dtsi. Makes support
of variants like OMAP57xx etc trivial and constrainted to board file usage,
rather than spinning off new dtsis.
Makes sense with the different product variants for DRA7, AM335x already
does it this way, but the rest of OMAP3/4/5 are doing it the other way.
I think its just too confusing to follow different conventions for different
SoCs. We should stick to just one, either this way or that.
I think bucketing DRA7(with multitude of SoC variants) with OMAP
family(usually with 5 variants) will be a wrong approach. we should choose
the approach appropriate for the SoC. hence, OMAPx having all default enabled
makes sense (as the delta is usually trivial), but on DRA7, the variants are
larger :(
just my 2 cents.
I can respin with the changes, but before I do so, Benoit do you agree with the
rationale for these and fine with the approach?
[1] http://marc.info/?t=13741659941r=1w=2
[2] http://marc.info/?l=linux-omapm=137510358229479w=2
[3]
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-February/086297.html
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