On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to support both power of two
and power of four page sizes. Also
On Thu, Feb 12, 2009 at 01:21:24PM -0600, Kumar Gala wrote:
On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to
On Thu, 2009-02-12 at 13:21 -0600, Kumar Gala wrote:
On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to
On Feb 12, 2009, at 2:34 PM, Josh Boyer wrote:
On Thu, Feb 12, 2009 at 01:21:24PM -0600, Kumar Gala wrote:
On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with
I can call it mmu-book3e.h if you think that might enough different to
convey the ISA 2.06 fact that the FSL style MMU is now part of the 3e
architecture.
That's better. book3e is what I've been using internally...
Cheers,
Ben.
___
On Thu, Feb 12, 2009 at 03:58:15PM -0600, Kumar Gala wrote:
On Feb 12, 2009, at 2:34 PM, Josh Boyer wrote:
On Thu, Feb 12, 2009 at 01:21:24PM -0600, Kumar Gala wrote:
On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
The Power ISA 2.06 added power of two page sizes to the embedded MMU
