On Aug 21, 2009, at 1:39 AM, Heiko Schocher wrote:
Hello,
I actually porting a mpc8321 based port, and because there is no FPU
on this CPU, I activated MATH_EMUL, as all other mpc832x ports did.
Is there something like a counter, which counts how many times this
Exception occurs?
Geert
On Aug 19, 2009, at 7:43 PM, Benjamin Herrenschmidt wrote:
On Wed, 2009-08-19 at 16:37 -0500, Kumar Gala wrote:
On Aug 19, 2009, at 2:25 AM, Benjamin Herrenschmidt wrote:
The whole thing only ever gets called if we had tlbsrx. so is there
any utility in making a part of conditional
that if an implementation has
hardware page table at this time it also implements in TLB reservations.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Add a MMU feature around virt_page_table_tlb_miss_done based on
MMU_FTR_USE_TLBRSRV
arch/powerpc/include/asm/mmu.h |9 +
arch
the further node
isn't a partition not all needed properties are there.
cheers
ben
* Kumar Gala | 2009-08-12 09:46:10 [-0500]:
Ben,
The following commit breaks the previous definition of flash
partitions according to
Documentation/powerpc/dts-bindings/mtd-physmap.txt. Using the
'name' field
On Aug 25, 2009, at 8:52 AM, Benjamin Krill wrote:
The previous implementation breaks the dts binding mtd-
physmap.txt. This
implementation fixes the issue by checking the availability of the reg
property instead of the name property.
Signed-off-by: Benjamin Krill b...@codiert.org
---
On Aug 18, 2009, at 6:28 PM, Anton Vorontsov wrote:
mpc8272_ads.c is using BCSR bits definitions from pq2ads.h, but
according to User's Guide the bits are wrong for MPC8272ADS boards
(I guess definitions from pq2ads should only be used for PQ2FADS
boards).
So, let's introduce our own
On Aug 18, 2009, at 6:28 PM, Anton Vorontsov wrote:
- Add usb node;
- Configure pins and clocks;
- Enable USB function in BCSR.
The support was successfully tested using serial and ethernet gadget
drivers.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
On Aug 18, 2009, at 6:28 PM, Anton Vorontsov wrote:
- Add gpio-controller node for BCSR17, it is used to control USB
speed and VBUS;
- Add timer node for QE GTM, needed for USB host;
- Add usb node itself;
- Add some probing code for BCSR GPIOs.
NOTE: QE USB doesn't work on prototype boards,
On Aug 18, 2009, at 4:20 PM, Michael Barkowski wrote:
This avoids having a short glitch if the desired initial value is not
the same as what was previously in the data register.
Signed-off-by: Michael Barkowski michaelbarkow...@ruggedcom.com
---
Anton Vorontsov wrote:
There is a recursive
setups, it's recommended
to upgrade U-Boot, since it will fixup clock-frequency automatically.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
On Tue, Aug 11, 2009 at 08:48:32AM -0500, Kumar Gala wrote:
On Aug 7, 2009, at 2:58 PM, Anton Vorontsov wrote:
This patch simply adds sdhci node
The MMUCSR is now defined as part of the Book-3E architecture so we
can move it into mmu-book3e.h and add some of the additional bits
defined by the architecture specs.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/mmu-book3e.h | 12
arch/powerpc
powerpc/82xx: Add CPM USB Gadget support for MPC8272ADS boards
powerpc/85xx: Add QE USB support for MPC8569E-MDS boards
Heiko Schocher (1):
powerpc/82xx: mgcoge - updated defconfig
Kumar Gala (1):
powerpc/booke: Move MMUCSR definition into mmu-book3e.h
Liang Li (4
. Since all current callers seem to pass it
one.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/machdep.h|6 +-
arch/powerpc/include/asm/pci-bridge.h | 35 +++-
arch/powerpc/kernel/pci-common.c | 70
arch
On Aug 25, 2009, at 9:20 PM, Kumar Gala wrote:
Some of the PCI features we have in ppc32 we will need on ppc64
platforms in the future. These include support for:
* ppc_md.pci_exclude_device
* indirect config cycles
* early config cycles
We also simplified the logic in fake_pci_bus
/kernel/pci_64.c | 289
---
arch/powerpc/kernel/pci_of_scan.c | 358
+
6 files changed, 364 insertions(+), 296 deletions(-)
create mode 100644 arch/powerpc/kernel/pci_of_scan.c
Acked-by: Kumar Gala ga...@kernel.crashing.org
On Aug 27, 2009, at 12:30 PM, Anton Vorontsov wrote:
MPC8569 CPUs have four QE RISCs, so we need to increase MAX_QE_RISC
constant, otherwise qe_upload_firmware() fails at sanity checking.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
arch/powerpc/sysdev/qe_lib/qe.c |2 +-
1
On Aug 25, 2009, at 8:54 AM, Poonam Aggrwal wrote:
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences
from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
-
On Aug 27, 2009, at 12:30 PM, Anton Vorontsov wrote:
For MPC8569 CPUs we'll need to reset QE after each suspend, so make
qe_reset() code path suitable for repeated invocation, that is:
- Don't initialize rheap structures if already initialized;
- Don't allocate muram for SDMA if already
On Aug 27, 2009, at 12:30 PM, Anton Vorontsov wrote:
This is needed to avoid #ifdefs in MPC85xx suspend/resume code.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
arch/powerpc/include/asm/qe.h |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
applied to next
- k
On Aug 27, 2009, at 12:30 PM, Anton Vorontsov wrote:
This patch adds suspend/resume support for MPC8540-compatible and
MPC8569 CPUs.
MPC8540-compatible PMCs are trivial: we just write SLP bit into PM
control and status register.
MPC8569 is a bit trickier, QE turns off during suspend and so
On Aug 18, 2009, at 5:04 PM, Anton Vorontsov wrote:
When cpm2.h included into spi_mpc8xxx driver, the SPI defines
in the header conflict with defines in the driver.
We don't need them in the header file, so remove them. Plus
remove struct spi, we'll use a better version in the driver.
On Aug 18, 2009, at 5:04 PM, Anton Vorontsov wrote:
struct mcc defined in both immap_qe.h and immap_cpm2.h, so they will
conflic when included in a single file. The mcc struct is easy to deal
with, since it isn't used in any driver (yet), so let's just rename QE
version to qe_mcc.
The
On Aug 18, 2009, at 5:04 PM, Anton Vorontsov wrote:
The bits are generic to CPM devices, so let's move them to the
common header file, so drivers won't need to privately reintroduce
another bunch of the same bits (as we can't include cpm2.h header
together with cpm1.h).
Signed-off-by: Anton
On Aug 18, 2009, at 5:04 PM, Anton Vorontsov wrote:
This is needed to avoid ugly #ifdefs in drivers. Also update
fsl_qe_udc
driver so that now it doesn't define its own versions that cause build
breakage when the generic stubs are used.
Signed-off-by: Anton Vorontsov
avoront...@ru.mvista.com
---
drivers/spi/spi_mpc8xxx.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
Acked-by: Kumar Gala ga...@kernel.crashing.org
- k
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_PMD_PRESENT, _PMD_PRESENT_MASK, and _PMD_BAD since the
32-bit ppc arch code expects them.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/pgtable-ppc32.h |2 +
arch/powerpc/include/asm/pte-book3e.h|3 ++
arch/powerpc/include/asm/pte-fsl-booke.h |7
On Sep 2, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-01 at 20:48 -0500, Kumar Gala wrote:
Switch to using the Power ISA defined PTE format when we have a 64-
bit
PTE. This makes the code handling between fsl-booke and book3e-64
similiar for TLB faults.
Additionally
on BookE secondary CPUs
Make it so that smp_ops probe() and setup_cpu() can be set to NULL.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/kernel/smp.c | 10 +++---
arch/powerpc/platforms/85xx/smp.c | 13 +++--
2 files changed, 10 insertions(+), 13
On Sep 8, 2009, at 4:31 PM, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-08 at 14:21 -0500, Kumar Gala wrote:
struct smp_ops_t smp_85xx_ops = {
+ .message_pass = NULL,
+ .probe = NULL,
.kick_cpu = smp_85xx_kick_cpu,
+ .setup_cpu = NULL,
};
Why explicitely
on BookE secondary CPUs
Make it so that smp_ops probe() and setup_cpu() can be set to NULL.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Removed explicit setting of NULL in structure
arch/powerpc/kernel/smp.c | 10 +++---
arch/powerpc/platforms/85xx/smp.c | 10
On Sep 9, 2009, at 1:22 PM, Scott Wood wrote:
On Fri, Sep 04, 2009 at 12:31:25PM +0200, Roland Lezuo wrote:
The following patch is needed to correctly assign the IRQs for the
gianfar driver on the MPC8313ERDB-revc boards. ERR and TX are swapped
as well as the interrupt lines for the two
Do you have floating point emulation turned on in the kernel?
- k
On Sep 10, 2009, at 10:01 AM, Isaac Gomez Morales wrote:
Hello,
I'm trying to get a Linux distro such as Debian in the following
system
System:
mpc8572ds HW
u-boot programmed on flash memory
vanillia linux installed on
797a747a82e23530ee45d2927bf84f3571c1acb2
Author: Kumar Gala ga...@kernel.crashing.org
Date: Tue Aug 18 15:21:40 2009 +
powerpc/mm: Fix assert_pte_locked to work properly on uniprocessor
Since the pte_lockptr is a spinlock it gets optimized away on
uniprocessor builds so using spin_is_locked is not correct. We
On Sep 15, 2009, at 1:37 PM, Christopher Best wrote:
On the MPC8572, eTSEC1 and eTSEC2 can be configured to jointly
operate in 16-bit encoded FIFO mode. Is there currently a Linux
driver for interfacing with this FIFO mode?
Not that I'm aware of. You should be able to modify
On Sep 11, 2009, at 6:47 AM, Aggrwal Poonam-B10812 wrote:
Ok, I wrongly understood protected interrupts as reserved for
one core. However, I still dislike two devices having the same name.
Otherwise it may work if every interrupt is delivered to both
cores although statistically only one
On Sep 16, 2009, at 11:17 PM, Felix Radensky wrote:
Hi,
On my custom MPC8536 based board running 2.6.31 kernel
FPGA is connected via x2 PCI-E lane. FPGA is identified
during PCI scan and is visible via lspci.
:01:00.0 Class ff00: Altera Corporation Unknown device 0004 (rev
01)
On Sep 24, 2009, at 12:05 AM, Benjamin Herrenschmidt wrote:
Here's what I'll ask Linus to pull tomorrow, currently sitting in
powerpc merge branch:
I need to send you a pull request. However being at plumbers finding
time to get the tree is proving difficult :)
- k
On Sep 21, 2009, at 7:30 AM, Paul Gortmaker wrote:
The PCI-e addressing was originally patterned of the MPC8548CDS
which has PCI1, PCI2, and PCI-e. Since this board only has
PCI1 and PCI-e, it makes more sense to be similar to the MPC8568MDS
board. This does that by cutting the PCI/PCI-e I/O
On Aug 5, 2009, at 11:25 PM, Felix Radensky wrote:
Hi, Poonam
Poonam Aggrwal wrote:
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
On Sep 19, 2009, at 10:13 AM, Poonam Aggrwal wrote:
This patch creates the dts files for each core and splits the
devices between
the two cores for P2020RDB.
core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto,
global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.
MPIC is
On Sep 25, 2009, at 4:07 AM, Fortini Matteo wrote:
I was trying to insert an optimized strlen() function using the
following code taken from the ibm site on an MPC5121, but it crashes
the kernel.
Is it because it's an unsupported op, or because I'm missing some
needed steps?
Thank you,
On Oct 2, 2009, at 9:46 AM, Timur Tabi wrote:
Michael Barkowski wrote:
Just wondering - is there a case where using volatile for UCC
parameter RAM for example will not work, or is the use of I/O
accessors everywhere an attempt to be portable to other
architectures?
'volatile' just
On Oct 5, 2009, at 2:15 AM, Mahajan Vivek-B08308 wrote:
From: Gala Kumar-B11780
Sent: Friday, September 25, 2009 12:08 AM
+ mbar(1);
why isn't eieio() sufficient here?
When I initially added / tested cache SRAM for P2020RDB, its RM talked
about using mbar() though mbar(1) is
On Oct 9, 2009, at 12:49 PM, Ron Mercer wrote:
I recently grabbed the latest net-2.6 kernel for a powerpc test box
and
got this compile error.
CC arch/powerpc/kernel/cputable.o
CC arch/powerpc/kernel/ptrace.o
CC arch/powerpc/kernel/syscalls.o
CC
On Oct 16, 2009, at 11:01 AM, Scott Wood wrote:
I have the LITE5200B, MPC8313-ERDB, MPC8572DS, and the P2020DS in
house, and it is really the same, sad story with each of
them. Wouldn't it be grand if the development boards would boot out
of the box when compiling the most recent kernel with
' was here
cc1: warnings being treated as errors
arch/powerpc/kernel/pci_64.c: In function 'pcibios_unmap_io_space':
arch/powerpc/kernel/pci_64.c:100: error: unused variable 'res'
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/kernel/pci_64.c |2 ++
arch/powerpc/kernel
This defconfig's purpose at this time is to help catch compile errors
between Book-3S and Book-3E support in ppc64. It is based on the
ppc64_defconfig with some things disabled that we dont support on
Book-3E right now (hugetlbfs, slices, etc.)
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
This is a series of simple Kconfig cleans related to powerpc intended
for v2.6.33. I'm assuming having them go via the powerpc tree is
probably the easiest.
- k
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Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
fs/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/fs/Kconfig b/fs/Kconfig
index d4bf8ca..f93d0ed 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -135,7 +135,7 @@ config TMPFS_POSIX_ACL
config HUGETLBFS
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
mm/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/mm/Kconfig b/mm/Kconfig
index 57963c6..7ca3777 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -129,7 +129,7 @@ config MEMORY_HOTPLUG
bool Allow
We dont need to depend on PPC64 explicitly as all powerpc platforms
(32-bit and 64-bit) define PPC now.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
init/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/init/Kconfig b/init/Kconfig
index 09c5c64
We can replace PPC32 || PPC64 as a dependancy with just PPC as all
powerpc platforms (32-bit and 64-bit) define PPC now.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
sound/ppc/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/sound/ppc/Kconfig b/sound
We don't need an explicit PPC64 in the DEBUG_PREEMPT dependancies as all
PPC platforms now support TRACE_IRQFLAGS_SUPPORT.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
lib/Kconfig.debug |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/lib/Kconfig.debug b/lib
On Oct 16, 2009, at 12:05 PM, Kumar Gala wrote:
This defconfig's purpose at this time is to help catch compile errors
between Book-3S and Book-3E support in ppc64. It is based on the
ppc64_defconfig with some things disabled that we dont support on
Book-3E right now (hugetlbfs, slices, etc
On Oct 15, 2009, at 5:13 AM, willy jacobs wrote:
On our MPC8548 (latest die revision) based boards with 2 GByte DDR2
RAM we see an stable kernel when
CONFIG_HIGHMEM is not set
In this case only the first 768 MB will be used (as reported by /
proc/cpuinfo).
Tested with/without the
On Oct 20, 2009, at 5:21 PM, Németh Márton wrote:
Hi Grant,
Hello List,
is there anybody who was successfully run Linux kernel on Freescale
MPC5554
[1], [2] or on Freescale MPC5534 [3], [4]? Both of these embedded
PowerPC
controllers have the e200z6 core.
Is there anybody who is working
On Oct 21, 2009, at 10:52 AM, Aaron Pace wrote:
Hello,
For the e500 processors, it appears that the first 3 of 16 permanent
TLB entries are used to map lowmem. Are the other 13 ever used?
not right now. We intend to use them for hugetlbfs support.
- k
On Oct 21, 2009, at 10:19 AM, Németh Márton wrote:
Kumar Gala wrote:
On Oct 20, 2009, at 5:21 PM, Németh Márton wrote:
Hi Grant,
Hello List,
is there anybody who was successfully run Linux kernel on Freescale
MPC5554
[1], [2] or on Freescale MPC5534 [3], [4]? Both of these embedded
PowerPC
On Oct 22, 2009, at 12:58 AM, Michael Neuling wrote:
irqs_disabled_flags is #defined in linux/irqflags.h when
CONFIG_TRACE_IRQFLAGS_SUPPORT is enabled.
This fixes the case when someone needs to include both linux/
irqflags.h
and asm/hw_irq.h.
Signed-off-by: Michael Neuling
On Oct 22, 2009, at 9:08 AM, wilbur.chan wrote:
mpc85xx with sata harddisk,which has a rootfs on sda3.
I ' ve tried to use freescale's kernel image , which is togehther
with the mpc85xx board, to successfully mount the sda3 filesystem when
booting,
But when I used my own kernle, it
On Oct 24, 2009, at 2:25 AM, wilbur.chan wrote:
2009/10/22 Kumar Gala ga...@kernel.crashing.org:
Post the full kernel boot log.
- k
And this is the booting log of freescale linux kernel, which
successfully mount the sata disk (sda3) as the rootfs:
Can you also post your .config?
- k
On Nov 2, 2009, at 9:40 AM, hank peng wrote:
Kernel version is 2.6.30 and I have enabled fsl DMA engine during
configuring kernel. After system booted, I have seen only 38 DMA
interrupts, and no increase later when I am doing data transfer
through network.
So I wonder if mpc8548 had made use
On Nov 3, 2009, at 8:38 AM, hank peng wrote:
2009/11/3 Micha Nelissen mi...@neli.hopto.org:
hank peng wrote:
I remember normal memory copy can also be done (chosen by user) by
DMA
engine on IOP80331(Intel embedded cpu, xscale arch), so why ppc
platform didn't make use of DMA doing memory
On Nov 5, 2009, at 1:48 PM, Scott Wood wrote:
Kumar Gala wrote:
On Nov 5, 2009, at 10:57 AM, Scott Wood wrote:
Kumar Gala wrote:
On Sep 23, 2009, at 2:01 PM, Anton Vorontsov wrote:
Currently 83xx PMC driver clears deep_sleeping variable very
early,
before devices are resumed. This makes
On Nov 10, 2009, at 6:10 PM, Anton Vorontsov wrote:
Hi all,
Here are some fixes for the gianfar driver, patches on the way.
Thanks,
Acked-by: Kumar Gala ga...@kernel.crashing.org
- k
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On Jul 2, 2009, at 11:12 AM, Martyn Welch wrote:
Add support for NVRAM on GE Fanuc's PPC9A.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts |6 ++
arch/powerpc/configs/86xx/gef_ppc9a_defconfig |4 ++--
On Jul 2, 2009, at 11:12 AM, Martyn Welch wrote:
Add support for NVRAM on GE Fanuc's SBC310.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc310.dts |6 ++
arch/powerpc/configs/86xx/gef_sbc310_defconfig |4 ++--
On Jul 2, 2009, at 11:12 AM, Martyn Welch wrote:
This patch enables the NVRAM found on the GE Fanuc SBC610
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_sbc610.dts |6 ++
arch/powerpc/configs/86xx/gef_sbc610_defconfig |4 ++--
: Add power management support for MPC8610HPCD boards
powerpc/83xx: Add power management support for MPC83xx QE boards
powerpc/fsl: Make fsl_deep_sleep() usable w/ modules and non-83xx builds
Kumar Gala (3):
powerpc/85xx: Kconfig cleanup
powerpc/fsl-booke: Rework TLB CAM code
On Nov 5, 2009, at 9:02 AM, Kumar Gala wrote:
On Oct 16, 2009, at 11:44 AM, Anton Vorontsov wrote:
From: Jiang Yutang b14...@freescale.com
Split sata_fsl_softreset() into hard and soft resets to make
error-handling more efficient device and PMP detection more
reliable.
Also includes fix
On Nov 17, 2009, at 1:10 AM, Li Yang wrote:
Rather than the original intelligent way, we grant user more freedom.
This enables user to map cacheable memory not managed by Linux.
Signed-off-by: Li Yang le...@freescale.com
---
The only direct users of this function is fb_mmap() and /dev/mem
On Nov 19, 2009, at 7:51 AM, Kumar Gala wrote:
On Nov 5, 2009, at 9:02 AM, Kumar Gala wrote:
On Oct 16, 2009, at 11:44 AM, Anton Vorontsov wrote:
From: Jiang Yutang b14...@freescale.com
Split sata_fsl_softreset() into hard and soft resets to make
error-handling more efficient device
On Oct 21, 2009, at 7:50 AM, Vivek Mahajan wrote:
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its
On Nov 19, 2009, at 8:21 AM, Kumar Gala wrote:
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
platforms/85xx/Kconfig
index d3a975e..b6f23c3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -144,6 +144,15 @@ config SBC8560
On Nov 19, 2009, at 8:45 AM, Josh Boyer wrote:
On Wed, Nov 04, 2009 at 01:55:19PM -0500, Josh Boyer wrote:
Hi Ben,
Please pull the next branch of the 4xx tree to get the following
commits.
I have some other things in the middle of being worked that may or
may not
make it in time for
On Nov 19, 2009, at 11:45 AM, Scott Wood wrote:
On Thu, Nov 19, 2009 at 08:29:19AM -0600, Kumar Gala wrote:
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we
Add basic support for the P4080 DS reference board. None of the data
path devices (ethernet, crypto, pme) are support at this time.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p4080ds.dts| 554 ++
arch/powerpc/platforms/85xx
On Dec 1, 2009, at 11:04 AM, Scott Wood wrote:
Mahajan Vivek-B08308 wrote:
From: Wood Scott-B07421 Sent: Friday, November 20, 2009 11:09 PM
Cache-sram does not have any device tree entry since it is not a
hardware as such. Putting it under chosen can be another option.
I think, Scott
Ben, David,
If we want to support true 4G/4G split on ppc32 using the MSB of the
address to determine of the pgd_t is for hugetlbfs isn't going to
work. Since every pointer in the pgd_t - pud_t - pmd_t is point to
at least a 4K page I would think the low order 12-bits should always
be
On Dec 4, 2009, at 2:58 AM, Benjamin Herrenschmidt wrote:
On Fri, 2009-12-04 at 01:18 -0600, Kumar Gala wrote:
Ben, David,
If we want to support true 4G/4G split on ppc32 using the MSB of the
address to determine of the pgd_t is for hugetlbfs isn't going to
work. Since every pointer
On Dec 4, 2009, at 3:25 PM, Benjamin Herrenschmidt wrote:
On Fri, 2009-12-04 at 08:09 -0600, Kumar Gala wrote:
On Dec 4, 2009, at 2:58 AM, Benjamin Herrenschmidt wrote:
On Fri, 2009-12-04 at 01:18 -0600, Kumar Gala wrote:
Ben, David,
If we want to support true 4G/4G split on ppc32 using
On Dec 7, 2009, at 8:28 PM, David Gibson wrote:
On Mon, Dec 07, 2009 at 12:04:37PM +1100, Benjamin Herrenschmidt
wrote:
Even than, does that preclude the format I suggested? I'm assuming
that pgd_t/pud_t/pmd_t are always a double word so the low order 4-
bits should be 0 (on 64-bit),
On Dec 8, 2009, at 6:48 PM, Mark Ware wrote:
Port C interrupts can be either falling edge, or either edge.
Other external interrupts are either falling edge or active low.
Signed-Off-By: Mark Ware mw...@elphinstone.net
---
Changed in v2:
- Disallow rising edge only on Port C
On Dec 7, 2009, at 4:54 PM, Anton Vorontsov wrote:
It appears that we wrongly calculate dev_base for type1 config cycles.
The thing is: we shouldn't subtract hose-first_busno because PCI core
sets PCI primary, secondary and subordinate bus numbers, and PCIe
controller actually takes the
On Dec 6, 2009, at 5:32 AM, Sebastian Andrzej Siewior wrote:
Signed-off-by: Sebastian Andrzej Siewior sebast...@breakpoint.cc
---
Documentation/powerpc/dts-bindings/fsl/mpic.txt | 42 +++
1 files changed, 42 insertions(+), 0 deletions(-)
create mode 100644
On Nov 17, 2009, at 9:42 AM, Dmitry Eremin-Solenikov wrote:
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
Minding reviewing for me.
- k
diff --git
On Nov 16, 2009, at 7:58 AM, Dmitry Eremin-Solenikov wrote:
mpc8349 bears two GPIO controllers. Enable support for them.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/boot/dts/mpc8349emitx.dts | 18 ++
1 files changed, 18 insertions(+), 0
On Nov 16, 2009, at 7:58 AM, Dmitry Eremin-Solenikov wrote:
Add OF descriptions of EEPROM, two GPIO extenders and SPD hanging on I2C
on this board.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/boot/dts/mpc8349emitx.dts | 25 +
1
On Nov 16, 2009, at 2:51 PM, Dmitry Eremin-Solenikov wrote:
Describe all LocalBus chipselects on MPC8349E-MITX board. Also add flash
bindings.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/boot/dts/mpc8349emitx.dts | 21 -
1 files
On Nov 16, 2009, at 7:58 AM, Dmitry Eremin-Solenikov wrote:
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/boot/dts/mpc8349emitx.dts | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
applied to next
- k
On Dec 10, 2009, at 5:14 AM, Mark Ware wrote:
Port C interrupts can be either falling edge, or either edge.
Other external interrupts are either falling edge or active low.
Tested on a custom 8280 based board.
Signed-off-by: Mark Ware mw...@elphinstone.net
---
Changed in v3:
- Cosmetic
On Dec 10, 2009, at 5:14 AM, Mark Ware wrote:
Port C interrupts can be either falling edge, or either edge.
Other external interrupts are either falling edge or active low.
Tested on a custom 8280 based board.
Signed-off-by: Mark Ware mw...@elphinstone.net
---
Changed in v3:
- Cosmetic
On Dec 10, 2009, at 12:01 PM, Anton Vorontsov wrote:
- Add nodes for PMC and GTM controllers. GTM4 can be used as a wakeup
source;
- Add fsl,magic-packet properties to eTSEC nodes, i.e. wake-on-lan
support. Unlike MPC8313 processors, MPC8315 can resume from deep
sleep upon magic packet
On Dec 10, 2009, at 12:00 PM, Anton Vorontsov wrote:
We need to save SICRL, SICRH and SCCR registers on suspend, and restore
them on resume. Otherwise, we lose IO and clocks setup on MPC8315E-RDB
boards when ULPI USB PHY is used (non-POR setup).
Signed-off-by: Anton Vorontsov
On Dec 10, 2009, at 12:00 PM, Anton Vorontsov wrote:
Currently 83xx PMC driver clears deep_sleeping variable very early,
before devices are resumed. This makes fsl_deep_sleep() unusable in
drivers' resume() callback.
Sure, drivers can store fsl_deep_sleep() value on suspend and use
the
On Dec 1, 2009, at 2:48 PM, Peter Korsgaard wrote:
gpiolib returns -ENXIO if struct gpio_chip::to_irq isn't set, so it's
safe to always call.
Signed-off-by: Peter Korsgaard jac...@sunsite.dk
---
arch/powerpc/include/asm/gpio.h |5 +
1 files changed, 1 insertions(+), 4 deletions(-)
On Dec 9, 2009, at 1:33 AM, Peter Korsgaard wrote:
Peter == Peter Korsgaard jac...@sunsite.dk writes:
Comments?
Peter Signed-off-by: Peter Korsgaard jac...@sunsite.dk
Peter ---
Peter arch/powerpc/sysdev/mpc8xxx_gpio.c | 147
Peter 1 files
On Dec 10, 2009, at 9:57 AM, Dave Kleikamp wrote:
These patches implement an extention to the ptrace interface proposed by
Thiago Bauermann and the the PowerPC gdb team.
GDB intends to support the following hardware debug features of BookE
processors:
4 hardware breakpoints (IAC)
2
On Dec 10, 2009, at 9:57 AM, Dave Kleikamp wrote:
These patches implement an extention to the ptrace interface proposed by
Thiago Bauermann and the the PowerPC gdb team.
GDB intends to support the following hardware debug features of BookE
processors:
4 hardware breakpoints (IAC)
2
On Dec 10, 2009, at 9:57 AM, Dave Kleikamp wrote:
+#define DBCR1_IAC1US 0xC000 /* Instr Addr Cmp 1 Sup/User */
+#define DBCR1_IAC1ER 0x3000 /* Instr Addr Cmp 1 Eff/Real */
+#define DBCR1_IAC1ER_01 0x1000 /* reserved */
+#define DBCR1_IAC1ER_10
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